Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sm1_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.51 98.68 85.92 92.73 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 92.21 97.50 82.14 89.19 100.00



Module Instance : tb.dut.u_sm1_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_40

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_42

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_43

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_44

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_45

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_46

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_47

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_48

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_49

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_50

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_51

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_52

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_53

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_54

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_55

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_56

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.78 100.00 98.39 100.00 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
SCORELINE
95.96 100.00
tb.dut.u_sm1_28

SCORELINE
95.96 100.00
tb.dut.u_sm1_29

SCORELINE
100.00 100.00
tb.dut.u_sm1_30

SCORELINE
95.96 100.00
tb.dut.u_sm1_31

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
SCORELINE
96.97 100.00
tb.dut.u_sm1_33

SCORELINE
96.97 100.00
tb.dut.u_sm1_34

SCORELINE
96.97 100.00
tb.dut.u_sm1_36

SCORELINE
96.97 100.00
tb.dut.u_sm1_38

SCORELINE
96.97 100.00
tb.dut.u_sm1_40

SCORELINE
96.97 100.00
tb.dut.u_sm1_42

SCORELINE
96.97 100.00
tb.dut.u_sm1_43

SCORELINE
96.97 100.00
tb.dut.u_sm1_44

SCORELINE
96.97 100.00
tb.dut.u_sm1_45

SCORELINE
96.97 100.00
tb.dut.u_sm1_46

SCORELINE
96.97 100.00
tb.dut.u_sm1_47

SCORELINE
96.97 100.00
tb.dut.u_sm1_48

SCORELINE
96.97 100.00
tb.dut.u_sm1_49

SCORELINE
96.97 100.00
tb.dut.u_sm1_50

SCORELINE
96.97 100.00
tb.dut.u_sm1_51

SCORELINE
96.97 100.00
tb.dut.u_sm1_52

SCORELINE
96.97 100.00
tb.dut.u_sm1_53

SCORELINE
96.97 100.00
tb.dut.u_sm1_54

SCORELINE
96.97 100.00
tb.dut.u_sm1_55

SCORELINE
96.97 100.00
tb.dut.u_sm1_56

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
SCORECOND
95.96 87.88
tb.dut.u_sm1_28

SCORECOND
95.96 87.88
tb.dut.u_sm1_29

SCORECOND
95.96 87.88
tb.dut.u_sm1_31

SCORECOND
100.00 100.00
tb.dut.u_sm1_30

TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT4,T14,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT4,T14,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT4,T14,T25
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T14,T25
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
SCORECOND
96.97 90.91
tb.dut.u_sm1_33

SCORECOND
96.97 90.91
tb.dut.u_sm1_34

SCORECOND
96.97 90.91
tb.dut.u_sm1_43

SCORECOND
96.97 90.91
tb.dut.u_sm1_44

SCORECOND
96.97 90.91
tb.dut.u_sm1_45

SCORECOND
96.97 90.91
tb.dut.u_sm1_46

SCORECOND
96.97 90.91
tb.dut.u_sm1_47

SCORECOND
96.97 90.91
tb.dut.u_sm1_48

SCORECOND
96.97 90.91
tb.dut.u_sm1_49

SCORECOND
96.97 90.91
tb.dut.u_sm1_50

SCORECOND
96.97 90.91
tb.dut.u_sm1_51

SCORECOND
96.97 90.91
tb.dut.u_sm1_52

SCORECOND
96.97 90.91
tb.dut.u_sm1_53

SCORECOND
96.97 90.91
tb.dut.u_sm1_54

SCORECOND
96.97 90.91
tb.dut.u_sm1_55

SCORECOND
96.97 90.91
tb.dut.u_sm1_56

SCORECOND
96.97 90.91
tb.dut.u_sm1_36

SCORECOND
96.97 90.91
tb.dut.u_sm1_38

SCORECOND
96.97 90.91
tb.dut.u_sm1_40

SCORECOND
96.97 90.91
tb.dut.u_sm1_42

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Module : tlul_socket_m1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 2147483647 24146626 0 0
gen_host_fifo[1].idInRange 2147483647 12840216 0 0
gen_host_fifo[2].idInRange 1678074708 3778441 0 0
maxM 21600 21600 0 0
rspIdInRange 2147483647 164572251 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 24146626 0 0
T1 61824 402 0 0
T2 379992 615 0 0
T3 3922584 95262 0 0
T4 464328 10401 0 0
T7 969648 6486 0 0
T8 8073696 10516 0 0
T9 249120 998 0 0
T10 737304 3984 0 0
T11 4927752 20416 0 0
T12 2745480 118241 0 0
T13 0 8140 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 12840216 0 0
T1 61824 213 0 0
T2 379992 379 0 0
T3 3922584 55057 0 0
T4 464328 10783 0 0
T7 969648 2555 0 0
T8 8073696 4908 0 0
T9 249120 427 0 0
T10 737304 1884 0 0
T11 4927752 8446 0 0
T12 2745480 44488 0 0
T13 0 59023 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 1678074708 3778441 0 0
T1 10304 33 0 0
T2 63332 83 0 0
T3 653764 8048 0 0
T4 77388 0 0 0
T7 161608 1089 0 0
T8 1345616 3230 0 0
T9 41520 121 0 0
T10 122884 523 0 0
T11 821292 2587 0 0
T12 457580 18009 0 0
T13 0 35248 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 21600 21600 0 0
T1 24 24 0 0
T2 24 24 0 0
T3 24 24 0 0
T4 24 24 0 0
T7 24 24 0 0
T8 24 24 0 0
T9 24 24 0 0
T10 24 24 0 0
T11 24 24 0 0
T12 24 24 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 164572251 0 0
T1 61824 544 0 0
T2 379992 1706 0 0
T3 3922584 105526 0 0
T4 464328 10485 0 0
T7 969648 23216 0 0
T8 8073696 44616 0 0
T9 249120 2799 0 0
T10 737304 16721 0 0
T11 4927752 76931 0 0
T12 2745480 347007 0 0
T13 0 376269 0 0

Line Coverage for Instance : tb.dut.u_sm1_28
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_28
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 1744104 0 0
gen_host_fifo[1].idInRange 419518677 391764 0 0
gen_host_fifo[2].idInRange 419518677 522510 0 0
maxM 900 900 0 0
rspIdInRange 419518677 20731123 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 1744104 0 0
T1 2576 42 0 0
T2 15833 55 0 0
T3 163441 8808 0 0
T4 19347 321 0 0
T7 40402 688 0 0
T8 336404 184 0 0
T9 10380 49 0 0
T10 30721 337 0 0
T11 205323 1580 0 0
T12 114395 3757 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 391764 0 0
T1 2576 6 0 0
T2 15833 6 0 0
T3 163441 1260 0 0
T4 19347 0 0 0
T7 40402 82 0 0
T8 336404 5 0 0
T9 10380 13 0 0
T10 30721 61 0 0
T11 205323 281 0 0
T12 114395 23 0 0
T13 0 2007 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 522510 0 0
T1 2576 4 0 0
T2 15833 22 0 0
T3 163441 1267 0 0
T4 19347 0 0 0
T7 40402 200 0 0
T8 336404 699 0 0
T9 10380 6 0 0
T10 30721 101 0 0
T11 205323 284 0 0
T12 114395 1068 0 0
T13 0 3730 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 20731123 0 0
T1 2576 52 0 0
T2 15833 359 0 0
T3 163441 11017 0 0
T4 19347 1285 0 0
T7 40402 3406 0 0
T8 336404 7272 0 0
T9 10380 351 0 0
T10 30721 2172 0 0
T11 205323 9793 0 0
T12 114395 70938 0 0

Line Coverage for Instance : tb.dut.u_sm1_29
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_29
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 2013769 0 0
gen_host_fifo[1].idInRange 419518677 505139 0 0
gen_host_fifo[2].idInRange 419518677 645504 0 0
maxM 900 900 0 0
rspIdInRange 419518677 19729933 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 2013769 0 0
T1 2576 62 0 0
T2 15833 85 0 0
T3 163441 12636 0 0
T4 19347 226 0 0
T7 40402 774 0 0
T8 336404 979 0 0
T9 10380 86 0 0
T10 30721 391 0 0
T11 205323 1785 0 0
T12 114395 5270 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 505139 0 0
T1 2576 9 0 0
T2 15833 7 0 0
T3 163441 2813 0 0
T4 19347 0 0 0
T7 40402 108 0 0
T8 336404 4 0 0
T9 10380 26 0 0
T10 30721 105 0 0
T11 205323 286 0 0
T12 114395 1984 0 0
T13 0 1163 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 645504 0 0
T1 2576 12 0 0
T2 15833 3 0 0
T3 163441 2485 0 0
T4 19347 0 0 0
T7 40402 131 0 0
T8 336404 643 0 0
T9 10380 15 0 0
T10 30721 83 0 0
T11 205323 245 0 0
T12 114395 1340 0 0
T13 0 2631 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 19729933 0 0
T1 2576 68 0 0
T2 15833 276 0 0
T3 163441 11890 0 0
T4 19347 1237 0 0
T7 40402 3499 0 0
T8 336404 7388 0 0
T9 10380 521 0 0
T10 30721 2329 0 0
T11 205323 10066 0 0
T12 114395 70716 0 0

Line Coverage for Instance : tb.dut.u_sm1_31
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_31
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 1968151 0 0
gen_host_fifo[1].idInRange 419518677 452315 0 0
gen_host_fifo[2].idInRange 419518677 575574 0 0
maxM 900 900 0 0
rspIdInRange 419518677 18827547 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 1968151 0 0
T1 2576 69 0 0
T2 15833 46 0 0
T3 163441 12796 0 0
T4 19347 360 0 0
T7 40402 676 0 0
T8 336404 1239 0 0
T9 10380 87 0 0
T10 30721 395 0 0
T11 205323 1654 0 0
T12 114395 6269 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 452315 0 0
T1 2576 10 0 0
T2 15833 6 0 0
T3 163441 3130 0 0
T4 19347 0 0 0
T7 40402 66 0 0
T8 336404 8 0 0
T9 10380 22 0 0
T10 30721 79 0 0
T11 205323 259 0 0
T12 114395 229 0 0
T13 0 897 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 575574 0 0
T1 2576 6 0 0
T2 15833 19 0 0
T3 163441 2598 0 0
T4 19347 0 0 0
T7 40402 146 0 0
T8 336404 369 0 0
T9 10380 36 0 0
T10 30721 127 0 0
T11 205323 364 0 0
T12 114395 2226 0 0
T13 0 5172 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 18827547 0 0
T1 2576 67 0 0
T2 15833 242 0 0
T3 163441 11857 0 0
T4 19347 1466 0 0
T7 40402 3305 0 0
T8 336404 7002 0 0
T9 10380 514 0 0
T10 30721 2352 0 0
T11 205323 10302 0 0
T12 114395 75266 0 0

Line Coverage for Instance : tb.dut.u_sm1_33
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_33
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 299732 0 0
gen_host_fifo[1].idInRange 419518677 384432 0 0
maxM 900 900 0 0
rspIdInRange 419518677 3924965 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 299732 0 0
T1 2576 6 0 0
T2 15833 7 0 0
T3 163441 1806 0 0
T4 19347 0 0 0
T7 40402 75 0 0
T8 336404 5 0 0
T9 10380 11 0 0
T10 30721 56 0 0
T11 205323 240 0 0
T12 114395 1647 0 0
T13 0 96 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 384432 0 0
T1 2576 9 0 0
T2 15833 12 0 0
T3 163441 1701 0 0
T4 19347 0 0 0
T7 40402 95 0 0
T8 336404 9 0 0
T9 10380 31 0 0
T10 30721 55 0 0
T11 205323 234 0 0
T12 114395 614 0 0
T13 0 2143 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 3924965 0 0
T1 2576 14 0 0
T2 15833 23 0 0
T3 163441 2866 0 0
T4 19347 0 0 0
T7 40402 539 0 0
T8 336404 1474 0 0
T9 10380 71 0 0
T10 30721 363 0 0
T11 205323 1914 0 0
T12 114395 2032 0 0
T13 0 19833 0 0

Line Coverage for Instance : tb.dut.u_sm1_34
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_34
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 277434 0 0
gen_host_fifo[1].idInRange 419518677 345229 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4102813 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 277434 0 0
T1 2576 14 0 0
T2 15833 7 0 0
T3 163441 3093 0 0
T4 19347 0 0 0
T7 40402 60 0 0
T8 336404 9 0 0
T9 10380 11 0 0
T10 30721 30 0 0
T11 205323 208 0 0
T12 114395 24 0 0
T13 0 65 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 345229 0 0
T1 2576 6 0 0
T2 15833 16 0 0
T3 163441 2828 0 0
T4 19347 0 0 0
T7 40402 76 0 0
T8 336404 616 0 0
T9 10380 8 0 0
T10 30721 58 0 0
T11 205323 297 0 0
T12 114395 947 0 0
T13 0 1246 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4102813 0 0
T1 2576 17 0 0
T2 15833 12 0 0
T3 163441 3488 0 0
T4 19347 0 0 0
T7 40402 509 0 0
T8 336404 918 0 0
T9 10380 33 0 0
T10 30721 294 0 0
T11 205323 1590 0 0
T12 114395 1866 0 0
T13 0 23128 0 0

Line Coverage for Instance : tb.dut.u_sm1_36
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_36
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T8,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 786124 0 0
gen_host_fifo[1].idInRange 419518677 916423 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4532169 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 786124 0 0
T1 2576 12 0 0
T2 15833 7 0 0
T3 163441 4759 0 0
T4 19347 4263 0 0
T7 40402 114 0 0
T8 336404 8 0 0
T9 10380 14 0 0
T10 30721 49 0 0
T11 205323 257 0 0
T12 114395 3373 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 916423 0 0
T1 2576 13 0 0
T2 15833 8 0 0
T3 163441 4044 0 0
T4 19347 5609 0 0
T7 40402 122 0 0
T8 336404 7 0 0
T9 10380 10 0 0
T10 30721 55 0 0
T11 205323 362 0 0
T12 114395 4841 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4532169 0 0
T1 2576 13 0 0
T2 15833 15 0 0
T3 163441 2908 0 0
T4 19347 1046 0 0
T7 40402 472 0 0
T8 336404 2024 0 0
T9 10380 101 0 0
T10 30721 350 0 0
T11 205323 2006 0 0
T12 114395 3272 0 0

Line Coverage for Instance : tb.dut.u_sm1_38
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_38
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT9,T10,T11
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 761273 0 0
gen_host_fifo[1].idInRange 419518677 872312 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4378541 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 761273 0 0
T1 2576 19 0 0
T2 15833 23 0 0
T3 163441 1874 0 0
T4 19347 0 0 0
T7 40402 145 0 0
T8 336404 10 0 0
T9 10380 16 0 0
T10 30721 39 0 0
T11 205323 319 0 0
T12 114395 4208 0 0
T13 0 1795 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 872312 0 0
T1 2576 8 0 0
T2 15833 13 0 0
T3 163441 2041 0 0
T4 19347 0 0 0
T7 40402 132 0 0
T8 336404 1 0 0
T9 10380 14 0 0
T10 30721 79 0 0
T11 205323 319 0 0
T12 114395 5823 0 0
T13 0 1720 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4378541 0 0
T1 2576 17 0 0
T2 15833 25 0 0
T3 163441 2293 0 0
T4 19347 0 0 0
T7 40402 453 0 0
T8 336404 1610 0 0
T9 10380 51 0 0
T10 30721 498 0 0
T11 205323 1998 0 0
T12 114395 3781 0 0
T13 0 26216 0 0

Line Coverage for Instance : tb.dut.u_sm1_40
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_40
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T10,T13
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 672158 0 0
gen_host_fifo[1].idInRange 419518677 798195 0 0
maxM 900 900 0 0
rspIdInRange 419518677 3722210 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 672158 0 0
T1 2576 22 0 0
T2 15833 5 0 0
T3 163441 6741 0 0
T4 19347 0 0 0
T7 40402 60 0 0
T8 336404 109 0 0
T9 10380 9 0 0
T10 30721 34 0 0
T11 205323 278 0 0
T12 114395 3773 0 0
T13 0 57 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 798195 0 0
T1 2576 31 0 0
T2 15833 8 0 0
T3 163441 6495 0 0
T4 19347 0 0 0
T7 40402 122 0 0
T8 336404 148 0 0
T9 10380 82 0 0
T10 30721 70 0 0
T11 205323 306 0 0
T12 114395 2639 0 0
T13 0 3844 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 3722210 0 0
T1 2576 18 0 0
T2 15833 26 0 0
T3 163441 3769 0 0
T4 19347 0 0 0
T7 40402 433 0 0
T8 336404 329 0 0
T9 10380 36 0 0
T10 30721 291 0 0
T11 205323 1920 0 0
T12 114395 1018 0 0
T13 0 17318 0 0

Line Coverage for Instance : tb.dut.u_sm1_42
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_42
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 659808 0 0
gen_host_fifo[1].idInRange 419518677 804639 0 0
maxM 900 900 0 0
rspIdInRange 419518677 5120815 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 659808 0 0
T1 2576 8 0 0
T2 15833 46 0 0
T3 163441 1175 0 0
T4 19347 0 0 0
T7 40402 66 0 0
T8 336404 459 0 0
T9 10380 9 0 0
T10 30721 35 0 0
T11 205323 432 0 0
T12 114395 32 0 0
T13 0 397 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 804639 0 0
T1 2576 9 0 0
T2 15833 6 0 0
T3 163441 1187 0 0
T4 19347 0 0 0
T7 40402 105 0 0
T8 336404 3 0 0
T9 10380 18 0 0
T10 30721 94 0 0
T11 205323 646 0 0
T12 114395 471 0 0
T13 0 5186 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 5120815 0 0
T1 2576 17 0 0
T2 15833 21 0 0
T3 163441 1917 0 0
T4 19347 0 0 0
T7 40402 439 0 0
T8 336404 6 0 0
T9 10380 85 0 0
T10 30721 364 0 0
T11 205323 2427 0 0
T12 114395 2953 0 0
T13 0 25180 0 0

Line Coverage for Instance : tb.dut.u_sm1_43
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_43
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 277198 0 0
gen_host_fifo[1].idInRange 419518677 381090 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4688909 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 277198 0 0
T1 2576 15 0 0
T2 15833 6 0 0
T3 163441 2208 0 0
T4 19347 0 0 0
T7 40402 64 0 0
T8 336404 4 0 0
T9 10380 25 0 0
T10 30721 59 0 0
T11 205323 232 0 0
T12 114395 35 0 0
T13 0 959 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 381090 0 0
T1 2576 8 0 0
T2 15833 3 0 0
T3 163441 2092 0 0
T4 19347 0 0 0
T7 40402 111 0 0
T8 336404 5 0 0
T9 10380 6 0 0
T10 30721 64 0 0
T11 205323 245 0 0
T12 114395 781 0 0
T13 0 1279 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4688909 0 0
T1 2576 20 0 0
T2 15833 11 0 0
T3 163441 3276 0 0
T4 19347 0 0 0
T7 40402 436 0 0
T8 336404 347 0 0
T9 10380 37 0 0
T10 30721 431 0 0
T11 205323 1868 0 0
T12 114395 3215 0 0
T13 0 19668 0 0

Line Coverage for Instance : tb.dut.u_sm1_44
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_44
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 263246 0 0
gen_host_fifo[1].idInRange 419518677 348094 0 0
maxM 900 900 0 0
rspIdInRange 419518677 3284752 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 263246 0 0
T1 2576 7 0 0
T2 15833 29 0 0
T3 163441 1324 0 0
T4 19347 0 0 0
T7 40402 79 0 0
T8 336404 6 0 0
T9 10380 7 0 0
T10 30721 50 0 0
T11 205323 189 0 0
T12 114395 577 0 0
T13 0 75 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 348094 0 0
T1 2576 11 0 0
T2 15833 44 0 0
T3 163441 1318 0 0
T4 19347 0 0 0
T7 40402 112 0 0
T8 336404 585 0 0
T9 10380 11 0 0
T10 30721 58 0 0
T11 205323 204 0 0
T12 114395 1333 0 0
T13 0 2810 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 3284752 0 0
T1 2576 17 0 0
T2 15833 49 0 0
T3 163441 2236 0 0
T4 19347 0 0 0
T7 40402 529 0 0
T8 336404 746 0 0
T9 10380 29 0 0
T10 30721 364 0 0
T11 205323 1518 0 0
T12 114395 4509 0 0
T13 0 24272 0 0

Line Coverage for Instance : tb.dut.u_sm1_45
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_45
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 269927 0 0
gen_host_fifo[1].idInRange 419518677 355538 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4703638 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 269927 0 0
T1 2576 9 0 0
T2 15833 11 0 0
T3 163441 2307 0 0
T4 19347 0 0 0
T7 40402 47 0 0
T8 336404 4 0 0
T9 10380 9 0 0
T10 30721 54 0 0
T11 205323 180 0 0
T12 114395 961 0 0
T13 0 57 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 355538 0 0
T1 2576 6 0 0
T2 15833 22 0 0
T3 163441 2107 0 0
T4 19347 0 0 0
T7 40402 81 0 0
T8 336404 1 0 0
T9 10380 8 0 0
T10 30721 112 0 0
T11 205323 250 0 0
T12 114395 572 0 0
T13 0 3317 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4703638 0 0
T1 2576 15 0 0
T2 15833 37 0 0
T3 163441 3386 0 0
T4 19347 0 0 0
T7 40402 407 0 0
T8 336404 5 0 0
T9 10380 33 0 0
T10 30721 362 0 0
T11 205323 1686 0 0
T12 114395 3408 0 0
T13 0 18793 0 0

Line Coverage for Instance : tb.dut.u_sm1_46
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_46
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 284910 0 0
gen_host_fifo[1].idInRange 419518677 389783 0 0
maxM 900 900 0 0
rspIdInRange 419518677 3908456 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 284910 0 0
T1 2576 9 0 0
T2 15833 5 0 0
T3 163441 1961 0 0
T4 19347 1169 0 0
T7 40402 57 0 0
T8 336404 6 0 0
T9 10380 13 0 0
T10 30721 34 0 0
T11 205323 214 0 0
T12 114395 840 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 389783 0 0
T1 2576 12 0 0
T2 15833 7 0 0
T3 163441 1555 0 0
T4 19347 1283 0 0
T7 40402 80 0 0
T8 336404 4 0 0
T9 10380 7 0 0
T10 30721 80 0 0
T11 205323 258 0 0
T12 114395 1388 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 3908456 0 0
T1 2576 20 0 0
T2 15833 21 0 0
T3 163441 2314 0 0
T4 19347 2254 0 0
T7 40402 492 0 0
T8 336404 1163 0 0
T9 10380 40 0 0
T10 30721 320 0 0
T11 205323 1649 0 0
T12 114395 3033 0 0

Line Coverage for Instance : tb.dut.u_sm1_47
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_47
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 319814 0 0
gen_host_fifo[1].idInRange 419518677 401743 0 0
maxM 900 900 0 0
rspIdInRange 419518677 3693473 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 319814 0 0
T1 2576 9 0 0
T2 15833 11 0 0
T3 163441 4037 0 0
T4 19347 0 0 0
T7 40402 70 0 0
T8 336404 6 0 0
T9 10380 4 0 0
T10 30721 44 0 0
T11 205323 202 0 0
T12 114395 1358 0 0
T13 0 651 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 401743 0 0
T1 2576 2 0 0
T2 15833 16 0 0
T3 163441 3242 0 0
T4 19347 0 0 0
T7 40402 95 0 0
T8 336404 130 0 0
T9 10380 10 0 0
T10 30721 39 0 0
T11 205323 299 0 0
T12 114395 1617 0 0
T13 0 344 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 3693473 0 0
T1 2576 10 0 0
T2 15833 32 0 0
T3 163441 4220 0 0
T4 19347 0 0 0
T7 40402 499 0 0
T8 336404 41 0 0
T9 10380 16 0 0
T10 30721 395 0 0
T11 205323 1678 0 0
T12 114395 3513 0 0
T13 0 28101 0 0

Line Coverage for Instance : tb.dut.u_sm1_48
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_48
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 292723 0 0
gen_host_fifo[1].idInRange 419518677 370576 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4253777 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 292723 0 0
T1 2576 5 0 0
T2 15833 17 0 0
T3 163441 2155 0 0
T4 19347 0 0 0
T7 40402 79 0 0
T8 336404 5 0 0
T9 10380 14 0 0
T10 30721 57 0 0
T11 205323 223 0 0
T12 114395 201 0 0
T13 0 52 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 370576 0 0
T1 2576 6 0 0
T2 15833 7 0 0
T3 163441 1850 0 0
T4 19347 0 0 0
T7 40402 67 0 0
T8 336404 888 0 0
T9 10380 15 0 0
T10 30721 53 0 0
T11 205323 280 0 0
T12 114395 327 0 0
T13 0 436 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4253777 0 0
T1 2576 11 0 0
T2 15833 26 0 0
T3 163441 2662 0 0
T4 19347 0 0 0
T7 40402 561 0 0
T8 336404 443 0 0
T9 10380 49 0 0
T10 30721 453 0 0
T11 205323 1790 0 0
T12 114395 2386 0 0
T13 0 18439 0 0

Line Coverage for Instance : tb.dut.u_sm1_49
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_49
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 311914 0 0
gen_host_fifo[1].idInRange 419518677 393211 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4782304 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 311914 0 0
T1 2576 10 0 0
T2 15833 4 0 0
T3 163441 1430 0 0
T4 19347 0 0 0
T7 40402 55 0 0
T8 336404 263 0 0
T9 10380 5 0 0
T10 30721 49 0 0
T11 205323 224 0 0
T12 114395 24 0 0
T13 0 1344 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 393211 0 0
T1 2576 12 0 0
T2 15833 7 0 0
T3 163441 1276 0 0
T4 19347 0 0 0
T7 40402 46 0 0
T8 336404 566 0 0
T9 10380 7 0 0
T10 30721 52 0 0
T11 205323 227 0 0
T12 114395 209 0 0
T13 0 190 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4782304 0 0
T1 2576 21 0 0
T2 15833 11 0 0
T3 163441 2286 0 0
T4 19347 0 0 0
T7 40402 478 0 0
T8 336404 201 0 0
T9 10380 40 0 0
T10 30721 456 0 0
T11 205323 1941 0 0
T12 114395 1519 0 0
T13 0 21229 0 0

Line Coverage for Instance : tb.dut.u_sm1_50
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_50
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T10,T11
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 303418 0 0
gen_host_fifo[1].idInRange 419518677 388905 0 0
maxM 900 900 0 0
rspIdInRange 419518677 5239412 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 303418 0 0
T1 2576 8 0 0
T2 15833 3 0 0
T3 163441 3783 0 0
T4 19347 0 0 0
T7 40402 36 0 0
T8 336404 7 0 0
T9 10380 22 0 0
T10 30721 63 0 0
T11 205323 194 0 0
T12 114395 1482 0 0
T13 0 64 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 388905 0 0
T1 2576 14 0 0
T2 15833 6 0 0
T3 163441 3123 0 0
T4 19347 0 0 0
T7 40402 72 0 0
T8 336404 296 0 0
T9 10380 9 0 0
T10 30721 71 0 0
T11 205323 242 0 0
T12 114395 1691 0 0
T13 0 446 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 5239412 0 0
T1 2576 22 0 0
T2 15833 10 0 0
T3 163441 3623 0 0
T4 19347 0 0 0
T7 40402 348 0 0
T8 336404 14 0 0
T9 10380 61 0 0
T10 30721 499 0 0
T11 205323 1686 0 0
T12 114395 6682 0 0
T13 0 22292 0 0

Line Coverage for Instance : tb.dut.u_sm1_51
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_51
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 324405 0 0
gen_host_fifo[1].idInRange 419518677 406900 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4016626 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 324405 0 0
T1 2576 2 0 0
T2 15833 9 0 0
T3 163441 1050 0 0
T4 19347 0 0 0
T7 40402 89 0 0
T8 336404 2 0 0
T9 10380 29 0 0
T10 30721 44 0 0
T11 205323 244 0 0
T12 114395 29 0 0
T13 0 562 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 406900 0 0
T1 2576 3 0 0
T2 15833 6 0 0
T3 163441 998 0 0
T4 19347 0 0 0
T7 40402 69 0 0
T8 336404 2 0 0
T9 10380 18 0 0
T10 30721 93 0 0
T11 205323 310 0 0
T12 114395 391 0 0
T13 0 972 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4016626 0 0
T1 2576 5 0 0
T2 15833 35 0 0
T3 163441 1978 0 0
T4 19347 0 0 0
T7 40402 494 0 0
T8 336404 83 0 0
T9 10380 73 0 0
T10 30721 334 0 0
T11 205323 1893 0 0
T12 114395 3053 0 0
T13 0 24145 0 0

Line Coverage for Instance : tb.dut.u_sm1_52
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_52
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 325498 0 0
gen_host_fifo[1].idInRange 419518677 420070 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4178386 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 325498 0 0
T1 2576 2 0 0
T2 15833 10 0 0
T3 163441 1483 0 0
T4 19347 0 0 0
T7 40402 64 0 0
T8 336404 3 0 0
T9 10380 11 0 0
T10 30721 66 0 0
T11 205323 203 0 0
T12 114395 32 0 0
T13 0 363 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 420070 0 0
T1 2576 6 0 0
T2 15833 7 0 0
T3 163441 1332 0 0
T4 19347 0 0 0
T7 40402 119 0 0
T8 336404 4 0 0
T9 10380 11 0 0
T10 30721 39 0 0
T11 205323 259 0 0
T12 114395 2151 0 0
T13 0 2578 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4178386 0 0
T1 2576 8 0 0
T2 15833 46 0 0
T3 163441 2386 0 0
T4 19347 0 0 0
T7 40402 550 0 0
T8 336404 1335 0 0
T9 10380 47 0 0
T10 30721 417 0 0
T11 205323 1554 0 0
T12 114395 2663 0 0
T13 0 19753 0 0

Line Coverage for Instance : tb.dut.u_sm1_53
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_53
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 268255 0 0
gen_host_fifo[1].idInRange 419518677 352038 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4524746 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 268255 0 0
T1 2576 8 0 0
T2 15833 10 0 0
T3 163441 2325 0 0
T4 19347 0 0 0
T7 40402 53 0 0
T8 336404 6 0 0
T9 10380 10 0 0
T10 30721 58 0 0
T11 205323 326 0 0
T12 114395 515 0 0
T13 0 360 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 352038 0 0
T1 2576 6 0 0
T2 15833 3 0 0
T3 163441 1954 0 0
T4 19347 0 0 0
T7 40402 91 0 0
T8 336404 4 0 0
T9 10380 7 0 0
T10 30721 74 0 0
T11 205323 425 0 0
T12 114395 1162 0 0
T13 0 1808 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4524746 0 0
T1 2576 14 0 0
T2 15833 32 0 0
T3 163441 2840 0 0
T4 19347 0 0 0
T7 40402 461 0 0
T8 336404 1215 0 0
T9 10380 33 0 0
T10 30721 376 0 0
T11 205323 2180 0 0
T12 114395 1557 0 0
T13 0 20800 0 0

Line Coverage for Instance : tb.dut.u_sm1_54
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_54
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 333636 0 0
gen_host_fifo[1].idInRange 419518677 423542 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4306897 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 333636 0 0
T1 2576 11 0 0
T2 15833 2 0 0
T3 163441 2768 0 0
T4 19347 0 0 0
T7 40402 75 0 0
T8 336404 6 0 0
T9 10380 10 0 0
T10 30721 44 0 0
T11 205323 187 0 0
T12 114395 31 0 0
T13 0 890 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 423542 0 0
T1 2576 2 0 0
T2 15833 13 0 0
T3 163441 2482 0 0
T4 19347 0 0 0
T7 40402 104 0 0
T8 336404 195 0 0
T9 10380 12 0 0
T10 30721 82 0 0
T11 205323 244 0 0
T12 114395 314 0 0
T13 0 857 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4306897 0 0
T1 2576 11 0 0
T2 15833 15 0 0
T3 163441 3880 0 0
T4 19347 0 0 0
T7 40402 530 0 0
T8 336404 747 0 0
T9 10380 45 0 0
T10 30721 402 0 0
T11 205323 1483 0 0
T12 114395 2889 0 0
T13 0 21979 0 0

Line Coverage for Instance : tb.dut.u_sm1_55
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_55
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T9,T10
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 267834 0 0
gen_host_fifo[1].idInRange 419518677 353407 0 0
maxM 900 900 0 0
rspIdInRange 419518677 4163390 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 267834 0 0
T1 2576 5 0 0
T2 15833 9 0 0
T3 163441 2322 0 0
T4 19347 0 0 0
T7 40402 138 0 0
T8 336404 5 0 0
T9 10380 16 0 0
T10 30721 45 0 0
T11 205323 231 0 0
T12 114395 761 0 0
T13 0 353 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 353407 0 0
T1 2576 11 0 0
T2 15833 8 0 0
T3 163441 1918 0 0
T4 19347 0 0 0
T7 40402 88 0 0
T8 336404 6 0 0
T9 10380 14 0 0
T10 30721 78 0 0
T11 205323 264 0 0
T12 114395 551 0 0
T13 0 265 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 4163390 0 0
T1 2576 15 0 0
T2 15833 21 0 0
T3 163441 2836 0 0
T4 19347 0 0 0
T7 40402 600 0 0
T8 336404 28 0 0
T9 10380 55 0 0
T10 30721 363 0 0
T11 205323 1831 0 0
T12 114395 1757 0 0
T13 0 25123 0 0

Line Coverage for Instance : tb.dut.u_sm1_56
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_56
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 315836 0 0
gen_host_fifo[1].idInRange 419518677 403698 0 0
maxM 900 900 0 0
rspIdInRange 419518677 3805742 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 315836 0 0
T1 2576 3 0 0
T2 15833 4 0 0
T3 163441 2658 0 0
T4 19347 2743 0 0
T7 40402 41 0 0
T8 336404 4 0 0
T9 10380 12 0 0
T10 30721 31 0 0
T11 205323 188 0 0
T12 114395 649 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 403698 0 0
T1 2576 3 0 0
T2 15833 6 0 0
T3 163441 2364 0 0
T4 19347 3891 0 0
T7 40402 74 0 0
T8 336404 254 0 0
T9 10380 8 0 0
T10 30721 49 0 0
T11 205323 255 0 0
T12 114395 720 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 3805742 0 0
T1 2576 6 0 0
T2 15833 17 0 0
T3 163441 3744 0 0
T4 19347 1988 0 0
T7 40402 400 0 0
T8 336404 310 0 0
T9 10380 44 0 0
T10 30721 369 0 0
T11 205323 1612 0 0
T12 114395 2003 0 0

Line Coverage for Instance : tb.dut.u_sm1_30
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_30
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT4,T14,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT4,T14,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT4,T14,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110CoveredT4,T14,T25
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT4,T14,T25
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T14,T25
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 419518677 10805459 0 0
gen_host_fifo[1].idInRange 419518677 1981173 0 0
gen_host_fifo[2].idInRange 419518677 2034853 0 0
maxM 900 900 0 0
rspIdInRange 419518677 19951627 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 10805459 0 0
T1 2576 45 0 0
T2 15833 204 0 0
T3 163441 9763 0 0
T4 19347 1319 0 0
T7 40402 2881 0 0
T8 336404 7187 0 0
T9 10380 519 0 0
T10 30721 1920 0 0
T11 205323 10626 0 0
T12 114395 82393 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 1981173 0 0
T1 2576 10 0 0
T2 15833 142 0 0
T3 163441 1947 0 0
T4 19347 0 0 0
T7 40402 438 0 0
T8 336404 1167 0 0
T9 10380 60 0 0
T10 30721 284 0 0
T11 205323 1694 0 0
T12 114395 13710 0 0
T13 0 25515 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 2034853 0 0
T1 2576 11 0 0
T2 15833 39 0 0
T3 163441 1698 0 0
T4 19347 0 0 0
T7 40402 612 0 0
T8 336404 1519 0 0
T9 10380 64 0 0
T10 30721 212 0 0
T11 205323 1694 0 0
T12 114395 13375 0 0
T13 0 23715 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 419518677 19951627 0 0
T1 2576 66 0 0
T2 15833 344 0 0
T3 163441 11854 0 0
T4 19347 1209 0 0
T7 40402 3376 0 0
T8 336404 9915 0 0
T9 10380 434 0 0
T10 30721 2167 0 0
T11 205323 10546 0 0
T12 114395 72978 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%