Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8316605	0	0
GntImpliesValid_A	2147483647	8316605	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8316605	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	462395401	0	0
ReadyAndValidImplyGrant_A	2147483647	8316605	0	0
ReqAndReadyImplyGrant_A	2147483647	8316605	0	0
ReqImpliesValid_A	2147483647	35730178	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	55214	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8316605	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61824	60624	0	0
T2	379992	377856	0	0
T3	3922584	3913800	0	0
T4	464328	462312	0	0
T7	969648	968808	0	0
T8	8073696	8073192	0	0
T9	249120	248736	0	0
T10	737304	736872	0	0
T11	4927752	4916016	0	0
T12	2745480	2745336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8316605	0	0
T1	61824	544	0	0
T2	379992	488	0	0
T3	3922584	105550	0	0
T4	464328	1836	0	0
T7	969648	4144	0	0
T8	8073696	362	0	0
T9	249120	784	0	0
T10	737304	2945	0	0
T11	4927752	14896	0	0
T12	2745480	2397	0	0
T13	0	2200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8316605	0	0
T1	61824	544	0	0
T2	379992	488	0	0
T3	3922584	105550	0	0
T4	464328	1836	0	0
T7	969648	4144	0	0
T8	8073696	362	0	0
T9	249120	784	0	0
T10	737304	2945	0	0
T11	4927752	14896	0	0
T12	2745480	2397	0	0
T13	0	2200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61824	60624	0	0
T2	379992	377856	0	0
T3	3922584	3913800	0	0
T4	464328	462312	0	0
T7	969648	968808	0	0
T8	8073696	8073192	0	0
T9	249120	248736	0	0
T10	737304	736872	0	0
T11	4927752	4916016	0	0
T12	2745480	2745336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61824	60624	0	0
T2	379992	377856	0	0
T3	3922584	3913800	0	0
T4	464328	462312	0	0
T7	969648	968808	0	0
T8	8073696	8073192	0	0
T9	249120	248736	0	0
T10	737304	736872	0	0
T11	4927752	4916016	0	0
T12	2745480	2745336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8316605	0	0
T1	61824	544	0	0
T2	379992	488	0	0
T3	3922584	105550	0	0
T4	464328	1836	0	0
T7	969648	4144	0	0
T8	8073696	362	0	0
T9	249120	784	0	0
T10	737304	2945	0	0
T11	4927752	14896	0	0
T12	2745480	2397	0	0
T13	0	2200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	462395401	0	0
T1	61824	711	0	0
T2	379992	19248	0	0
T3	3922584	86931	0	0
T4	464328	21653	0	0
T7	969648	61937	0	0
T8	8073696	430744	0	0
T9	249120	14143	0	0
T10	737304	44979	0	0
T11	4927752	280465	0	0
T12	2745480	1009612	0	0
T13	0	155086	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8316605	0	0
T1	61824	544	0	0
T2	379992	488	0	0
T3	3922584	105550	0	0
T4	464328	1836	0	0
T7	969648	4144	0	0
T8	8073696	362	0	0
T9	249120	784	0	0
T10	737304	2945	0	0
T11	4927752	14896	0	0
T12	2745480	2397	0	0
T13	0	2200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8316605	0	0
T1	61824	544	0	0
T2	379992	488	0	0
T3	3922584	105550	0	0
T4	464328	1836	0	0
T7	969648	4144	0	0
T8	8073696	362	0	0
T9	249120	784	0	0
T10	737304	2945	0	0
T11	4927752	14896	0	0
T12	2745480	2397	0	0
T13	0	2200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35730178	0	0
T1	61824	648	0	0
T2	379992	1077	0	0
T3	3922584	133756	0	0
T4	464328	14893	0	0
T7	969648	9935	0	0
T8	8073696	18654	0	0
T9	249120	1537	0	0
T10	737304	6298	0	0
T11	4927752	31121	0	0
T12	2745480	175823	0	0
T13	0	37581	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55214	0	21600
T3	326882	1123	0	2
T4	38694	0	0	2
T7	80804	1	0	2
T8	672808	0	0	2
T9	20760	0	0	2
T10	61442	0	0	2
T11	410646	2	0	2
T12	228790	0	0	2
T13	419610	0	0	2
T14	0	7	0	0
T15	0	7	0	0
T16	0	26	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	0	8	0	0
T20	0	440	0	0
T21	0	12	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	520858	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61824	60624	0	0
T2	379992	377856	0	0
T3	3922584	3913800	0	0
T4	464328	462312	0	0
T7	969648	968808	0	0
T8	8073696	8073192	0	0
T9	249120	248736	0	0
T10	737304	736872	0	0
T11	4927752	4916016	0	0
T12	2745480	2745336	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8316605	0	0
T1	61824	544	0	0
T2	379992	488	0	0
T3	3922584	105550	0	0
T4	464328	1836	0	0
T7	969648	4144	0	0
T8	8073696	362	0	0
T9	249120	784	0	0
T10	737304	2945	0	0
T11	4927752	14896	0	0
T12	2745480	2397	0	0
T13	0	2200	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	938707	0	0
GntImpliesValid_A	419518677	938707	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	938707	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	12863621	0	0
ReadyAndValidImplyGrant_A	419518677	938707	0	0
ReqAndReadyImplyGrant_A	419518677	938707	0	0
ReqImpliesValid_A	419518677	2672718	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	938707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	938707	0	0
T1	2576	68	0	0
T2	15833	45	0	0
T3	163441	11890	0	0
T4	19347	156	0	0
T7	40402	512	0	0
T8	336404	42	0	0
T9	10380	92	0	0
T10	30721	317	0	0
T11	205323	1587	0	0
T12	114395	249	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	938707	0	0
T1	2576	68	0	0
T2	15833	45	0	0
T3	163441	11890	0	0
T4	19347	156	0	0
T7	40402	512	0	0
T8	336404	42	0	0
T9	10380	92	0	0
T10	30721	317	0	0
T11	205323	1587	0	0
T12	114395	249	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	938707	0	0
T1	2576	68	0	0
T2	15833	45	0	0
T3	163441	11890	0	0
T4	19347	156	0	0
T7	40402	512	0	0
T8	336404	42	0	0
T9	10380	92	0	0
T10	30721	317	0	0
T11	205323	1587	0	0
T12	114395	249	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	12863621	0	0
T1	2576	54	0	0
T2	15833	289	0	0
T3	163441	8564	0	0
T4	19347	1202	0	0
T7	40402	3681	0	0
T8	336404	15485	0	0
T9	10380	644	0	0
T10	30721	2332	0	0
T11	205323	11889	0	0
T12	114395	75615	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	938707	0	0
T1	2576	68	0	0
T2	15833	45	0	0
T3	163441	11890	0	0
T4	19347	156	0	0
T7	40402	512	0	0
T8	336404	42	0	0
T9	10380	92	0	0
T10	30721	317	0	0
T11	205323	1587	0	0
T12	114395	249	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	938707	0	0
T1	2576	68	0	0
T2	15833	45	0	0
T3	163441	11890	0	0
T4	19347	156	0	0
T7	40402	512	0	0
T8	336404	42	0	0
T9	10380	92	0	0
T10	30721	317	0	0
T11	205323	1587	0	0
T12	114395	249	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	2672718	0	0
T1	2576	83	0	0
T2	15833	95	0	0
T3	163441	15229	0	0
T4	19347	226	0	0
T7	40402	981	0	0
T8	336404	1626	0	0
T9	10380	127	0	0
T10	30721	567	0	0
T11	205323	2313	0	0
T12	114395	8350	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	938707	0	0
T1	2576	68	0	0
T2	15833	45	0	0
T3	163441	11890	0	0
T4	19347	156	0	0
T7	40402	512	0	0
T8	336404	42	0	0
T9	10380	92	0	0
T10	30721	317	0	0
T11	205323	1587	0	0
T12	114395	249	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	922365	0	0
GntImpliesValid_A	419518677	922365	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	922365	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	12975293	0	0
ReadyAndValidImplyGrant_A	419518677	922365	0	0
ReqAndReadyImplyGrant_A	419518677	922365	0	0
ReqImpliesValid_A	419518677	2580761	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	922365	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922365	0	0
T1	2576	67	0	0
T2	15833	41	0	0
T3	163441	11859	0	0
T4	19347	184	0	0
T7	40402	481	0	0
T8	336404	42	0	0
T9	10380	94	0	0
T10	30721	333	0	0
T11	205323	1654	0	0
T12	114395	263	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922365	0	0
T1	2576	67	0	0
T2	15833	41	0	0
T3	163441	11859	0	0
T4	19347	184	0	0
T7	40402	481	0	0
T8	336404	42	0	0
T9	10380	94	0	0
T10	30721	333	0	0
T11	205323	1654	0	0
T12	114395	263	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922365	0	0
T1	2576	67	0	0
T2	15833	41	0	0
T3	163441	11859	0	0
T4	19347	184	0	0
T7	40402	481	0	0
T8	336404	42	0	0
T9	10380	94	0	0
T10	30721	333	0	0
T11	205323	1654	0	0
T12	114395	263	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	12975293	0	0
T1	2576	50	0	0
T2	15833	274	0	0
T3	163441	8461	0	0
T4	19347	1423	0	0
T7	40402	3391	0	0
T8	336404	13235	0	0
T9	10380	773	0	0
T10	30721	2377	0	0
T11	205323	11896	0	0
T12	114395	91548	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922365	0	0
T1	2576	67	0	0
T2	15833	41	0	0
T3	163441	11859	0	0
T4	19347	184	0	0
T7	40402	481	0	0
T8	336404	42	0	0
T9	10380	94	0	0
T10	30721	333	0	0
T11	205323	1654	0	0
T12	114395	263	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922365	0	0
T1	2576	67	0	0
T2	15833	41	0	0
T3	163441	11859	0	0
T4	19347	184	0	0
T7	40402	481	0	0
T8	336404	42	0	0
T9	10380	94	0	0
T10	30721	333	0	0
T11	205323	1654	0	0
T12	114395	263	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	2580761	0	0
T1	2576	85	0	0
T2	15833	71	0	0
T3	163441	15269	0	0
T4	19347	360	0	0
T7	40402	887	0	0
T8	336404	1616	0	0
T9	10380	145	0	0
T10	30721	591	0	0
T11	205323	2273	0	0
T12	114395	8724	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922365	0	0
T1	2576	67	0	0
T2	15833	41	0	0
T3	163441	11859	0	0
T4	19347	184	0	0
T7	40402	481	0	0
T8	336404	42	0	0
T9	10380	94	0	0
T10	30721	333	0	0
T11	205323	1654	0	0
T12	114395	263	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	232775	0	0
GntImpliesValid_A	419518677	232775	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	232775	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3180716	0	0
ReadyAndValidImplyGrant_A	419518677	232775	0	0
ReqAndReadyImplyGrant_A	419518677	232775	0	0
ReqImpliesValid_A	419518677	575158	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	232775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232775	0	0
T1	2576	14	0	0
T2	15833	19	0	0
T3	163441	2867	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	14	0	0
T9	10380	28	0	0
T10	30721	81	0	0
T11	205323	419	0	0
T12	114395	76	0	0
T13	0	126	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232775	0	0
T1	2576	14	0	0
T2	15833	19	0	0
T3	163441	2867	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	14	0	0
T9	10380	28	0	0
T10	30721	81	0	0
T11	205323	419	0	0
T12	114395	76	0	0
T13	0	126	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232775	0	0
T1	2576	14	0	0
T2	15833	19	0	0
T3	163441	2867	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	14	0	0
T9	10380	28	0	0
T10	30721	81	0	0
T11	205323	419	0	0
T12	114395	76	0	0
T13	0	126	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3180716	0	0
T1	2576	14	0	0
T2	15833	103	0	0
T3	163441	2485	0	0
T4	19347	1	0	0
T7	40402	792	0	0
T8	336404	5226	0	0
T9	10380	167	0	0
T10	30721	652	0	0
T11	205323	3342	0	0
T12	114395	24541	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232775	0	0
T1	2576	14	0	0
T2	15833	19	0	0
T3	163441	2867	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	14	0	0
T9	10380	28	0	0
T10	30721	81	0	0
T11	205323	419	0	0
T12	114395	76	0	0
T13	0	126	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232775	0	0
T1	2576	14	0	0
T2	15833	19	0	0
T3	163441	2867	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	14	0	0
T9	10380	28	0	0
T10	30721	81	0	0
T11	205323	419	0	0
T12	114395	76	0	0
T13	0	126	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	575158	0	0
T1	2576	15	0	0
T2	15833	19	0	0
T3	163441	3261	0	0
T4	19347	0	0	0
T7	40402	170	0	0
T8	336404	14	0	0
T9	10380	42	0	0
T10	30721	111	0	0
T11	205323	473	0	0
T12	114395	2261	0	0
T13	0	2239	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232775	0	0
T1	2576	14	0	0
T2	15833	19	0	0
T3	163441	2867	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	14	0	0
T9	10380	28	0	0
T10	30721	81	0	0
T11	205323	419	0	0
T12	114395	76	0	0
T13	0	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	225157	0	0
GntImpliesValid_A	419518677	225157	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	225157	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3158303	0	0
ReadyAndValidImplyGrant_A	419518677	225157	0	0
ReqAndReadyImplyGrant_A	419518677	225157	0	0
ReqImpliesValid_A	419518677	532532	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	225157	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225157	0	0
T1	2576	17	0	0
T2	15833	12	0	0
T3	163441	3489	0	0
T4	19347	0	0	0
T7	40402	112	0	0
T8	336404	14	0	0
T9	10380	19	0	0
T10	30721	73	0	0
T11	205323	393	0	0
T12	114395	61	0	0
T13	0	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225157	0	0
T1	2576	17	0	0
T2	15833	12	0	0
T3	163441	3489	0	0
T4	19347	0	0	0
T7	40402	112	0	0
T8	336404	14	0	0
T9	10380	19	0	0
T10	30721	73	0	0
T11	205323	393	0	0
T12	114395	61	0	0
T13	0	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225157	0	0
T1	2576	17	0	0
T2	15833	12	0	0
T3	163441	3489	0	0
T4	19347	0	0	0
T7	40402	112	0	0
T8	336404	14	0	0
T9	10380	19	0	0
T10	30721	73	0	0
T11	205323	393	0	0
T12	114395	61	0	0
T13	0	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3158303	0	0
T1	2576	15	0	0
T2	15833	87	0	0
T3	163441	2427	0	0
T4	19347	1	0	0
T7	40402	910	0	0
T8	336404	4469	0	0
T9	10380	115	0	0
T10	30721	602	0	0
T11	205323	2808	0	0
T12	114395	20492	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225157	0	0
T1	2576	17	0	0
T2	15833	12	0	0
T3	163441	3489	0	0
T4	19347	0	0	0
T7	40402	112	0	0
T8	336404	14	0	0
T9	10380	19	0	0
T10	30721	73	0	0
T11	205323	393	0	0
T12	114395	61	0	0
T13	0	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225157	0	0
T1	2576	17	0	0
T2	15833	12	0	0
T3	163441	3489	0	0
T4	19347	0	0	0
T7	40402	112	0	0
T8	336404	14	0	0
T9	10380	19	0	0
T10	30721	73	0	0
T11	205323	393	0	0
T12	114395	61	0	0
T13	0	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	532532	0	0
T1	2576	20	0	0
T2	15833	23	0	0
T3	163441	4563	0	0
T4	19347	0	0	0
T7	40402	136	0	0
T8	336404	625	0	0
T9	10380	19	0	0
T10	30721	88	0	0
T11	205323	503	0	0
T12	114395	971	0	0
T13	0	1311	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225157	0	0
T1	2576	17	0	0
T2	15833	12	0	0
T3	163441	3489	0	0
T4	19347	0	0	0
T7	40402	112	0	0
T8	336404	14	0	0
T9	10380	19	0	0
T10	30721	73	0	0
T11	205323	393	0	0
T12	114395	61	0	0
T13	0	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	219290	0	0
GntImpliesValid_A	419518677	219290	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	219290	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	5541496	0	0
ReadyAndValidImplyGrant_A	419518677	219290	0	0
ReqAndReadyImplyGrant_A	419518677	219290	0	0
ReqImpliesValid_A	419518677	1270905	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	219290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	219290	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	2908	0	0
T4	19347	326	0	0
T7	40402	108	0	0
T8	336404	15	0	0
T9	10380	23	0	0
T10	30721	90	0	0
T11	205323	444	0	0
T12	114395	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	219290	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	2908	0	0
T4	19347	326	0	0
T7	40402	108	0	0
T8	336404	15	0	0
T9	10380	23	0	0
T10	30721	90	0	0
T11	205323	444	0	0
T12	114395	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	219290	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	2908	0	0
T4	19347	326	0	0
T7	40402	108	0	0
T8	336404	15	0	0
T9	10380	23	0	0
T10	30721	90	0	0
T11	205323	444	0	0
T12	114395	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	5541496	0	0
T1	2576	68	0	0
T2	15833	954	0	0
T3	163441	7191	0	0
T4	19347	583	0	0
T7	40402	2036	0	0
T8	336404	1793	0	0
T9	10380	114	0	0
T10	30721	464	0	0
T11	205323	5615	0	0
T12	114395	57747	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	219290	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	2908	0	0
T4	19347	326	0	0
T7	40402	108	0	0
T8	336404	15	0	0
T9	10380	23	0	0
T10	30721	90	0	0
T11	205323	444	0	0
T12	114395	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	219290	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	2908	0	0
T4	19347	326	0	0
T7	40402	108	0	0
T8	336404	15	0	0
T9	10380	23	0	0
T10	30721	90	0	0
T11	205323	444	0	0
T12	114395	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	1270905	0	0
T1	2576	25	0	0
T2	15833	15	0	0
T3	163441	6346	0	0
T4	19347	6307	0	0
T7	40402	236	0	0
T8	336404	15	0	0
T9	10380	24	0	0
T10	30721	104	0	0
T11	205323	613	0	0
T12	114395	7353	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	219290	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	2908	0	0
T4	19347	326	0	0
T7	40402	108	0	0
T8	336404	15	0	0
T9	10380	23	0	0
T10	30721	90	0	0
T11	205323	444	0	0
T12	114395	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	228384	0	0
GntImpliesValid_A	419518677	228384	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	228384	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	5661808	0	0
ReadyAndValidImplyGrant_A	419518677	228384	0	0
ReqAndReadyImplyGrant_A	419518677	228384	0	0
ReqImpliesValid_A	419518677	1278199	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	228384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	228384	0	0
T1	2576	17	0	0
T2	15833	21	0	0
T3	163441	2293	0	0
T4	19347	0	0	0
T7	40402	102	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	92	0	0
T11	205323	434	0	0
T12	114395	78	0	0
T13	0	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	228384	0	0
T1	2576	17	0	0
T2	15833	21	0	0
T3	163441	2293	0	0
T4	19347	0	0	0
T7	40402	102	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	92	0	0
T11	205323	434	0	0
T12	114395	78	0	0
T13	0	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	228384	0	0
T1	2576	17	0	0
T2	15833	21	0	0
T3	163441	2293	0	0
T4	19347	0	0	0
T7	40402	102	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	92	0	0
T11	205323	434	0	0
T12	114395	78	0	0
T13	0	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	5661808	0	0
T1	2576	142	0	0
T2	15833	432	0	0
T3	163441	8390	0	0
T4	19347	0	0	0
T7	40402	1820	0	0
T8	336404	2965	0	0
T9	10380	241	0	0
T10	30721	474	0	0
T11	205323	5839	0	0
T12	114395	84887	0	0
T13	0	41405	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	228384	0	0
T1	2576	17	0	0
T2	15833	21	0	0
T3	163441	2293	0	0
T4	19347	0	0	0
T7	40402	102	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	92	0	0
T11	205323	434	0	0
T12	114395	78	0	0
T13	0	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	228384	0	0
T1	2576	17	0	0
T2	15833	21	0	0
T3	163441	2293	0	0
T4	19347	0	0	0
T7	40402	102	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	92	0	0
T11	205323	434	0	0
T12	114395	78	0	0
T13	0	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	1278199	0	0
T1	2576	27	0	0
T2	15833	36	0	0
T3	163441	3690	0	0
T4	19347	0	0	0
T7	40402	277	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	118	0	0
T11	205323	631	0	0
T12	114395	10031	0	0
T13	0	3515	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	228384	0	0
T1	2576	17	0	0
T2	15833	21	0	0
T3	163441	2293	0	0
T4	19347	0	0	0
T7	40402	102	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	92	0	0
T11	205323	434	0	0
T12	114395	78	0	0
T13	0	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	234093	0	0
GntImpliesValid_A	419518677	234093	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	234093	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	4784864	0	0
ReadyAndValidImplyGrant_A	419518677	234093	0	0
ReqAndReadyImplyGrant_A	419518677	234093	0	0
ReqImpliesValid_A	419518677	1123266	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	234093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234093	0	0
T1	2576	18	0	0
T2	15833	13	0	0
T3	163441	3770	0	0
T4	19347	0	0	0
T7	40402	104	0	0
T8	336404	13	0	0
T9	10380	23	0	0
T10	30721	76	0	0
T11	205323	429	0	0
T12	114395	51	0	0
T13	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234093	0	0
T1	2576	18	0	0
T2	15833	13	0	0
T3	163441	3770	0	0
T4	19347	0	0	0
T7	40402	104	0	0
T8	336404	13	0	0
T9	10380	23	0	0
T10	30721	76	0	0
T11	205323	429	0	0
T12	114395	51	0	0
T13	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234093	0	0
T1	2576	18	0	0
T2	15833	13	0	0
T3	163441	3770	0	0
T4	19347	0	0	0
T7	40402	104	0	0
T8	336404	13	0	0
T9	10380	23	0	0
T10	30721	76	0	0
T11	205323	429	0	0
T12	114395	51	0	0
T13	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	4784864	0	0
T1	2576	79	0	0
T2	15833	623	0	0
T3	163441	9705	0	0
T4	19347	0	0	0
T7	40402	799	0	0
T8	336404	3657	0	0
T9	10380	381	0	0
T10	30721	818	0	0
T11	205323	5609	0	0
T12	114395	125238	0	0
T13	0	61783	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234093	0	0
T1	2576	18	0	0
T2	15833	13	0	0
T3	163441	3770	0	0
T4	19347	0	0	0
T7	40402	104	0	0
T8	336404	13	0	0
T9	10380	23	0	0
T10	30721	76	0	0
T11	205323	429	0	0
T12	114395	51	0	0
T13	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234093	0	0
T1	2576	18	0	0
T2	15833	13	0	0
T3	163441	3770	0	0
T4	19347	0	0	0
T7	40402	104	0	0
T8	336404	13	0	0
T9	10380	23	0	0
T10	30721	76	0	0
T11	205323	429	0	0
T12	114395	51	0	0
T13	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	1123266	0	0
T1	2576	53	0	0
T2	15833	13	0	0
T3	163441	9314	0	0
T4	19347	0	0	0
T7	40402	177	0	0
T8	336404	257	0	0
T9	10380	91	0	0
T10	30721	104	0	0
T11	205323	584	0	0
T12	114395	6380	0	0
T13	0	3901	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234093	0	0
T1	2576	18	0	0
T2	15833	13	0	0
T3	163441	3770	0	0
T4	19347	0	0	0
T7	40402	104	0	0
T8	336404	13	0	0
T9	10380	23	0	0
T10	30721	76	0	0
T11	205323	429	0	0
T12	114395	51	0	0
T13	0	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	234282	0	0
GntImpliesValid_A	419518677	234282	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	234282	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	4562338	0	0
ReadyAndValidImplyGrant_A	419518677	234282	0	0
ReqAndReadyImplyGrant_A	419518677	234282	0	0
ReqImpliesValid_A	419518677	1097756	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	234282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234282	0	0
T1	2576	17	0	0
T2	15833	13	0	0
T3	163441	1917	0	0
T4	19347	0	0	0
T7	40402	106	0	0
T8	336404	6	0	0
T9	10380	25	0	0
T10	30721	93	0	0
T11	205323	615	0	0
T12	114395	64	0	0
T13	0	156	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234282	0	0
T1	2576	17	0	0
T2	15833	13	0	0
T3	163441	1917	0	0
T4	19347	0	0	0
T7	40402	106	0	0
T8	336404	6	0	0
T9	10380	25	0	0
T10	30721	93	0	0
T11	205323	615	0	0
T12	114395	64	0	0
T13	0	156	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234282	0	0
T1	2576	17	0	0
T2	15833	13	0	0
T3	163441	1917	0	0
T4	19347	0	0	0
T7	40402	106	0	0
T8	336404	6	0	0
T9	10380	25	0	0
T10	30721	93	0	0
T11	205323	615	0	0
T12	114395	64	0	0
T13	0	156	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	4562338	0	0
T1	2576	88	0	0
T2	15833	703	0	0
T3	163441	7022	0	0
T4	19347	0	0	0
T7	40402	1151	0	0
T8	336404	5057	0	0
T9	10380	158	0	0
T10	30721	633	0	0
T11	205323	7097	0	0
T12	114395	29666	0	0
T13	0	51898	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234282	0	0
T1	2576	17	0	0
T2	15833	13	0	0
T3	163441	1917	0	0
T4	19347	0	0	0
T7	40402	106	0	0
T8	336404	6	0	0
T9	10380	25	0	0
T10	30721	93	0	0
T11	205323	615	0	0
T12	114395	64	0	0
T13	0	156	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234282	0	0
T1	2576	17	0	0
T2	15833	13	0	0
T3	163441	1917	0	0
T4	19347	0	0	0
T7	40402	106	0	0
T8	336404	6	0	0
T9	10380	25	0	0
T10	30721	93	0	0
T11	205323	615	0	0
T12	114395	64	0	0
T13	0	156	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	1097756	0	0
T1	2576	17	0	0
T2	15833	52	0	0
T3	163441	2342	0	0
T4	19347	0	0	0
T7	40402	160	0	0
T8	336404	462	0	0
T9	10380	27	0	0
T10	30721	129	0	0
T11	205323	1067	0	0
T12	114395	503	0	0
T13	0	5583	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234282	0	0
T1	2576	17	0	0
T2	15833	13	0	0
T3	163441	1917	0	0
T4	19347	0	0	0
T7	40402	106	0	0
T8	336404	6	0	0
T9	10380	25	0	0
T10	30721	93	0	0
T11	205323	615	0	0
T12	114395	64	0	0
T13	0	156	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	227073	0	0
GntImpliesValid_A	419518677	227073	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	227073	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3186714	0	0
ReadyAndValidImplyGrant_A	419518677	227073	0	0
ReqAndReadyImplyGrant_A	419518677	227073	0	0
ReqImpliesValid_A	419518677	564041	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	227073	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	227073	0	0
T1	2576	20	0	0
T2	15833	9	0	0
T3	163441	3278	0	0
T4	19347	0	0	0
T7	40402	114	0	0
T8	336404	9	0	0
T9	10380	27	0	0
T10	30721	94	0	0
T11	205323	404	0	0
T12	114395	70	0	0
T13	0	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	227073	0	0
T1	2576	20	0	0
T2	15833	9	0	0
T3	163441	3278	0	0
T4	19347	0	0	0
T7	40402	114	0	0
T8	336404	9	0	0
T9	10380	27	0	0
T10	30721	94	0	0
T11	205323	404	0	0
T12	114395	70	0	0
T13	0	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	227073	0	0
T1	2576	20	0	0
T2	15833	9	0	0
T3	163441	3278	0	0
T4	19347	0	0	0
T7	40402	114	0	0
T8	336404	9	0	0
T9	10380	27	0	0
T10	30721	94	0	0
T11	205323	404	0	0
T12	114395	70	0	0
T13	0	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3186714	0	0
T1	2576	18	0	0
T2	15833	89	0	0
T3	163441	2644	0	0
T4	19347	1	0	0
T7	40402	748	0	0
T8	336404	2113	0	0
T9	10380	220	0	0
T10	30721	677	0	0
T11	205323	3279	0	0
T12	114395	20423	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	227073	0	0
T1	2576	20	0	0
T2	15833	9	0	0
T3	163441	3278	0	0
T4	19347	0	0	0
T7	40402	114	0	0
T8	336404	9	0	0
T9	10380	27	0	0
T10	30721	94	0	0
T11	205323	404	0	0
T12	114395	70	0	0
T13	0	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	227073	0	0
T1	2576	20	0	0
T2	15833	9	0	0
T3	163441	3278	0	0
T4	19347	0	0	0
T7	40402	114	0	0
T8	336404	9	0	0
T9	10380	27	0	0
T10	30721	94	0	0
T11	205323	404	0	0
T12	114395	70	0	0
T13	0	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	564041	0	0
T1	2576	23	0	0
T2	15833	9	0	0
T3	163441	3924	0	0
T4	19347	0	0	0
T7	40402	175	0	0
T8	336404	9	0	0
T9	10380	31	0	0
T10	30721	123	0	0
T11	205323	477	0	0
T12	114395	816	0	0
T13	0	2238	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	227073	0	0
T1	2576	20	0	0
T2	15833	9	0	0
T3	163441	3278	0	0
T4	19347	0	0	0
T7	40402	114	0	0
T8	336404	9	0	0
T9	10380	27	0	0
T10	30721	94	0	0
T11	205323	404	0	0
T12	114395	70	0	0
T13	0	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	210426	0	0
GntImpliesValid_A	419518677	210426	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	210426	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3247351	0	0
ReadyAndValidImplyGrant_A	419518677	210426	0	0
ReqAndReadyImplyGrant_A	419518677	210426	0	0
ReqImpliesValid_A	419518677	528126	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	210426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	210426	0	0
T1	2576	17	0	0
T2	15833	27	0	0
T3	163441	2237	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	9	0	0
T9	10380	16	0	0
T10	30721	79	0	0
T11	205323	363	0	0
T12	114395	76	0	0
T13	0	137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	210426	0	0
T1	2576	17	0	0
T2	15833	27	0	0
T3	163441	2237	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	9	0	0
T9	10380	16	0	0
T10	30721	79	0	0
T11	205323	363	0	0
T12	114395	76	0	0
T13	0	137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	210426	0	0
T1	2576	17	0	0
T2	15833	27	0	0
T3	163441	2237	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	9	0	0
T9	10380	16	0	0
T10	30721	79	0	0
T11	205323	363	0	0
T12	114395	76	0	0
T13	0	137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3247351	0	0
T1	2576	17	0	0
T2	15833	174	0	0
T3	163441	2001	0	0
T4	19347	1	0	0
T7	40402	875	0	0
T8	336404	2057	0	0
T9	10380	135	0	0
T10	30721	555	0	0
T11	205323	2727	0	0
T12	114395	25967	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	210426	0	0
T1	2576	17	0	0
T2	15833	27	0	0
T3	163441	2237	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	9	0	0
T9	10380	16	0	0
T10	30721	79	0	0
T11	205323	363	0	0
T12	114395	76	0	0
T13	0	137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	210426	0	0
T1	2576	17	0	0
T2	15833	27	0	0
T3	163441	2237	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	9	0	0
T9	10380	16	0	0
T10	30721	79	0	0
T11	205323	363	0	0
T12	114395	76	0	0
T13	0	137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	528126	0	0
T1	2576	18	0	0
T2	15833	73	0	0
T3	163441	2486	0	0
T4	19347	0	0	0
T7	40402	191	0	0
T8	336404	591	0	0
T9	10380	18	0	0
T10	30721	108	0	0
T11	205323	393	0	0
T12	114395	1910	0	0
T13	0	2885	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	210426	0	0
T1	2576	17	0	0
T2	15833	27	0	0
T3	163441	2237	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	9	0	0
T9	10380	16	0	0
T10	30721	79	0	0
T11	205323	363	0	0
T12	114395	76	0	0
T13	0	137	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	226001	0	0
GntImpliesValid_A	419518677	226001	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	226001	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3272134	0	0
ReadyAndValidImplyGrant_A	419518677	226001	0	0
ReqAndReadyImplyGrant_A	419518677	226001	0	0
ReqImpliesValid_A	419518677	542901	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	226001	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	226001	0	0
T1	2576	15	0	0
T2	15833	21	0	0
T3	163441	3386	0	0
T4	19347	0	0	0
T7	40402	107	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	94	0	0
T11	205323	357	0	0
T12	114395	74	0	0
T13	0	126	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	226001	0	0
T1	2576	15	0	0
T2	15833	21	0	0
T3	163441	3386	0	0
T4	19347	0	0	0
T7	40402	107	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	94	0	0
T11	205323	357	0	0
T12	114395	74	0	0
T13	0	126	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	226001	0	0
T1	2576	15	0	0
T2	15833	21	0	0
T3	163441	3386	0	0
T4	19347	0	0	0
T7	40402	107	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	94	0	0
T11	205323	357	0	0
T12	114395	74	0	0
T13	0	126	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3272134	0	0
T1	2576	16	0	0
T2	15833	180	0	0
T3	163441	2760	0	0
T4	19347	1	0	0
T7	40402	829	0	0
T8	336404	1931	0	0
T9	10380	99	0	0
T10	30721	672	0	0
T11	205323	2712	0	0
T12	114395	23650	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	226001	0	0
T1	2576	15	0	0
T2	15833	21	0	0
T3	163441	3386	0	0
T4	19347	0	0	0
T7	40402	107	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	94	0	0
T11	205323	357	0	0
T12	114395	74	0	0
T13	0	126	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	226001	0	0
T1	2576	15	0	0
T2	15833	21	0	0
T3	163441	3386	0	0
T4	19347	0	0	0
T7	40402	107	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	94	0	0
T11	205323	357	0	0
T12	114395	74	0	0
T13	0	126	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	542901	0	0
T1	2576	15	0	0
T2	15833	33	0	0
T3	163441	4025	0	0
T4	19347	0	0	0
T7	40402	128	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	166	0	0
T11	205323	430	0	0
T12	114395	1533	0	0
T13	0	3374	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	226001	0	0
T1	2576	15	0	0
T2	15833	21	0	0
T3	163441	3386	0	0
T4	19347	0	0	0
T7	40402	107	0	0
T8	336404	5	0	0
T9	10380	17	0	0
T10	30721	94	0	0
T11	205323	357	0	0
T12	114395	74	0	0
T13	0	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	225809	0	0
GntImpliesValid_A	419518677	225809	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	225809	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3354158	0	0
ReadyAndValidImplyGrant_A	419518677	225809	0	0
ReqAndReadyImplyGrant_A	419518677	225809	0	0
ReqImpliesValid_A	419518677	575198	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	225809	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225809	0	0
T1	2576	20	0	0
T2	15833	12	0	0
T3	163441	2314	0	0
T4	19347	411	0	0
T7	40402	112	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	83	0	0
T11	205323	402	0	0
T12	114395	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225809	0	0
T1	2576	20	0	0
T2	15833	12	0	0
T3	163441	2314	0	0
T4	19347	411	0	0
T7	40402	112	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	83	0	0
T11	205323	402	0	0
T12	114395	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225809	0	0
T1	2576	20	0	0
T2	15833	12	0	0
T3	163441	2314	0	0
T4	19347	411	0	0
T7	40402	112	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	83	0	0
T11	205323	402	0	0
T12	114395	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3354158	0	0
T1	2576	20	0	0
T2	15833	127	0	0
T3	163441	1785	0	0
T4	19347	862	0	0
T7	40402	921	0	0
T8	336404	2544	0	0
T9	10380	140	0	0
T10	30721	549	0	0
T11	205323	2837	0	0
T12	114395	26465	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225809	0	0
T1	2576	20	0	0
T2	15833	12	0	0
T3	163441	2314	0	0
T4	19347	411	0	0
T7	40402	112	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	83	0	0
T11	205323	402	0	0
T12	114395	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225809	0	0
T1	2576	20	0	0
T2	15833	12	0	0
T3	163441	2314	0	0
T4	19347	411	0	0
T7	40402	112	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	83	0	0
T11	205323	402	0	0
T12	114395	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	575198	0	0
T1	2576	21	0	0
T2	15833	12	0	0
T3	163441	2856	0	0
T4	19347	1865	0	0
T7	40402	136	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	114	0	0
T11	205323	472	0	0
T12	114395	2228	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225809	0	0
T1	2576	20	0	0
T2	15833	12	0	0
T3	163441	2314	0	0
T4	19347	411	0	0
T7	40402	112	0	0
T8	336404	10	0	0
T9	10380	20	0	0
T10	30721	83	0	0
T11	205323	402	0	0
T12	114395	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	232714	0	0
GntImpliesValid_A	419518677	232714	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	232714	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3276782	0	0
ReadyAndValidImplyGrant_A	419518677	232714	0	0
ReqAndReadyImplyGrant_A	419518677	232714	0	0
ReqImpliesValid_A	419518677	603560	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	232714	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232714	0	0
T1	2576	10	0	0
T2	15833	21	0	0
T3	163441	4220	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	12	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	411	0	0
T12	114395	74	0	0
T13	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232714	0	0
T1	2576	10	0	0
T2	15833	21	0	0
T3	163441	4220	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	12	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	411	0	0
T12	114395	74	0	0
T13	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232714	0	0
T1	2576	10	0	0
T2	15833	21	0	0
T3	163441	4220	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	12	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	411	0	0
T12	114395	74	0	0
T13	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3276782	0	0
T1	2576	10	0	0
T2	15833	153	0	0
T3	163441	2744	0	0
T4	19347	1	0	0
T7	40402	1046	0	0
T8	336404	4598	0	0
T9	10380	146	0	0
T10	30721	622	0	0
T11	205323	3118	0	0
T12	114395	25935	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232714	0	0
T1	2576	10	0	0
T2	15833	21	0	0
T3	163441	4220	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	12	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	411	0	0
T12	114395	74	0	0
T13	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232714	0	0
T1	2576	10	0	0
T2	15833	21	0	0
T3	163441	4220	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	12	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	411	0	0
T12	114395	74	0	0
T13	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	603560	0	0
T1	2576	11	0	0
T2	15833	27	0	0
T3	163441	5709	0	0
T4	19347	0	0	0
T7	40402	165	0	0
T8	336404	136	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	498	0	0
T12	114395	2975	0	0
T13	0	995	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	232714	0	0
T1	2576	10	0	0
T2	15833	21	0	0
T3	163441	4220	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	12	0	0
T9	10380	14	0	0
T10	30721	83	0	0
T11	205323	411	0	0
T12	114395	74	0	0
T13	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	237140	0	0
GntImpliesValid_A	419518677	237140	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	237140	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3212492	0	0
ReadyAndValidImplyGrant_A	419518677	237140	0	0
ReqAndReadyImplyGrant_A	419518677	237140	0	0
ReqImpliesValid_A	419518677	561425	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	237140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237140	0	0
T1	2576	11	0	0
T2	15833	19	0	0
T3	163441	2665	0	0
T4	19347	0	0	0
T7	40402	109	0	0
T8	336404	8	0	0
T9	10380	29	0	0
T10	30721	84	0	0
T11	205323	409	0	0
T12	114395	58	0	0
T13	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237140	0	0
T1	2576	11	0	0
T2	15833	19	0	0
T3	163441	2665	0	0
T4	19347	0	0	0
T7	40402	109	0	0
T8	336404	8	0	0
T9	10380	29	0	0
T10	30721	84	0	0
T11	205323	409	0	0
T12	114395	58	0	0
T13	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237140	0	0
T1	2576	11	0	0
T2	15833	19	0	0
T3	163441	2665	0	0
T4	19347	0	0	0
T7	40402	109	0	0
T8	336404	8	0	0
T9	10380	29	0	0
T10	30721	84	0	0
T11	205323	409	0	0
T12	114395	58	0	0
T13	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3212492	0	0
T1	2576	12	0	0
T2	15833	165	0	0
T3	163441	2049	0	0
T4	19347	1	0	0
T7	40402	803	0	0
T8	336404	1943	0	0
T9	10380	175	0	0
T10	30721	591	0	0
T11	205323	3024	0	0
T12	114395	17333	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237140	0	0
T1	2576	11	0	0
T2	15833	19	0	0
T3	163441	2665	0	0
T4	19347	0	0	0
T7	40402	109	0	0
T8	336404	8	0	0
T9	10380	29	0	0
T10	30721	84	0	0
T11	205323	409	0	0
T12	114395	58	0	0
T13	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237140	0	0
T1	2576	11	0	0
T2	15833	19	0	0
T3	163441	2665	0	0
T4	19347	0	0	0
T7	40402	109	0	0
T8	336404	8	0	0
T9	10380	29	0	0
T10	30721	84	0	0
T11	205323	409	0	0
T12	114395	58	0	0
T13	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	561425	0	0
T1	2576	11	0	0
T2	15833	24	0	0
T3	163441	3293	0	0
T4	19347	0	0	0
T7	40402	146	0	0
T8	336404	893	0	0
T9	10380	29	0	0
T10	30721	110	0	0
T11	205323	503	0	0
T12	114395	528	0	0
T13	0	488	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237140	0	0
T1	2576	11	0	0
T2	15833	19	0	0
T3	163441	2665	0	0
T4	19347	0	0	0
T7	40402	109	0	0
T8	336404	8	0	0
T9	10380	29	0	0
T10	30721	84	0	0
T11	205323	409	0	0
T12	114395	58	0	0
T13	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	242841	0	0
GntImpliesValid_A	419518677	242841	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	242841	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3266094	0	0
ReadyAndValidImplyGrant_A	419518677	242841	0	0
ReqAndReadyImplyGrant_A	419518677	242841	0	0
ReqImpliesValid_A	419518677	595614	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	242841	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	242841	0	0
T1	2576	21	0	0
T2	15833	11	0	0
T3	163441	2286	0	0
T4	19347	0	0	0
T7	40402	97	0	0
T8	336404	12	0	0
T9	10380	12	0	0
T10	30721	87	0	0
T11	205323	405	0	0
T12	114395	49	0	0
T13	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	242841	0	0
T1	2576	21	0	0
T2	15833	11	0	0
T3	163441	2286	0	0
T4	19347	0	0	0
T7	40402	97	0	0
T8	336404	12	0	0
T9	10380	12	0	0
T10	30721	87	0	0
T11	205323	405	0	0
T12	114395	49	0	0
T13	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	242841	0	0
T1	2576	21	0	0
T2	15833	11	0	0
T3	163441	2286	0	0
T4	19347	0	0	0
T7	40402	97	0	0
T8	336404	12	0	0
T9	10380	12	0	0
T10	30721	87	0	0
T11	205323	405	0	0
T12	114395	49	0	0
T13	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3266094	0	0
T1	2576	21	0	0
T2	15833	66	0	0
T3	163441	2030	0	0
T4	19347	1	0	0
T7	40402	626	0	0
T8	336404	4722	0	0
T9	10380	66	0	0
T10	30721	697	0	0
T11	205323	2969	0	0
T12	114395	17856	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	242841	0	0
T1	2576	21	0	0
T2	15833	11	0	0
T3	163441	2286	0	0
T4	19347	0	0	0
T7	40402	97	0	0
T8	336404	12	0	0
T9	10380	12	0	0
T10	30721	87	0	0
T11	205323	405	0	0
T12	114395	49	0	0
T13	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	242841	0	0
T1	2576	21	0	0
T2	15833	11	0	0
T3	163441	2286	0	0
T4	19347	0	0	0
T7	40402	97	0	0
T8	336404	12	0	0
T9	10380	12	0	0
T10	30721	87	0	0
T11	205323	405	0	0
T12	114395	49	0	0
T13	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	595614	0	0
T1	2576	22	0	0
T2	15833	11	0	0
T3	163441	2555	0	0
T4	19347	0	0	0
T7	40402	101	0	0
T8	336404	829	0	0
T9	10380	12	0	0
T10	30721	101	0	0
T11	205323	450	0	0
T12	114395	233	0	0
T13	0	1534	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	242841	0	0
T1	2576	21	0	0
T2	15833	11	0	0
T3	163441	2286	0	0
T4	19347	0	0	0
T7	40402	97	0	0
T8	336404	12	0	0
T9	10380	12	0	0
T10	30721	87	0	0
T11	205323	405	0	0
T12	114395	49	0	0
T13	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	234605	0	0
GntImpliesValid_A	419518677	234605	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	234605	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3231392	0	0
ReadyAndValidImplyGrant_A	419518677	234605	0	0
ReqAndReadyImplyGrant_A	419518677	234605	0	0
ReqImpliesValid_A	419518677	582948	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	234605	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234605	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	3624	0	0
T4	19347	0	0	0
T7	40402	89	0	0
T8	336404	14	0	0
T9	10380	24	0	0
T10	30721	100	0	0
T11	205323	374	0	0
T12	114395	97	0	0
T13	0	129	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234605	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	3624	0	0
T4	19347	0	0	0
T7	40402	89	0	0
T8	336404	14	0	0
T9	10380	24	0	0
T10	30721	100	0	0
T11	205323	374	0	0
T12	114395	97	0	0
T13	0	129	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234605	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	3624	0	0
T4	19347	0	0	0
T7	40402	89	0	0
T8	336404	14	0	0
T9	10380	24	0	0
T10	30721	100	0	0
T11	205323	374	0	0
T12	114395	97	0	0
T13	0	129	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3231392	0	0
T1	2576	23	0	0
T2	15833	76	0	0
T3	163441	2207	0	0
T4	19347	1	0	0
T7	40402	690	0	0
T8	336404	4413	0	0
T9	10380	167	0	0
T10	30721	723	0	0
T11	205323	2854	0	0
T12	114395	33571	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234605	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	3624	0	0
T4	19347	0	0	0
T7	40402	89	0	0
T8	336404	14	0	0
T9	10380	24	0	0
T10	30721	100	0	0
T11	205323	374	0	0
T12	114395	97	0	0
T13	0	129	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234605	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	3624	0	0
T4	19347	0	0	0
T7	40402	89	0	0
T8	336404	14	0	0
T9	10380	24	0	0
T10	30721	100	0	0
T11	205323	374	0	0
T12	114395	97	0	0
T13	0	129	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	582948	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	5054	0	0
T4	19347	0	0	0
T7	40402	108	0	0
T8	336404	303	0	0
T9	10380	31	0	0
T10	30721	127	0	0
T11	205323	436	0	0
T12	114395	3006	0	0
T13	0	510	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	234605	0	0
T1	2576	22	0	0
T2	15833	9	0	0
T3	163441	3624	0	0
T4	19347	0	0	0
T7	40402	89	0	0
T8	336404	14	0	0
T9	10380	24	0	0
T10	30721	100	0	0
T11	205323	374	0	0
T12	114395	97	0	0
T13	0	129	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	248676	0	0
GntImpliesValid_A	419518677	248676	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	248676	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3347305	0	0
ReadyAndValidImplyGrant_A	419518677	248676	0	0
ReqAndReadyImplyGrant_A	419518677	248676	0	0
ReqImpliesValid_A	419518677	615241	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	248676	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	248676	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	1980	0	0
T4	19347	0	0	0
T7	40402	98	0	0
T8	336404	4	0	0
T9	10380	41	0	0
T10	30721	85	0	0
T11	205323	462	0	0
T12	114395	64	0	0
T13	0	140	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	248676	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	1980	0	0
T4	19347	0	0	0
T7	40402	98	0	0
T8	336404	4	0	0
T9	10380	41	0	0
T10	30721	85	0	0
T11	205323	462	0	0
T12	114395	64	0	0
T13	0	140	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	248676	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	1980	0	0
T4	19347	0	0	0
T7	40402	98	0	0
T8	336404	4	0	0
T9	10380	41	0	0
T10	30721	85	0	0
T11	205323	462	0	0
T12	114395	64	0	0
T13	0	140	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3347305	0	0
T1	2576	6	0	0
T2	15833	113	0	0
T3	163441	1933	0	0
T4	19347	1	0	0
T7	40402	712	0	0
T8	336404	802	0	0
T9	10380	292	0	0
T10	30721	625	0	0
T11	205323	3528	0	0
T12	114395	21609	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	248676	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	1980	0	0
T4	19347	0	0	0
T7	40402	98	0	0
T8	336404	4	0	0
T9	10380	41	0	0
T10	30721	85	0	0
T11	205323	462	0	0
T12	114395	64	0	0
T13	0	140	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	248676	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	1980	0	0
T4	19347	0	0	0
T7	40402	98	0	0
T8	336404	4	0	0
T9	10380	41	0	0
T10	30721	85	0	0
T11	205323	462	0	0
T12	114395	64	0	0
T13	0	140	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	615241	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	2040	0	0
T4	19347	0	0	0
T7	40402	150	0	0
T8	336404	4	0	0
T9	10380	47	0	0
T10	30721	137	0	0
T11	205323	554	0	0
T12	114395	420	0	0
T13	0	1534	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	248676	0	0
T1	2576	5	0	0
T2	15833	15	0	0
T3	163441	1980	0	0
T4	19347	0	0	0
T7	40402	98	0	0
T8	336404	4	0	0
T9	10380	41	0	0
T10	30721	85	0	0
T11	205323	462	0	0
T12	114395	64	0	0
T13	0	140	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	240735	0	0
GntImpliesValid_A	419518677	240735	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	240735	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3266956	0	0
ReadyAndValidImplyGrant_A	419518677	240735	0	0
ReqAndReadyImplyGrant_A	419518677	240735	0	0
ReqImpliesValid_A	419518677	621526	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	240735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	240735	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2386	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	89	0	0
T11	205323	396	0	0
T12	114395	71	0	0
T13	0	140	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	240735	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2386	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	89	0	0
T11	205323	396	0	0
T12	114395	71	0	0
T13	0	140	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	240735	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2386	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	89	0	0
T11	205323	396	0	0
T12	114395	71	0	0
T13	0	140	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3266956	0	0
T1	2576	9	0	0
T2	15833	111	0	0
T3	163441	2126	0	0
T4	19347	1	0	0
T7	40402	851	0	0
T8	336404	2418	0	0
T9	10380	151	0	0
T10	30721	706	0	0
T11	205323	2938	0	0
T12	114395	24598	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	240735	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2386	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	89	0	0
T11	205323	396	0	0
T12	114395	71	0	0
T13	0	140	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	240735	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2386	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	89	0	0
T11	205323	396	0	0
T12	114395	71	0	0
T13	0	140	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	621526	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2659	0	0
T4	19347	0	0	0
T7	40402	183	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	105	0	0
T11	205323	462	0	0
T12	114395	2183	0	0
T13	0	2941	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	240735	0	0
T1	2576	8	0	0
T2	15833	17	0	0
T3	163441	2386	0	0
T4	19347	0	0	0
T7	40402	117	0	0
T8	336404	7	0	0
T9	10380	22	0	0
T10	30721	89	0	0
T11	205323	396	0	0
T12	114395	71	0	0
T13	0	140	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	225276	0	0
GntImpliesValid_A	419518677	225276	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	225276	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3215994	0	0
ReadyAndValidImplyGrant_A	419518677	225276	0	0
ReqAndReadyImplyGrant_A	419518677	225276	0	0
ReqImpliesValid_A	419518677	533494	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	225276	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225276	0	0
T1	2576	14	0	0
T2	15833	9	0	0
T3	163441	2840	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	85	0	0
T11	205323	517	0	0
T12	114395	57	0	0
T13	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225276	0	0
T1	2576	14	0	0
T2	15833	9	0	0
T3	163441	2840	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	85	0	0
T11	205323	517	0	0
T12	114395	57	0	0
T13	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225276	0	0
T1	2576	14	0	0
T2	15833	9	0	0
T3	163441	2840	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	85	0	0
T11	205323	517	0	0
T12	114395	57	0	0
T13	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3215994	0	0
T1	2576	15	0	0
T2	15833	47	0	0
T3	163441	2145	0	0
T4	19347	1	0	0
T7	40402	912	0	0
T8	336404	2479	0	0
T9	10380	110	0	0
T10	30721	682	0	0
T11	205323	3604	0	0
T12	114395	15534	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225276	0	0
T1	2576	14	0	0
T2	15833	9	0	0
T3	163441	2840	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	85	0	0
T11	205323	517	0	0
T12	114395	57	0	0
T13	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225276	0	0
T1	2576	14	0	0
T2	15833	9	0	0
T3	163441	2840	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	85	0	0
T11	205323	517	0	0
T12	114395	57	0	0
T13	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	533494	0	0
T1	2576	14	0	0
T2	15833	13	0	0
T3	163441	3548	0	0
T4	19347	0	0	0
T7	40402	144	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	132	0	0
T11	205323	732	0	0
T12	114395	1677	0	0
T13	0	2168	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	225276	0	0
T1	2576	14	0	0
T2	15833	9	0	0
T3	163441	2840	0	0
T4	19347	0	0	0
T7	40402	120	0	0
T8	336404	10	0	0
T9	10380	17	0	0
T10	30721	85	0	0
T11	205323	517	0	0
T12	114395	57	0	0
T13	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	237939	0	0
GntImpliesValid_A	419518677	237939	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	237939	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3251442	0	0
ReadyAndValidImplyGrant_A	419518677	237939	0	0
ReqAndReadyImplyGrant_A	419518677	237939	0	0
ReqImpliesValid_A	419518677	623248	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	237939	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237939	0	0
T1	2576	11	0	0
T2	15833	15	0	0
T3	163441	3881	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	14	0	0
T9	10380	22	0	0
T10	30721	81	0	0
T11	205323	369	0	0
T12	114395	73	0	0
T13	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237939	0	0
T1	2576	11	0	0
T2	15833	15	0	0
T3	163441	3881	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	14	0	0
T9	10380	22	0	0
T10	30721	81	0	0
T11	205323	369	0	0
T12	114395	73	0	0
T13	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237939	0	0
T1	2576	11	0	0
T2	15833	15	0	0
T3	163441	3881	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	14	0	0
T9	10380	22	0	0
T10	30721	81	0	0
T11	205323	369	0	0
T12	114395	73	0	0
T13	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3251442	0	0
T1	2576	10	0	0
T2	15833	68	0	0
T3	163441	3071	0	0
T4	19347	1	0	0
T7	40402	862	0	0
T8	336404	4182	0	0
T9	10380	141	0	0
T10	30721	656	0	0
T11	205323	2731	0	0
T12	114395	23794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237939	0	0
T1	2576	11	0	0
T2	15833	15	0	0
T3	163441	3881	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	14	0	0
T9	10380	22	0	0
T10	30721	81	0	0
T11	205323	369	0	0
T12	114395	73	0	0
T13	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237939	0	0
T1	2576	11	0	0
T2	15833	15	0	0
T3	163441	3881	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	14	0	0
T9	10380	22	0	0
T10	30721	81	0	0
T11	205323	369	0	0
T12	114395	73	0	0
T13	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	623248	0	0
T1	2576	13	0	0
T2	15833	15	0	0
T3	163441	4703	0	0
T4	19347	0	0	0
T7	40402	179	0	0
T8	336404	201	0	0
T9	10380	22	0	0
T10	30721	126	0	0
T11	205323	431	0	0
T12	114395	345	0	0
T13	0	1747	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	237939	0	0
T1	2576	11	0	0
T2	15833	15	0	0
T3	163441	3881	0	0
T4	19347	0	0	0
T7	40402	118	0	0
T8	336404	14	0	0
T9	10380	22	0	0
T10	30721	81	0	0
T11	205323	369	0	0
T12	114395	73	0	0
T13	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	218599	0	0
GntImpliesValid_A	419518677	218599	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	218599	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3166615	0	0
ReadyAndValidImplyGrant_A	419518677	218599	0	0
ReqAndReadyImplyGrant_A	419518677	218599	0	0
ReqImpliesValid_A	419518677	524888	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	218599	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	218599	0	0
T1	2576	15	0	0
T2	15833	16	0	0
T3	163441	2837	0	0
T4	19347	0	0	0
T7	40402	121	0	0
T8	336404	11	0	0
T9	10380	26	0	0
T10	30721	80	0	0
T11	205323	398	0	0
T12	114395	59	0	0
T13	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	218599	0	0
T1	2576	15	0	0
T2	15833	16	0	0
T3	163441	2837	0	0
T4	19347	0	0	0
T7	40402	121	0	0
T8	336404	11	0	0
T9	10380	26	0	0
T10	30721	80	0	0
T11	205323	398	0	0
T12	114395	59	0	0
T13	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	218599	0	0
T1	2576	15	0	0
T2	15833	16	0	0
T3	163441	2837	0	0
T4	19347	0	0	0
T7	40402	121	0	0
T8	336404	11	0	0
T9	10380	26	0	0
T10	30721	80	0	0
T11	205323	398	0	0
T12	114395	59	0	0
T13	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3166615	0	0
T1	2576	15	0	0
T2	15833	111	0	0
T3	163441	2162	0	0
T4	19347	1	0	0
T7	40402	915	0	0
T8	336404	4215	0	0
T9	10380	233	0	0
T10	30721	531	0	0
T11	205323	2855	0	0
T12	114395	19203	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	218599	0	0
T1	2576	15	0	0
T2	15833	16	0	0
T3	163441	2837	0	0
T4	19347	0	0	0
T7	40402	121	0	0
T8	336404	11	0	0
T9	10380	26	0	0
T10	30721	80	0	0
T11	205323	398	0	0
T12	114395	59	0	0
T13	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	218599	0	0
T1	2576	15	0	0
T2	15833	16	0	0
T3	163441	2837	0	0
T4	19347	0	0	0
T7	40402	121	0	0
T8	336404	11	0	0
T9	10380	26	0	0
T10	30721	80	0	0
T11	205323	398	0	0
T12	114395	59	0	0
T13	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	524888	0	0
T1	2576	16	0	0
T2	15833	17	0	0
T3	163441	3525	0	0
T4	19347	0	0	0
T7	40402	224	0	0
T8	336404	11	0	0
T9	10380	30	0	0
T10	30721	123	0	0
T11	205323	495	0	0
T12	114395	1312	0	0
T13	0	618	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	218599	0	0
T1	2576	15	0	0
T2	15833	16	0	0
T3	163441	2837	0	0
T4	19347	0	0	0
T7	40402	121	0	0
T8	336404	11	0	0
T9	10380	26	0	0
T10	30721	80	0	0
T11	205323	398	0	0
T12	114395	59	0	0
T13	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	231823	0	0
GntImpliesValid_A	419518677	231823	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	231823	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	3254304	0	0
ReadyAndValidImplyGrant_A	419518677	231823	0	0
ReqAndReadyImplyGrant_A	419518677	231823	0	0
ReqImpliesValid_A	419518677	606596	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	0	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	231823	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	231823	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	3744	0	0
T4	19347	448	0	0
T7	40402	96	0	0
T8	336404	13	0	0
T9	10380	19	0	0
T10	30721	67	0	0
T11	205323	390	0	0
T12	114395	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	231823	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	3744	0	0
T4	19347	448	0	0
T7	40402	96	0	0
T8	336404	13	0	0
T9	10380	19	0	0
T10	30721	67	0	0
T11	205323	390	0	0
T12	114395	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	231823	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	3744	0	0
T4	19347	448	0	0
T7	40402	96	0	0
T8	336404	13	0	0
T9	10380	19	0	0
T10	30721	67	0	0
T11	205323	390	0	0
T12	114395	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	3254304	0	0
T1	2576	7	0	0
T2	15833	76	0	0
T3	163441	3015	0	0
T4	19347	514	0	0
T7	40402	605	0	0
T8	336404	3430	0	0
T9	10380	133	0	0
T10	30721	509	0	0
T11	205323	2751	0	0
T12	114395	18139	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	231823	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	3744	0	0
T4	19347	448	0	0
T7	40402	96	0	0
T8	336404	13	0	0
T9	10380	19	0	0
T10	30721	67	0	0
T11	205323	390	0	0
T12	114395	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	231823	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	3744	0	0
T4	19347	448	0	0
T7	40402	96	0	0
T8	336404	13	0	0
T9	10380	19	0	0
T10	30721	67	0	0
T11	205323	390	0	0
T12	114395	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	606596	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	4486	0	0
T4	19347	4495	0	0
T7	40402	115	0	0
T8	336404	258	0	0
T9	10380	20	0	0
T10	30721	80	0	0
T11	205323	443	0	0
T12	114395	1369	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	231823	0	0
T1	2576	6	0	0
T2	15833	10	0	0
T3	163441	3744	0	0
T4	19347	448	0	0
T7	40402	96	0	0
T8	336404	13	0	0
T9	10380	19	0	0
T10	30721	67	0	0
T11	205323	390	0	0
T12	114395	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	922173	0	0
GntImpliesValid_A	419518677	922173	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	922173	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	12108885	0	0
ReadyAndValidImplyGrant_A	419518677	922173	0	0
ReqAndReadyImplyGrant_A	419518677	922173	0	0
ReqImpliesValid_A	419518677	2360721	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	19409	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	922173	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922173	0	0
T1	2576	52	0	0
T2	15833	49	0	0
T3	163441	11023	0	0
T4	19347	159	0	0
T7	40402	490	0	0
T8	336404	35	0	0
T9	10380	63	0	0
T10	30721	307	0	0
T11	205323	1590	0	0
T12	114395	247	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922173	0	0
T1	2576	52	0	0
T2	15833	49	0	0
T3	163441	11023	0	0
T4	19347	159	0	0
T7	40402	490	0	0
T8	336404	35	0	0
T9	10380	63	0	0
T10	30721	307	0	0
T11	205323	1590	0	0
T12	114395	247	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922173	0	0
T1	2576	52	0	0
T2	15833	49	0	0
T3	163441	11023	0	0
T4	19347	159	0	0
T7	40402	490	0	0
T8	336404	35	0	0
T9	10380	63	0	0
T10	30721	307	0	0
T11	205323	1590	0	0
T12	114395	247	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	12108885	0	0
T1	2576	1	0	0
T2	15833	283	0	0
T3	163441	13	0	0
T4	19347	1128	0	0
T7	40402	2573	0	0
T8	336404	11154	0	0
T9	10380	466	0	0
T10	30721	1979	0	0
T11	205323	10254	0	0
T12	114395	82200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922173	0	0
T1	2576	52	0	0
T2	15833	49	0	0
T3	163441	11023	0	0
T4	19347	159	0	0
T7	40402	490	0	0
T8	336404	35	0	0
T9	10380	63	0	0
T10	30721	307	0	0
T11	205323	1590	0	0
T12	114395	247	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922173	0	0
T1	2576	52	0	0
T2	15833	49	0	0
T3	163441	11023	0	0
T4	19347	159	0	0
T7	40402	490	0	0
T8	336404	35	0	0
T9	10380	63	0	0
T10	30721	307	0	0
T11	205323	1590	0	0
T12	114395	247	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	2360721	0	0
T1	2576	52	0	0
T2	15833	83	0	0
T3	163441	11023	0	0
T4	19347	321	0	0
T7	40402	939	0	0
T8	336404	888	0	0
T9	10380	68	0	0
T10	30721	488	0	0
T11	205323	2138	0	0
T12	114395	4848	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	19409	0	900
T3	163441	282	0	1
T4	19347	0	0	1
T7	40402	0	0	1
T8	336404	0	0	1
T9	10380	0	0	1
T10	30721	0	0	1
T11	205323	0	0	1
T12	114395	0	0	1
T13	209805	0	0	1
T14	0	3	0	0
T15	0	7	0	0
T16	0	1	0	0
T17	0	6	0	0
T18	0	1	0	0
T19	0	5	0	0
T21	0	5	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	260429	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	922173	0	0
T1	2576	52	0	0
T2	15833	49	0	0
T3	163441	11023	0	0
T4	19347	159	0	0
T7	40402	490	0	0
T8	336404	35	0	0
T9	10380	63	0	0
T10	30721	307	0	0
T11	205323	1590	0	0
T12	114395	247	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419518677	419391272	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419518677	919722	0	0
GntImpliesValid_A	419518677	919722	0	0
GrantKnown_A	419518677	419391272	0	0
IdxKnown_A	419518677	419391272	0	0
IndexIsCorrect_A	419518677	919722	0	0
LockArbDecision_A	419518677	0	0	0
NoReadyValidNoGrant_A	419518677	352008344	0	0
ReadyAndValidImplyGrant_A	419518677	919722	0	0
ReqAndReadyImplyGrant_A	419518677	919722	0	0
ReqImpliesValid_A	419518677	14159356	0	0
ReqStaysHighUntilGranted0_M	419518677	0	0	0
RoundRobin_A	419518677	35805	0	900
ValidKnown_A	419518677	419391272	0	0
gen_data_port_assertion.DataFlow_A	419518677	919722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	919722	0	0
T1	2576	66	0	0
T2	15833	49	0	0
T3	163441	11856	0	0
T4	19347	152	0	0
T7	40402	476	0	0
T8	336404	32	0	0
T9	10380	81	0	0
T10	30721	292	0	0
T11	205323	1674	0	0
T12	114395	278	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	919722	0	0
T1	2576	66	0	0
T2	15833	49	0	0
T3	163441	11856	0	0
T4	19347	152	0	0
T7	40402	476	0	0
T8	336404	32	0	0
T9	10380	81	0	0
T10	30721	292	0	0
T11	205323	1674	0	0
T12	114395	278	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	919722	0	0
T1	2576	66	0	0
T2	15833	49	0	0
T3	163441	11856	0	0
T4	19347	152	0	0
T7	40402	476	0	0
T8	336404	32	0	0
T9	10380	81	0	0
T10	30721	292	0	0
T11	205323	1674	0	0
T12	114395	278	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	352008344	0	0
T1	2576	1	0	0
T2	15833	13944	0	0
T3	163441	1	0	0
T4	19347	15927	0	0
T7	40402	33389	0	0
T8	336404	325856	0	0
T9	10380	8876	0	0
T10	30721	25853	0	0
T11	205323	174189	0	0
T12	114395	103601	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	919722	0	0
T1	2576	66	0	0
T2	15833	49	0	0
T3	163441	11856	0	0
T4	19347	152	0	0
T7	40402	476	0	0
T8	336404	32	0	0
T9	10380	81	0	0
T10	30721	292	0	0
T11	205323	1674	0	0
T12	114395	278	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	919722	0	0
T1	2576	66	0	0
T2	15833	49	0	0
T3	163441	11856	0	0
T4	19347	152	0	0
T7	40402	476	0	0
T8	336404	32	0	0
T9	10380	81	0	0
T10	30721	292	0	0
T11	205323	1674	0	0
T12	114395	278	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	14159356	0	0
T1	2576	66	0	0
T2	15833	385	0	0
T3	163441	11856	0	0
T4	19347	1319	0	0
T7	40402	3827	0	0
T8	336404	9873	0	0
T9	10380	634	0	0
T10	30721	2363	0	0
T11	205323	13750	0	0
T12	114395	105867	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	35805	0	900
T3	163441	841	0	1
T4	19347	0	0	1
T7	40402	1	0	1
T8	336404	0	0	1
T9	10380	0	0	1
T10	30721	0	0	1
T11	205323	2	0	1
T12	114395	0	0	1
T13	209805	0	0	1
T14	0	4	0	0
T16	0	25	0	0
T17	0	14	0	0
T18	0	9	0	0
T19	0	3	0	0
T20	0	440	0	0
T21	0	7	0	0
T24	260429	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	419391272	0	0
T1	2576	2526	0	0
T2	15833	15744	0	0
T3	163441	163075	0	0
T4	19347	19263	0	0
T7	40402	40367	0	0
T8	336404	336383	0	0
T9	10380	10364	0	0
T10	30721	30703	0	0
T11	205323	204834	0	0
T12	114395	114389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419518677	919722	0	0
T1	2576	66	0	0
T2	15833	49	0	0
T3	163441	11856	0	0
T4	19347	152	0	0
T7	40402	476	0	0
T8	336404	32	0	0
T9	10380	81	0	0
T10	30721	292	0	0
T11	205323	1674	0	0
T12	114395	278	0	0