Line Coverage for Module :
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Line Coverage for Module :
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Module :
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T9 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T9 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
tlul_socket_m1
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
23341982 |
0 |
0 |
T1 |
9382666 |
21392 |
0 |
0 |
T2 |
6324264 |
277854 |
0 |
0 |
T3 |
176496 |
2027 |
0 |
0 |
T7 |
7540392 |
437 |
0 |
0 |
T8 |
220728 |
1140 |
0 |
0 |
T9 |
273120 |
789 |
0 |
0 |
T10 |
1775736 |
11413 |
0 |
0 |
T11 |
9472224 |
536 |
0 |
0 |
T12 |
1135200 |
6887 |
0 |
0 |
T13 |
387936 |
6406 |
0 |
0 |
T23 |
544783 |
33 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
12799057 |
0 |
0 |
T1 |
9382666 |
5927 |
0 |
0 |
T2 |
6324264 |
107761 |
0 |
0 |
T3 |
176496 |
1103 |
0 |
0 |
T7 |
7540392 |
260 |
0 |
0 |
T8 |
220728 |
498 |
0 |
0 |
T9 |
273120 |
186 |
0 |
0 |
T10 |
1775736 |
5112 |
0 |
0 |
T11 |
9472224 |
240 |
0 |
0 |
T12 |
1135200 |
3012 |
0 |
0 |
T13 |
387936 |
3223 |
0 |
0 |
T23 |
544783 |
49 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1684855740 |
3697478 |
0 |
0 |
T1 |
1631768 |
1438 |
0 |
0 |
T2 |
1054044 |
60605 |
0 |
0 |
T3 |
29416 |
137 |
0 |
0 |
T7 |
1256732 |
35 |
0 |
0 |
T8 |
36788 |
99 |
0 |
0 |
T9 |
45520 |
38 |
0 |
0 |
T10 |
295956 |
1654 |
0 |
0 |
T11 |
1578704 |
61 |
0 |
0 |
T12 |
189200 |
909 |
0 |
0 |
T13 |
64656 |
435 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21600 |
21600 |
0 |
0 |
T1 |
24 |
24 |
0 |
0 |
T2 |
24 |
24 |
0 |
0 |
T3 |
24 |
24 |
0 |
0 |
T7 |
24 |
24 |
0 |
0 |
T8 |
24 |
24 |
0 |
0 |
T9 |
24 |
24 |
0 |
0 |
T10 |
24 |
24 |
0 |
0 |
T11 |
24 |
24 |
0 |
0 |
T12 |
24 |
24 |
0 |
0 |
T13 |
24 |
24 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
160598639 |
0 |
0 |
T1 |
9790608 |
70322 |
0 |
0 |
T2 |
6324264 |
1015869 |
0 |
0 |
T3 |
176496 |
2845 |
0 |
0 |
T7 |
7540392 |
59274 |
0 |
0 |
T8 |
220728 |
2396 |
0 |
0 |
T9 |
273120 |
928 |
0 |
0 |
T10 |
1775736 |
18238 |
0 |
0 |
T11 |
9472224 |
141726 |
0 |
0 |
T12 |
1135200 |
20150 |
0 |
0 |
T13 |
387936 |
8380 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_28
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_28
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_28
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
1707969 |
0 |
0 |
T1 |
407942 |
2166 |
0 |
0 |
T2 |
263511 |
22385 |
0 |
0 |
T3 |
7354 |
254 |
0 |
0 |
T7 |
314183 |
43 |
0 |
0 |
T8 |
9197 |
104 |
0 |
0 |
T9 |
11380 |
71 |
0 |
0 |
T10 |
73989 |
1104 |
0 |
0 |
T11 |
394676 |
59 |
0 |
0 |
T12 |
47300 |
685 |
0 |
0 |
T13 |
16164 |
740 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
400836 |
0 |
0 |
T1 |
407942 |
2 |
0 |
0 |
T2 |
263511 |
4508 |
0 |
0 |
T3 |
7354 |
48 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
14 |
0 |
0 |
T9 |
11380 |
11 |
0 |
0 |
T10 |
73989 |
255 |
0 |
0 |
T11 |
394676 |
11 |
0 |
0 |
T12 |
47300 |
181 |
0 |
0 |
T13 |
16164 |
150 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
541891 |
0 |
0 |
T1 |
407942 |
5 |
0 |
0 |
T2 |
263511 |
5609 |
0 |
0 |
T3 |
7354 |
29 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
6 |
0 |
0 |
T9 |
11380 |
3 |
0 |
0 |
T10 |
73989 |
221 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
127 |
0 |
0 |
T13 |
16164 |
102 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
18419591 |
0 |
0 |
T1 |
407942 |
19316 |
0 |
0 |
T2 |
263511 |
71571 |
0 |
0 |
T3 |
7354 |
329 |
0 |
0 |
T7 |
314183 |
3612 |
0 |
0 |
T8 |
9197 |
372 |
0 |
0 |
T9 |
11380 |
117 |
0 |
0 |
T10 |
73989 |
2512 |
0 |
0 |
T11 |
394676 |
21021 |
0 |
0 |
T12 |
47300 |
3541 |
0 |
0 |
T13 |
16164 |
982 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_29
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_29
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_29
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
1820043 |
0 |
0 |
T1 |
407942 |
625 |
0 |
0 |
T2 |
263511 |
15054 |
0 |
0 |
T3 |
7354 |
263 |
0 |
0 |
T7 |
314183 |
78 |
0 |
0 |
T8 |
9197 |
90 |
0 |
0 |
T9 |
11380 |
51 |
0 |
0 |
T10 |
73989 |
1193 |
0 |
0 |
T11 |
394676 |
80 |
0 |
0 |
T12 |
47300 |
772 |
0 |
0 |
T13 |
16164 |
930 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
447061 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
8267 |
0 |
0 |
T3 |
7354 |
45 |
0 |
0 |
T7 |
314183 |
5 |
0 |
0 |
T8 |
9197 |
13 |
0 |
0 |
T9 |
11380 |
9 |
0 |
0 |
T10 |
73989 |
172 |
0 |
0 |
T11 |
394676 |
9 |
0 |
0 |
T12 |
47300 |
107 |
0 |
0 |
T13 |
16164 |
141 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
566848 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
6324 |
0 |
0 |
T3 |
7354 |
37 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
22 |
0 |
0 |
T9 |
11380 |
2 |
0 |
0 |
T10 |
73989 |
343 |
0 |
0 |
T11 |
394676 |
3 |
0 |
0 |
T12 |
47300 |
166 |
0 |
0 |
T13 |
16164 |
120 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
19172514 |
0 |
0 |
T1 |
407942 |
14003 |
0 |
0 |
T2 |
263511 |
72093 |
0 |
0 |
T3 |
7354 |
310 |
0 |
0 |
T7 |
314183 |
2058 |
0 |
0 |
T8 |
9197 |
323 |
0 |
0 |
T9 |
11380 |
112 |
0 |
0 |
T10 |
73989 |
2352 |
0 |
0 |
T11 |
394676 |
22413 |
0 |
0 |
T12 |
47300 |
4071 |
0 |
0 |
T13 |
16164 |
922 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_31
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_31
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T9 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_31
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
1807216 |
0 |
0 |
T1 |
407942 |
991 |
0 |
0 |
T2 |
263511 |
16361 |
0 |
0 |
T3 |
7354 |
249 |
0 |
0 |
T7 |
314183 |
42 |
0 |
0 |
T8 |
9197 |
136 |
0 |
0 |
T9 |
11380 |
104 |
0 |
0 |
T10 |
73989 |
1216 |
0 |
0 |
T11 |
394676 |
73 |
0 |
0 |
T12 |
47300 |
746 |
0 |
0 |
T13 |
16164 |
938 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
428621 |
0 |
0 |
T1 |
407942 |
108 |
0 |
0 |
T2 |
263511 |
2597 |
0 |
0 |
T3 |
7354 |
51 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
7 |
0 |
0 |
T9 |
11380 |
7 |
0 |
0 |
T10 |
73989 |
212 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
109 |
0 |
0 |
T13 |
16164 |
153 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
573095 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
5173 |
0 |
0 |
T3 |
7354 |
32 |
0 |
0 |
T7 |
314183 |
4 |
0 |
0 |
T8 |
9197 |
29 |
0 |
0 |
T9 |
11380 |
5 |
0 |
0 |
T10 |
73989 |
210 |
0 |
0 |
T11 |
394676 |
6 |
0 |
0 |
T12 |
47300 |
220 |
0 |
0 |
T13 |
16164 |
114 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
19614115 |
0 |
0 |
T1 |
407942 |
16734 |
0 |
0 |
T2 |
263511 |
73392 |
0 |
0 |
T3 |
7354 |
290 |
0 |
0 |
T7 |
314183 |
2511 |
0 |
0 |
T8 |
9197 |
398 |
0 |
0 |
T9 |
11380 |
155 |
0 |
0 |
T10 |
73989 |
2178 |
0 |
0 |
T11 |
394676 |
18933 |
0 |
0 |
T12 |
47300 |
3457 |
0 |
0 |
T13 |
16164 |
937 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_33
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_33
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_33
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
265696 |
0 |
0 |
T1 |
407942 |
5 |
0 |
0 |
T2 |
263511 |
1160 |
0 |
0 |
T3 |
7354 |
40 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
6 |
0 |
0 |
T9 |
11380 |
6 |
0 |
0 |
T10 |
73989 |
139 |
0 |
0 |
T11 |
394676 |
10 |
0 |
0 |
T12 |
47300 |
94 |
0 |
0 |
T13 |
16164 |
133 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
356552 |
0 |
0 |
T1 |
407942 |
134 |
0 |
0 |
T2 |
263511 |
2668 |
0 |
0 |
T3 |
7354 |
31 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
7 |
0 |
0 |
T9 |
11380 |
1 |
0 |
0 |
T10 |
73989 |
153 |
0 |
0 |
T11 |
394676 |
6 |
0 |
0 |
T12 |
47300 |
105 |
0 |
0 |
T13 |
16164 |
119 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3925314 |
0 |
0 |
T1 |
407942 |
289 |
0 |
0 |
T2 |
263511 |
35339 |
0 |
0 |
T3 |
7354 |
70 |
0 |
0 |
T7 |
314183 |
3286 |
0 |
0 |
T8 |
9197 |
24 |
0 |
0 |
T9 |
11380 |
13 |
0 |
0 |
T10 |
73989 |
504 |
0 |
0 |
T11 |
394676 |
4257 |
0 |
0 |
T12 |
47300 |
293 |
0 |
0 |
T13 |
16164 |
237 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_34
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_34
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_34
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
288055 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
1825 |
0 |
0 |
T3 |
7354 |
36 |
0 |
0 |
T7 |
314183 |
5 |
0 |
0 |
T8 |
9197 |
7 |
0 |
0 |
T9 |
11380 |
11 |
0 |
0 |
T10 |
73989 |
95 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
114 |
0 |
0 |
T13 |
16164 |
134 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
381048 |
0 |
0 |
T1 |
407942 |
645 |
0 |
0 |
T2 |
263511 |
2613 |
0 |
0 |
T3 |
7354 |
35 |
0 |
0 |
T7 |
314183 |
8 |
0 |
0 |
T8 |
9197 |
4 |
0 |
0 |
T9 |
11380 |
4 |
0 |
0 |
T10 |
73989 |
152 |
0 |
0 |
T11 |
394676 |
6 |
0 |
0 |
T12 |
47300 |
131 |
0 |
0 |
T13 |
16164 |
83 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4031166 |
0 |
0 |
T1 |
407942 |
625 |
0 |
0 |
T2 |
263511 |
38012 |
0 |
0 |
T3 |
7354 |
70 |
0 |
0 |
T7 |
314183 |
1739 |
0 |
0 |
T8 |
9197 |
35 |
0 |
0 |
T9 |
11380 |
20 |
0 |
0 |
T10 |
73989 |
350 |
0 |
0 |
T11 |
394676 |
1475 |
0 |
0 |
T12 |
47300 |
281 |
0 |
0 |
T13 |
16164 |
208 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_36
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_36
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T12 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_36
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
685053 |
0 |
0 |
T2 |
263511 |
135 |
0 |
0 |
T3 |
7354 |
110 |
0 |
0 |
T7 |
314183 |
14 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
9 |
0 |
0 |
T10 |
73989 |
169 |
0 |
0 |
T11 |
394676 |
3 |
0 |
0 |
T12 |
47300 |
86 |
0 |
0 |
T13 |
16164 |
254 |
0 |
0 |
T23 |
544783 |
33 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
791955 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
429 |
0 |
0 |
T3 |
7354 |
64 |
0 |
0 |
T7 |
314183 |
9 |
0 |
0 |
T8 |
9197 |
9 |
0 |
0 |
T9 |
11380 |
9 |
0 |
0 |
T10 |
73989 |
162 |
0 |
0 |
T11 |
394676 |
11 |
0 |
0 |
T12 |
47300 |
92 |
0 |
0 |
T13 |
16164 |
170 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4237635 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
36803 |
0 |
0 |
T3 |
7354 |
96 |
0 |
0 |
T7 |
314183 |
1973 |
0 |
0 |
T8 |
9197 |
70 |
0 |
0 |
T9 |
11380 |
40 |
0 |
0 |
T10 |
73989 |
299 |
0 |
0 |
T11 |
394676 |
340 |
0 |
0 |
T12 |
47300 |
306 |
0 |
0 |
T13 |
16164 |
199 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_38
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_38
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T3,T8,T10 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T8,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_38
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
966920 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
1483 |
0 |
0 |
T3 |
7354 |
89 |
0 |
0 |
T7 |
314183 |
14 |
0 |
0 |
T8 |
9197 |
11 |
0 |
0 |
T9 |
11380 |
6 |
0 |
0 |
T10 |
73989 |
179 |
0 |
0 |
T11 |
394676 |
7 |
0 |
0 |
T12 |
47300 |
123 |
0 |
0 |
T13 |
16164 |
308 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
1089794 |
0 |
0 |
T1 |
407942 |
7 |
0 |
0 |
T2 |
263511 |
2546 |
0 |
0 |
T3 |
7354 |
117 |
0 |
0 |
T7 |
314183 |
2 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
4 |
0 |
0 |
T10 |
73989 |
162 |
0 |
0 |
T11 |
394676 |
2 |
0 |
0 |
T12 |
47300 |
209 |
0 |
0 |
T13 |
16164 |
174 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4711326 |
0 |
0 |
T1 |
407942 |
11 |
0 |
0 |
T2 |
263511 |
35058 |
0 |
0 |
T3 |
7354 |
73 |
0 |
0 |
T7 |
314183 |
1754 |
0 |
0 |
T8 |
9197 |
60 |
0 |
0 |
T9 |
11380 |
10 |
0 |
0 |
T10 |
73989 |
324 |
0 |
0 |
T11 |
394676 |
2563 |
0 |
0 |
T12 |
47300 |
279 |
0 |
0 |
T13 |
16164 |
234 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_40
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_40
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_40
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
664782 |
0 |
0 |
T1 |
407942 |
5 |
0 |
0 |
T2 |
263511 |
96 |
0 |
0 |
T3 |
7354 |
44 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
12 |
0 |
0 |
T9 |
11380 |
16 |
0 |
0 |
T10 |
73989 |
212 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
80 |
0 |
0 |
T13 |
16164 |
236 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
803535 |
0 |
0 |
T1 |
407942 |
2 |
0 |
0 |
T2 |
263511 |
1116 |
0 |
0 |
T3 |
7354 |
53 |
0 |
0 |
T7 |
314183 |
22 |
0 |
0 |
T8 |
9197 |
11 |
0 |
0 |
T9 |
11380 |
6 |
0 |
0 |
T10 |
73989 |
395 |
0 |
0 |
T11 |
394676 |
8 |
0 |
0 |
T12 |
47300 |
116 |
0 |
0 |
T13 |
16164 |
228 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4400174 |
0 |
0 |
T1 |
407942 |
256 |
0 |
0 |
T2 |
263511 |
45981 |
0 |
0 |
T3 |
7354 |
72 |
0 |
0 |
T7 |
314183 |
2524 |
0 |
0 |
T8 |
9197 |
46 |
0 |
0 |
T9 |
11380 |
10 |
0 |
0 |
T10 |
73989 |
441 |
0 |
0 |
T11 |
394676 |
2326 |
0 |
0 |
T12 |
47300 |
412 |
0 |
0 |
T13 |
16164 |
230 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_42
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_42
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_42
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
620437 |
0 |
0 |
T1 |
407942 |
1 |
0 |
0 |
T2 |
263511 |
80 |
0 |
0 |
T3 |
7354 |
74 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
39 |
0 |
0 |
T10 |
73989 |
293 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
80 |
0 |
0 |
T13 |
16164 |
199 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
748909 |
0 |
0 |
T1 |
407942 |
635 |
0 |
0 |
T2 |
263511 |
633 |
0 |
0 |
T3 |
7354 |
56 |
0 |
0 |
T7 |
314183 |
67 |
0 |
0 |
T8 |
9197 |
11 |
0 |
0 |
T9 |
11380 |
4 |
0 |
0 |
T10 |
73989 |
237 |
0 |
0 |
T11 |
394676 |
41 |
0 |
0 |
T12 |
47300 |
170 |
0 |
0 |
T13 |
16164 |
233 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4436433 |
0 |
0 |
T1 |
407942 |
7 |
0 |
0 |
T2 |
263511 |
32431 |
0 |
0 |
T3 |
7354 |
95 |
0 |
0 |
T7 |
314183 |
2030 |
0 |
0 |
T8 |
9197 |
62 |
0 |
0 |
T9 |
11380 |
11 |
0 |
0 |
T10 |
73989 |
441 |
0 |
0 |
T11 |
394676 |
2405 |
0 |
0 |
T12 |
47300 |
223 |
0 |
0 |
T13 |
16164 |
224 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_43
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T8,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_43
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
271035 |
0 |
0 |
T1 |
407942 |
8 |
0 |
0 |
T2 |
263511 |
1944 |
0 |
0 |
T3 |
7354 |
45 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
18 |
0 |
0 |
T9 |
11380 |
3 |
0 |
0 |
T10 |
73989 |
165 |
0 |
0 |
T11 |
394676 |
7 |
0 |
0 |
T12 |
47300 |
73 |
0 |
0 |
T13 |
16164 |
141 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
378296 |
0 |
0 |
T1 |
407942 |
3 |
0 |
0 |
T2 |
263511 |
5507 |
0 |
0 |
T3 |
7354 |
42 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
75 |
0 |
0 |
T9 |
11380 |
4 |
0 |
0 |
T10 |
73989 |
171 |
0 |
0 |
T11 |
394676 |
3 |
0 |
0 |
T12 |
47300 |
83 |
0 |
0 |
T13 |
16164 |
123 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4248065 |
0 |
0 |
T1 |
407942 |
228 |
0 |
0 |
T2 |
263511 |
37538 |
0 |
0 |
T3 |
7354 |
81 |
0 |
0 |
T7 |
314183 |
3579 |
0 |
0 |
T8 |
9197 |
63 |
0 |
0 |
T9 |
11380 |
11 |
0 |
0 |
T10 |
73989 |
501 |
0 |
0 |
T11 |
394676 |
2792 |
0 |
0 |
T12 |
47300 |
257 |
0 |
0 |
T13 |
16164 |
250 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_44
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T9,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_44
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
257916 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
2379 |
0 |
0 |
T3 |
7354 |
37 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
5 |
0 |
0 |
T10 |
73989 |
133 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
92 |
0 |
0 |
T13 |
16164 |
148 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
355673 |
0 |
0 |
T1 |
407942 |
9 |
0 |
0 |
T2 |
263511 |
2914 |
0 |
0 |
T3 |
7354 |
41 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
19 |
0 |
0 |
T9 |
11380 |
10 |
0 |
0 |
T10 |
73989 |
139 |
0 |
0 |
T11 |
394676 |
10 |
0 |
0 |
T12 |
47300 |
98 |
0 |
0 |
T13 |
16164 |
130 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4334201 |
0 |
0 |
T1 |
407942 |
312 |
0 |
0 |
T2 |
263511 |
36758 |
0 |
0 |
T3 |
7354 |
74 |
0 |
0 |
T7 |
314183 |
1299 |
0 |
0 |
T8 |
9197 |
33 |
0 |
0 |
T9 |
11380 |
45 |
0 |
0 |
T10 |
73989 |
447 |
0 |
0 |
T11 |
394676 |
2024 |
0 |
0 |
T12 |
47300 |
246 |
0 |
0 |
T13 |
16164 |
259 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_45
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_45
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
322911 |
0 |
0 |
T1 |
407942 |
3 |
0 |
0 |
T2 |
263511 |
1234 |
0 |
0 |
T3 |
7354 |
38 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
1 |
0 |
0 |
T9 |
11380 |
22 |
0 |
0 |
T10 |
73989 |
166 |
0 |
0 |
T11 |
394676 |
9 |
0 |
0 |
T12 |
47300 |
77 |
0 |
0 |
T13 |
16164 |
135 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
426782 |
0 |
0 |
T1 |
407942 |
367 |
0 |
0 |
T2 |
263511 |
2959 |
0 |
0 |
T3 |
7354 |
30 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
11 |
0 |
0 |
T9 |
11380 |
1 |
0 |
0 |
T10 |
73989 |
198 |
0 |
0 |
T11 |
394676 |
6 |
0 |
0 |
T12 |
47300 |
50 |
0 |
0 |
T13 |
16164 |
111 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
5541225 |
0 |
0 |
T1 |
407942 |
77 |
0 |
0 |
T2 |
263511 |
32115 |
0 |
0 |
T3 |
7354 |
65 |
0 |
0 |
T7 |
314183 |
1407 |
0 |
0 |
T8 |
9197 |
6 |
0 |
0 |
T9 |
11380 |
27 |
0 |
0 |
T10 |
73989 |
442 |
0 |
0 |
T11 |
394676 |
5002 |
0 |
0 |
T12 |
47300 |
204 |
0 |
0 |
T13 |
16164 |
237 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_46
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_46
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
252400 |
0 |
0 |
T1 |
407942 |
2 |
0 |
0 |
T2 |
263511 |
944 |
0 |
0 |
T3 |
7354 |
37 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
7 |
0 |
0 |
T10 |
73989 |
131 |
0 |
0 |
T11 |
394676 |
13 |
0 |
0 |
T12 |
47300 |
92 |
0 |
0 |
T13 |
16164 |
117 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
360663 |
0 |
0 |
T1 |
407942 |
6 |
0 |
0 |
T2 |
263511 |
2995 |
0 |
0 |
T3 |
7354 |
41 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
6 |
0 |
0 |
T9 |
11380 |
1 |
0 |
0 |
T10 |
73989 |
168 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
67 |
0 |
0 |
T13 |
16164 |
120 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4177475 |
0 |
0 |
T1 |
407942 |
8 |
0 |
0 |
T2 |
263511 |
30919 |
0 |
0 |
T3 |
7354 |
75 |
0 |
0 |
T7 |
314183 |
1460 |
0 |
0 |
T8 |
9197 |
59 |
0 |
0 |
T9 |
11380 |
7 |
0 |
0 |
T10 |
73989 |
459 |
0 |
0 |
T11 |
394676 |
4213 |
0 |
0 |
T12 |
47300 |
228 |
0 |
0 |
T13 |
16164 |
227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_47
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T2,T3,T9 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T9,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_47
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
285268 |
0 |
0 |
T1 |
407942 |
2 |
0 |
0 |
T2 |
263511 |
870 |
0 |
0 |
T3 |
7354 |
46 |
0 |
0 |
T7 |
314183 |
20 |
0 |
0 |
T8 |
9197 |
4 |
0 |
0 |
T9 |
11380 |
10 |
0 |
0 |
T10 |
73989 |
111 |
0 |
0 |
T11 |
394676 |
8 |
0 |
0 |
T12 |
47300 |
95 |
0 |
0 |
T13 |
16164 |
135 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
377868 |
0 |
0 |
T1 |
407942 |
3 |
0 |
0 |
T2 |
263511 |
2490 |
0 |
0 |
T3 |
7354 |
44 |
0 |
0 |
T7 |
314183 |
13 |
0 |
0 |
T8 |
9197 |
4 |
0 |
0 |
T9 |
11380 |
3 |
0 |
0 |
T10 |
73989 |
127 |
0 |
0 |
T11 |
394676 |
17 |
0 |
0 |
T12 |
47300 |
99 |
0 |
0 |
T13 |
16164 |
89 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3822241 |
0 |
0 |
T1 |
407942 |
5 |
0 |
0 |
T2 |
263511 |
39624 |
0 |
0 |
T3 |
7354 |
87 |
0 |
0 |
T7 |
314183 |
6206 |
0 |
0 |
T8 |
9197 |
26 |
0 |
0 |
T9 |
11380 |
11 |
0 |
0 |
T10 |
73989 |
451 |
0 |
0 |
T11 |
394676 |
5006 |
0 |
0 |
T12 |
47300 |
324 |
0 |
0 |
T13 |
16164 |
207 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_48
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
282992 |
0 |
0 |
T1 |
407942 |
403 |
0 |
0 |
T2 |
263511 |
591 |
0 |
0 |
T3 |
7354 |
37 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
7 |
0 |
0 |
T9 |
11380 |
15 |
0 |
0 |
T10 |
73989 |
174 |
0 |
0 |
T11 |
394676 |
5 |
0 |
0 |
T12 |
47300 |
85 |
0 |
0 |
T13 |
16164 |
108 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
363112 |
0 |
0 |
T1 |
407942 |
288 |
0 |
0 |
T2 |
263511 |
3211 |
0 |
0 |
T3 |
7354 |
32 |
0 |
0 |
T7 |
314183 |
9 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
4 |
0 |
0 |
T10 |
73989 |
165 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
95 |
0 |
0 |
T13 |
16164 |
135 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3741442 |
0 |
0 |
T1 |
407942 |
80 |
0 |
0 |
T2 |
263511 |
39146 |
0 |
0 |
T3 |
7354 |
67 |
0 |
0 |
T7 |
314183 |
1686 |
0 |
0 |
T8 |
9197 |
45 |
0 |
0 |
T9 |
11380 |
19 |
0 |
0 |
T10 |
73989 |
453 |
0 |
0 |
T11 |
394676 |
2403 |
0 |
0 |
T12 |
47300 |
257 |
0 |
0 |
T13 |
16164 |
238 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_49
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T9,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
292301 |
0 |
0 |
T1 |
407942 |
340 |
0 |
0 |
T2 |
263511 |
1356 |
0 |
0 |
T3 |
7354 |
49 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
11 |
0 |
0 |
T9 |
11380 |
6 |
0 |
0 |
T10 |
73989 |
152 |
0 |
0 |
T11 |
394676 |
7 |
0 |
0 |
T12 |
47300 |
107 |
0 |
0 |
T13 |
16164 |
148 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
390191 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
4247 |
0 |
0 |
T3 |
7354 |
46 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
6 |
0 |
0 |
T9 |
11380 |
9 |
0 |
0 |
T10 |
73989 |
150 |
0 |
0 |
T11 |
394676 |
3 |
0 |
0 |
T12 |
47300 |
84 |
0 |
0 |
T13 |
16164 |
129 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3649426 |
0 |
0 |
T1 |
407942 |
166 |
0 |
0 |
T2 |
263511 |
27527 |
0 |
0 |
T3 |
7354 |
87 |
0 |
0 |
T7 |
314183 |
1383 |
0 |
0 |
T8 |
9197 |
37 |
0 |
0 |
T9 |
11380 |
25 |
0 |
0 |
T10 |
73989 |
416 |
0 |
0 |
T11 |
394676 |
2394 |
0 |
0 |
T12 |
47300 |
331 |
0 |
0 |
T13 |
16164 |
265 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_50
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_50
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
313338 |
0 |
0 |
T1 |
407942 |
7 |
0 |
0 |
T2 |
263511 |
1319 |
0 |
0 |
T3 |
7354 |
40 |
0 |
0 |
T7 |
314183 |
9 |
0 |
0 |
T8 |
9197 |
16 |
0 |
0 |
T9 |
11380 |
7 |
0 |
0 |
T10 |
73989 |
151 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
74 |
0 |
0 |
T13 |
16164 |
116 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
420858 |
0 |
0 |
T1 |
407942 |
673 |
0 |
0 |
T2 |
263511 |
2756 |
0 |
0 |
T3 |
7354 |
26 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
7 |
0 |
0 |
T9 |
11380 |
3 |
0 |
0 |
T10 |
73989 |
154 |
0 |
0 |
T11 |
394676 |
10 |
0 |
0 |
T12 |
47300 |
84 |
0 |
0 |
T13 |
16164 |
120 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4619043 |
0 |
0 |
T1 |
407942 |
690 |
0 |
0 |
T2 |
263511 |
30069 |
0 |
0 |
T3 |
7354 |
64 |
0 |
0 |
T7 |
314183 |
2949 |
0 |
0 |
T8 |
9197 |
17 |
0 |
0 |
T9 |
11380 |
23 |
0 |
0 |
T10 |
73989 |
416 |
0 |
0 |
T11 |
394676 |
2446 |
0 |
0 |
T12 |
47300 |
317 |
0 |
0 |
T13 |
16164 |
219 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_51
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T10,T11 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_51
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
308111 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
1031 |
0 |
0 |
T3 |
7354 |
87 |
0 |
0 |
T7 |
314183 |
13 |
0 |
0 |
T8 |
9197 |
18 |
0 |
0 |
T9 |
11380 |
5 |
0 |
0 |
T10 |
73989 |
140 |
0 |
0 |
T11 |
394676 |
15 |
0 |
0 |
T12 |
47300 |
70 |
0 |
0 |
T13 |
16164 |
143 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
410118 |
0 |
0 |
T1 |
407942 |
5 |
0 |
0 |
T2 |
263511 |
3264 |
0 |
0 |
T3 |
7354 |
76 |
0 |
0 |
T7 |
314183 |
2 |
0 |
0 |
T8 |
9197 |
14 |
0 |
0 |
T9 |
11380 |
5 |
0 |
0 |
T10 |
73989 |
232 |
0 |
0 |
T11 |
394676 |
5 |
0 |
0 |
T12 |
47300 |
72 |
0 |
0 |
T13 |
16164 |
117 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3626328 |
0 |
0 |
T1 |
407942 |
366 |
0 |
0 |
T2 |
263511 |
35391 |
0 |
0 |
T3 |
7354 |
153 |
0 |
0 |
T7 |
314183 |
2941 |
0 |
0 |
T8 |
9197 |
80 |
0 |
0 |
T9 |
11380 |
14 |
0 |
0 |
T10 |
73989 |
467 |
0 |
0 |
T11 |
394676 |
5212 |
0 |
0 |
T12 |
47300 |
256 |
0 |
0 |
T13 |
16164 |
242 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_52
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T8,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
321725 |
0 |
0 |
T1 |
407942 |
7 |
0 |
0 |
T2 |
263511 |
2754 |
0 |
0 |
T3 |
7354 |
51 |
0 |
0 |
T7 |
314183 |
9 |
0 |
0 |
T8 |
9197 |
124 |
0 |
0 |
T9 |
11380 |
7 |
0 |
0 |
T10 |
73989 |
115 |
0 |
0 |
T11 |
394676 |
2 |
0 |
0 |
T12 |
47300 |
91 |
0 |
0 |
T13 |
16164 |
123 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
420003 |
0 |
0 |
T1 |
407942 |
5 |
0 |
0 |
T2 |
263511 |
2514 |
0 |
0 |
T3 |
7354 |
39 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
142 |
0 |
0 |
T9 |
11380 |
2 |
0 |
0 |
T10 |
73989 |
179 |
0 |
0 |
T11 |
394676 |
5 |
0 |
0 |
T12 |
47300 |
82 |
0 |
0 |
T13 |
16164 |
132 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3888039 |
0 |
0 |
T1 |
407942 |
61 |
0 |
0 |
T2 |
263511 |
36712 |
0 |
0 |
T3 |
7354 |
85 |
0 |
0 |
T7 |
314183 |
4459 |
0 |
0 |
T8 |
9197 |
149 |
0 |
0 |
T9 |
11380 |
17 |
0 |
0 |
T10 |
73989 |
399 |
0 |
0 |
T11 |
394676 |
1513 |
0 |
0 |
T12 |
47300 |
253 |
0 |
0 |
T13 |
16164 |
240 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_53
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T9 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
284347 |
0 |
0 |
T1 |
407942 |
424 |
0 |
0 |
T2 |
263511 |
280 |
0 |
0 |
T3 |
7354 |
39 |
0 |
0 |
T7 |
314183 |
8 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
5 |
0 |
0 |
T10 |
73989 |
128 |
0 |
0 |
T11 |
394676 |
14 |
0 |
0 |
T12 |
47300 |
85 |
0 |
0 |
T13 |
16164 |
121 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
381694 |
0 |
0 |
T1 |
407942 |
642 |
0 |
0 |
T2 |
263511 |
967 |
0 |
0 |
T3 |
7354 |
39 |
0 |
0 |
T7 |
314183 |
10 |
0 |
0 |
T8 |
9197 |
8 |
0 |
0 |
T9 |
11380 |
8 |
0 |
0 |
T10 |
73989 |
156 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
80 |
0 |
0 |
T13 |
16164 |
105 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4896173 |
0 |
0 |
T1 |
407942 |
874 |
0 |
0 |
T2 |
263511 |
33379 |
0 |
0 |
T3 |
7354 |
73 |
0 |
0 |
T7 |
314183 |
2035 |
0 |
0 |
T8 |
9197 |
30 |
0 |
0 |
T9 |
11380 |
21 |
0 |
0 |
T10 |
73989 |
402 |
0 |
0 |
T11 |
394676 |
4857 |
0 |
0 |
T12 |
47300 |
290 |
0 |
0 |
T13 |
16164 |
207 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_54
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
286765 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
281 |
0 |
0 |
T3 |
7354 |
38 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
10 |
0 |
0 |
T9 |
11380 |
3 |
0 |
0 |
T10 |
73989 |
129 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
89 |
0 |
0 |
T13 |
16164 |
130 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
391090 |
0 |
0 |
T1 |
407942 |
235 |
0 |
0 |
T2 |
263511 |
2526 |
0 |
0 |
T3 |
7354 |
37 |
0 |
0 |
T7 |
314183 |
6 |
0 |
0 |
T8 |
9197 |
12 |
0 |
0 |
T9 |
11380 |
2 |
0 |
0 |
T10 |
73989 |
133 |
0 |
0 |
T11 |
394676 |
4 |
0 |
0 |
T12 |
47300 |
133 |
0 |
0 |
T13 |
16164 |
112 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
3904269 |
0 |
0 |
T1 |
407942 |
141 |
0 |
0 |
T2 |
263511 |
34709 |
0 |
0 |
T3 |
7354 |
73 |
0 |
0 |
T7 |
314183 |
2779 |
0 |
0 |
T8 |
9197 |
44 |
0 |
0 |
T9 |
11380 |
5 |
0 |
0 |
T10 |
73989 |
530 |
0 |
0 |
T11 |
394676 |
669 |
0 |
0 |
T12 |
47300 |
300 |
0 |
0 |
T13 |
16164 |
232 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_55
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T9,T10 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_55
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
288765 |
0 |
0 |
T1 |
407942 |
1 |
0 |
0 |
T2 |
263511 |
1131 |
0 |
0 |
T3 |
7354 |
31 |
0 |
0 |
T7 |
314183 |
4 |
0 |
0 |
T8 |
9197 |
12 |
0 |
0 |
T9 |
11380 |
3 |
0 |
0 |
T10 |
73989 |
146 |
0 |
0 |
T11 |
394676 |
10 |
0 |
0 |
T12 |
47300 |
64 |
0 |
0 |
T13 |
16164 |
143 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
376388 |
0 |
0 |
T2 |
263511 |
576 |
0 |
0 |
T3 |
7354 |
41 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
14 |
0 |
0 |
T9 |
11380 |
7 |
0 |
0 |
T10 |
73989 |
177 |
0 |
0 |
T11 |
394676 |
8 |
0 |
0 |
T12 |
47300 |
107 |
0 |
0 |
T13 |
16164 |
110 |
0 |
0 |
T23 |
544783 |
49 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4372253 |
0 |
0 |
T1 |
407942 |
1 |
0 |
0 |
T2 |
263511 |
32765 |
0 |
0 |
T3 |
7354 |
70 |
0 |
0 |
T7 |
314183 |
2166 |
0 |
0 |
T8 |
9197 |
58 |
0 |
0 |
T9 |
11380 |
22 |
0 |
0 |
T10 |
73989 |
481 |
0 |
0 |
T11 |
394676 |
4108 |
0 |
0 |
T12 |
47300 |
224 |
0 |
0 |
T13 |
16164 |
243 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_56
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T7,T8 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T8,T9 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
278119 |
0 |
0 |
T1 |
407942 |
4 |
0 |
0 |
T2 |
263511 |
1160 |
0 |
0 |
T3 |
7354 |
44 |
0 |
0 |
T7 |
314183 |
7 |
0 |
0 |
T8 |
9197 |
4 |
0 |
0 |
T9 |
11380 |
4 |
0 |
0 |
T10 |
73989 |
126 |
0 |
0 |
T11 |
394676 |
3 |
0 |
0 |
T12 |
47300 |
102 |
0 |
0 |
T13 |
16164 |
139 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
375315 |
0 |
0 |
T1 |
407942 |
3 |
0 |
0 |
T2 |
263511 |
4228 |
0 |
0 |
T3 |
7354 |
30 |
0 |
0 |
T7 |
314183 |
5 |
0 |
0 |
T8 |
9197 |
20 |
0 |
0 |
T9 |
11380 |
11 |
0 |
0 |
T10 |
73989 |
150 |
0 |
0 |
T11 |
394676 |
5 |
0 |
0 |
T12 |
47300 |
102 |
0 |
0 |
T13 |
16164 |
104 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
4290946 |
0 |
0 |
T1 |
407942 |
7 |
0 |
0 |
T2 |
263511 |
34806 |
0 |
0 |
T3 |
7354 |
69 |
0 |
0 |
T7 |
314183 |
1096 |
0 |
0 |
T8 |
9197 |
26 |
0 |
0 |
T9 |
11380 |
15 |
0 |
0 |
T10 |
73989 |
369 |
0 |
0 |
T11 |
394676 |
1332 |
0 |
0 |
T12 |
47300 |
243 |
0 |
0 |
T13 |
16164 |
232 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_30
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_30
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T9 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T9 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T9 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_30
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
10469818 |
0 |
0 |
T1 |
407942 |
16378 |
0 |
0 |
T2 |
263511 |
202001 |
0 |
0 |
T3 |
7354 |
249 |
0 |
0 |
T7 |
314183 |
103 |
0 |
0 |
T8 |
9197 |
499 |
0 |
0 |
T9 |
11380 |
374 |
0 |
0 |
T10 |
73989 |
4846 |
0 |
0 |
T11 |
394676 |
187 |
0 |
0 |
T12 |
47300 |
2911 |
0 |
0 |
T13 |
16164 |
687 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
1922695 |
0 |
0 |
T1 |
407942 |
2143 |
0 |
0 |
T2 |
263511 |
41230 |
0 |
0 |
T3 |
7354 |
39 |
0 |
0 |
T7 |
314183 |
31 |
0 |
0 |
T8 |
9197 |
64 |
0 |
0 |
T9 |
11380 |
61 |
0 |
0 |
T10 |
73989 |
913 |
0 |
0 |
T11 |
394676 |
54 |
0 |
0 |
T12 |
47300 |
556 |
0 |
0 |
T13 |
16164 |
135 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
2015644 |
0 |
0 |
T1 |
407942 |
1425 |
0 |
0 |
T2 |
263511 |
43499 |
0 |
0 |
T3 |
7354 |
39 |
0 |
0 |
T7 |
314183 |
19 |
0 |
0 |
T8 |
9197 |
42 |
0 |
0 |
T9 |
11380 |
28 |
0 |
0 |
T10 |
73989 |
880 |
0 |
0 |
T11 |
394676 |
48 |
0 |
0 |
T12 |
47300 |
396 |
0 |
0 |
T13 |
16164 |
99 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421213935 |
18539245 |
0 |
0 |
T1 |
407942 |
16061 |
0 |
0 |
T2 |
263511 |
93731 |
0 |
0 |
T3 |
7354 |
317 |
0 |
0 |
T7 |
314183 |
2342 |
0 |
0 |
T8 |
9197 |
333 |
0 |
0 |
T9 |
11380 |
178 |
0 |
0 |
T10 |
73989 |
2604 |
0 |
0 |
T11 |
394676 |
22022 |
0 |
0 |
T12 |
47300 |
3557 |
0 |
0 |
T13 |
16164 |
909 |
0 |
0 |