Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7592625	0	0
GntImpliesValid_A	2147483647	7592625	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7592625	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	461206765	0	0
ReadyAndValidImplyGrant_A	2147483647	7592625	0	0
ReqAndReadyImplyGrant_A	2147483647	7592625	0	0
ReqImpliesValid_A	2147483647	34834622	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	36073	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7592625	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9790608	9789840	0	0
T2	6324264	6324216	0	0
T3	176496	175920	0	0
T7	7540392	7538880	0	0
T8	220728	213336	0	0
T9	273120	271968	0	0
T10	1775736	1774704	0	0
T11	9472224	9471216	0	0
T12	1135200	1134792	0	0
T13	387936	386568	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7592625	0	0
T1	9790608	413	0	0
T2	6324264	7237	0	0
T3	176496	2845	0	0
T7	7540392	443	0	0
T8	220728	814	0	0
T9	273120	441	0	0
T10	1775736	7917	0	0
T11	9472224	480	0	0
T12	1135200	4909	0	0
T13	387936	8380	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7592625	0	0
T1	9790608	413	0	0
T2	6324264	7237	0	0
T3	176496	2845	0	0
T7	7540392	443	0	0
T8	220728	814	0	0
T9	273120	441	0	0
T10	1775736	7917	0	0
T11	9472224	480	0	0
T12	1135200	4909	0	0
T13	387936	8380	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9790608	9789840	0	0
T2	6324264	6324216	0	0
T3	176496	175920	0	0
T7	7540392	7538880	0	0
T8	220728	213336	0	0
T9	273120	271968	0	0
T10	1775736	1774704	0	0
T11	9472224	9471216	0	0
T12	1135200	1134792	0	0
T13	387936	386568	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9790608	9789840	0	0
T2	6324264	6324216	0	0
T3	176496	175920	0	0
T7	7540392	7538880	0	0
T8	220728	213336	0	0
T9	273120	271968	0	0
T10	1775736	1774704	0	0
T11	9472224	9471216	0	0
T12	1135200	1134792	0	0
T13	387936	386568	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7592625	0	0
T1	9790608	413	0	0
T2	6324264	7237	0	0
T3	176496	2845	0	0
T7	7540392	443	0	0
T8	220728	814	0	0
T9	273120	441	0	0
T10	1775736	7917	0	0
T11	9472224	480	0	0
T12	1135200	4909	0	0
T13	387936	8380	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	461206765	0	0
T1	9790608	507893	0	0
T2	6324264	2170376	0	0
T3	176496	3864	0	0
T7	7540392	264097	0	0
T8	220728	12546	0	0
T9	273120	13610	0	0
T10	1775736	117988	0	0
T11	9472224	330617	0	0
T12	1135200	72690	0	0
T13	387936	11521	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7592625	0	0
T1	9790608	413	0	0
T2	6324264	7237	0	0
T3	176496	2845	0	0
T7	7540392	443	0	0
T8	220728	814	0	0
T9	273120	441	0	0
T10	1775736	7917	0	0
T11	9472224	480	0	0
T12	1135200	4909	0	0
T13	387936	8380	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7592625	0	0
T1	9790608	413	0	0
T2	6324264	7237	0	0
T3	176496	2845	0	0
T7	7540392	443	0	0
T8	220728	814	0	0
T9	273120	441	0	0
T10	1775736	7917	0	0
T11	9472224	480	0	0
T12	1135200	4909	0	0
T13	387936	8380	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34834622	0	0
T1	9790608	28757	0	0
T2	6324264	430374	0	0
T3	176496	3219	0	0
T7	7540392	732	0	0
T8	220728	1672	0	0
T9	273120	1013	0	0
T10	1775736	17895	0	0
T11	9472224	837	0	0
T12	1135200	10680	0	0
T13	387936	9939	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36073	0	21600
T3	14708	9	0	2
T6	0	18	0	0
T7	628366	0	0	2
T8	18394	0	0	2
T9	22760	0	0	2
T10	147978	4	0	2
T11	789352	0	0	2
T12	94600	0	0	2
T13	32328	30	0	2
T14	0	2	0	0
T15	0	12	0	0
T16	0	1	0	0
T17	0	7	0	0
T18	0	66	0	0
T19	0	20	0	0
T20	0	1	0	0
T21	0	1098	0	0
T22	0	6	0	0
T23	1089566	0	0	2
T24	257128	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9790608	9789840	0	0
T2	6324264	6324216	0	0
T3	176496	175920	0	0
T7	7540392	7538880	0	0
T8	220728	213336	0	0
T9	273120	271968	0	0
T10	1775736	1774704	0	0
T11	9472224	9471216	0	0
T12	1135200	1134792	0	0
T13	387936	386568	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7592625	0	0
T1	9790608	413	0	0
T2	6324264	7237	0	0
T3	176496	2845	0	0
T7	7540392	443	0	0
T8	220728	814	0	0
T9	273120	441	0	0
T10	1775736	7917	0	0
T11	9472224	480	0	0
T12	1135200	4909	0	0
T13	387936	8380	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	830513	0	0
GntImpliesValid_A	421213935	830513	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	830513	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	12454106	0	0
ReadyAndValidImplyGrant_A	421213935	830513	0	0
ReqAndReadyImplyGrant_A	421213935	830513	0	0
ReqImpliesValid_A	421213935	2435533	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	830513	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	830513	0	0
T1	407942	55	0	0
T2	263511	730	0	0
T3	7354	310	0	0
T7	314183	57	0	0
T8	9197	93	0	0
T9	11380	52	0	0
T10	73989	916	0	0
T11	394676	65	0	0
T12	47300	601	0	0
T13	16164	922	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	830513	0	0
T1	407942	55	0	0
T2	263511	730	0	0
T3	7354	310	0	0
T7	314183	57	0	0
T8	9197	93	0	0
T9	11380	52	0	0
T10	73989	916	0	0
T11	394676	65	0	0
T12	47300	601	0	0
T13	16164	922	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	830513	0	0
T1	407942	55	0	0
T2	263511	730	0	0
T3	7354	310	0	0
T7	314183	57	0	0
T8	9197	93	0	0
T9	11380	52	0	0
T10	73989	916	0	0
T11	394676	65	0	0
T12	47300	601	0	0
T13	16164	922	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	12454106	0	0
T1	407942	17892	0	0
T2	263511	235073	0	0
T3	7354	276	0	0
T7	314183	257	0	0
T8	9197	752	0	0
T9	11380	391	0	0
T10	73989	6971	0	0
T11	394676	264	0	0
T12	47300	4084	0	0
T13	16164	683	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	830513	0	0
T1	407942	55	0	0
T2	263511	730	0	0
T3	7354	310	0	0
T7	314183	57	0	0
T8	9197	93	0	0
T9	11380	52	0	0
T10	73989	916	0	0
T11	394676	65	0	0
T12	47300	601	0	0
T13	16164	922	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	830513	0	0
T1	407942	55	0	0
T2	263511	730	0	0
T3	7354	310	0	0
T7	314183	57	0	0
T8	9197	93	0	0
T9	11380	52	0	0
T10	73989	916	0	0
T11	394676	65	0	0
T12	47300	601	0	0
T13	16164	922	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	2435533	0	0
T1	407942	633	0	0
T2	263511	27803	0	0
T3	7354	345	0	0
T7	314183	89	0	0
T8	9197	125	0	0
T9	11380	62	0	0
T10	73989	1701	0	0
T11	394676	92	0	0
T12	47300	1040	0	0
T13	16164	1162	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	830513	0	0
T1	407942	55	0	0
T2	263511	730	0	0
T3	7354	310	0	0
T7	314183	57	0	0
T8	9197	93	0	0
T9	11380	52	0	0
T10	73989	916	0	0
T11	394676	65	0	0
T12	47300	601	0	0
T13	16164	922	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	842244	0	0
GntImpliesValid_A	421213935	842244	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	842244	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	12550977	0	0
ReadyAndValidImplyGrant_A	421213935	842244	0	0
ReqAndReadyImplyGrant_A	421213935	842244	0	0
ReqImpliesValid_A	421213935	2424997	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	842244	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	842244	0	0
T1	407942	56	0	0
T2	263511	736	0	0
T3	7354	290	0	0
T7	314183	34	0	0
T8	9197	89	0	0
T9	11380	68	0	0
T10	73989	875	0	0
T11	394676	53	0	0
T12	47300	531	0	0
T13	16164	937	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	842244	0	0
T1	407942	56	0	0
T2	263511	736	0	0
T3	7354	290	0	0
T7	314183	34	0	0
T8	9197	89	0	0
T9	11380	68	0	0
T10	73989	875	0	0
T11	394676	53	0	0
T12	47300	531	0	0
T13	16164	937	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	842244	0	0
T1	407942	56	0	0
T2	263511	736	0	0
T3	7354	290	0	0
T7	314183	34	0	0
T8	9197	89	0	0
T9	11380	68	0	0
T10	73989	875	0	0
T11	394676	53	0	0
T12	47300	531	0	0
T13	16164	937	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	12550977	0	0
T1	407942	17837	0	0
T2	263511	250781	0	0
T3	7354	256	0	0
T7	314183	141	0	0
T8	9197	560	0	0
T9	11380	508	0	0
T10	73989	6316	0	0
T11	394676	253	0	0
T12	47300	3966	0	0
T13	16164	703	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	842244	0	0
T1	407942	56	0	0
T2	263511	736	0	0
T3	7354	290	0	0
T7	314183	34	0	0
T8	9197	89	0	0
T9	11380	68	0	0
T10	73989	875	0	0
T11	394676	53	0	0
T12	47300	531	0	0
T13	16164	937	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	842244	0	0
T1	407942	56	0	0
T2	263511	736	0	0
T3	7354	290	0	0
T7	314183	34	0	0
T8	9197	89	0	0
T9	11380	68	0	0
T10	73989	875	0	0
T11	394676	53	0	0
T12	47300	531	0	0
T13	16164	937	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	2424997	0	0
T1	407942	1103	0	0
T2	263511	22975	0	0
T3	7354	325	0	0
T7	314183	53	0	0
T8	9197	171	0	0
T9	11380	116	0	0
T10	73989	1621	0	0
T11	394676	83	0	0
T12	47300	1043	0	0
T13	16164	1172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	842244	0	0
T1	407942	56	0	0
T2	263511	736	0	0
T3	7354	290	0	0
T7	314183	34	0	0
T8	9197	89	0	0
T9	11380	68	0	0
T10	73989	875	0	0
T11	394676	53	0	0
T12	47300	531	0	0
T13	16164	937	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	204622	0	0
GntImpliesValid_A	421213935	204622	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	204622	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3088744	0	0
ReadyAndValidImplyGrant_A	421213935	204622	0	0
ReqAndReadyImplyGrant_A	421213935	204622	0	0
ReqImpliesValid_A	421213935	534544	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	204622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204622	0	0
T1	407942	11	0	0
T2	263511	206	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	217	0	0
T11	394676	16	0	0
T12	47300	151	0	0
T13	16164	237	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204622	0	0
T1	407942	11	0	0
T2	263511	206	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	217	0	0
T11	394676	16	0	0
T12	47300	151	0	0
T13	16164	237	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204622	0	0
T1	407942	11	0	0
T2	263511	206	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	217	0	0
T11	394676	16	0	0
T12	47300	151	0	0
T13	16164	237	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3088744	0	0
T1	407942	3963	0	0
T2	263511	71891	0	0
T3	7354	70	0	0
T7	314183	58	0	0
T8	9197	88	0	0
T9	11380	64	0	0
T10	73989	1645	0	0
T11	394676	70	0	0
T12	47300	1122	0	0
T13	16164	224	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204622	0	0
T1	407942	11	0	0
T2	263511	206	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	217	0	0
T11	394676	16	0	0
T12	47300	151	0	0
T13	16164	237	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204622	0	0
T1	407942	11	0	0
T2	263511	206	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	217	0	0
T11	394676	16	0	0
T12	47300	151	0	0
T13	16164	237	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	534544	0	0
T1	407942	139	0	0
T2	263511	3828	0	0
T3	7354	71	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	291	0	0
T11	394676	16	0	0
T12	47300	199	0	0
T13	16164	251	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204622	0	0
T1	407942	11	0	0
T2	263511	206	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	13	0	0
T9	11380	7	0	0
T10	73989	217	0	0
T11	394676	16	0	0
T12	47300	151	0	0
T13	16164	237	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	220838	0	0
GntImpliesValid_A	421213935	220838	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	220838	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3203894	0	0
ReadyAndValidImplyGrant_A	421213935	220838	0	0
ReqAndReadyImplyGrant_A	421213935	220838	0	0
ReqImpliesValid_A	421213935	570798	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	220838	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	220838	0	0
T1	407942	17	0	0
T2	263511	211	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	192	0	0
T11	394676	10	0	0
T12	47300	151	0	0
T13	16164	208	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	220838	0	0
T1	407942	17	0	0
T2	263511	211	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	192	0	0
T11	394676	10	0	0
T12	47300	151	0	0
T13	16164	208	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	220838	0	0
T1	407942	17	0	0
T2	263511	211	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	192	0	0
T11	394676	10	0	0
T12	47300	151	0	0
T13	16164	208	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3203894	0	0
T1	407942	7565	0	0
T2	263511	68045	0	0
T3	7354	70	0	0
T7	314183	52	0	0
T8	9197	103	0	0
T9	11380	129	0	0
T10	73989	1413	0	0
T11	394676	46	0	0
T12	47300	1024	0	0
T13	16164	201	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	220838	0	0
T1	407942	17	0	0
T2	263511	211	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	192	0	0
T11	394676	10	0	0
T12	47300	151	0	0
T13	16164	208	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	220838	0	0
T1	407942	17	0	0
T2	263511	211	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	192	0	0
T11	394676	10	0	0
T12	47300	151	0	0
T13	16164	208	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	570798	0	0
T1	407942	649	0	0
T2	263511	4264	0	0
T3	7354	71	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	247	0	0
T11	394676	10	0	0
T12	47300	245	0	0
T13	16164	216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	220838	0	0
T1	407942	17	0	0
T2	263511	211	0	0
T3	7354	70	0	0
T7	314183	13	0	0
T8	9197	11	0	0
T9	11380	15	0	0
T10	73989	192	0	0
T11	394676	10	0	0
T12	47300	151	0	0
T13	16164	208	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	203132	0	0
GntImpliesValid_A	421213935	203132	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	203132	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	5167991	0	0
ReadyAndValidImplyGrant_A	421213935	203132	0	0
ReqAndReadyImplyGrant_A	421213935	203132	0	0
ReqImpliesValid_A	421213935	1155536	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	203132	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203132	0	0
T1	407942	4	0	0
T2	263511	194	0	0
T3	7354	96	0	0
T7	314183	15	0	0
T8	9197	19	0	0
T9	11380	17	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	133	0	0
T13	16164	199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203132	0	0
T1	407942	4	0	0
T2	263511	194	0	0
T3	7354	96	0	0
T7	314183	15	0	0
T8	9197	19	0	0
T9	11380	17	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	133	0	0
T13	16164	199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203132	0	0
T1	407942	4	0	0
T2	263511	194	0	0
T3	7354	96	0	0
T7	314183	15	0	0
T8	9197	19	0	0
T9	11380	17	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	133	0	0
T13	16164	199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	5167991	0	0
T1	407942	2682	0	0
T2	263511	14422	0	0
T3	7354	542	0	0
T7	314183	348	0	0
T8	9197	126	0	0
T9	11380	203	0	0
T10	73989	2653	0	0
T11	394676	110	0	0
T12	47300	1079	0	0
T13	16164	1778	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203132	0	0
T1	407942	4	0	0
T2	263511	194	0	0
T3	7354	96	0	0
T7	314183	15	0	0
T8	9197	19	0	0
T9	11380	17	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	133	0	0
T13	16164	199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203132	0	0
T1	407942	4	0	0
T2	263511	194	0	0
T3	7354	96	0	0
T7	314183	15	0	0
T8	9197	19	0	0
T9	11380	17	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	133	0	0
T13	16164	199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	1155536	0	0
T1	407942	4	0	0
T2	263511	564	0	0
T3	7354	168	0	0
T7	314183	23	0	0
T8	9197	19	0	0
T9	11380	18	0	0
T10	73989	322	0	0
T11	394676	14	0	0
T12	47300	178	0	0
T13	16164	418	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203132	0	0
T1	407942	4	0	0
T2	263511	194	0	0
T3	7354	96	0	0
T7	314183	15	0	0
T8	9197	19	0	0
T9	11380	17	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	133	0	0
T13	16164	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	217148	0	0
GntImpliesValid_A	421213935	217148	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	217148	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	5981706	0	0
ReadyAndValidImplyGrant_A	421213935	217148	0	0
ReqAndReadyImplyGrant_A	421213935	217148	0	0
ReqImpliesValid_A	421213935	1536918	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	217148	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217148	0	0
T1	407942	11	0	0
T2	263511	234	0	0
T3	7354	73	0	0
T7	314183	8	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	204	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	234	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217148	0	0
T1	407942	11	0	0
T2	263511	234	0	0
T3	7354	73	0	0
T7	314183	8	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	204	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	234	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217148	0	0
T1	407942	11	0	0
T2	263511	234	0	0
T3	7354	73	0	0
T7	314183	8	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	204	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	234	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	5981706	0	0
T1	407942	3359	0	0
T2	263511	48573	0	0
T3	7354	861	0	0
T7	314183	81	0	0
T8	9197	163	0	0
T9	11380	640	0	0
T10	73989	2987	0	0
T11	394676	102	0	0
T12	47300	2242	0	0
T13	16164	1879	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217148	0	0
T1	407942	11	0	0
T2	263511	234	0	0
T3	7354	73	0	0
T7	314183	8	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	204	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	234	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217148	0	0
T1	407942	11	0	0
T2	263511	234	0	0
T3	7354	73	0	0
T7	314183	8	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	204	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	234	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	1536918	0	0
T1	407942	11	0	0
T2	263511	3689	0	0
T3	7354	189	0	0
T7	314183	16	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	341	0	0
T11	394676	9	0	0
T12	47300	332	0	0
T13	16164	478	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217148	0	0
T1	407942	11	0	0
T2	263511	234	0	0
T3	7354	73	0	0
T7	314183	8	0	0
T8	9197	21	0	0
T9	11380	10	0	0
T10	73989	204	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	234	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	218467	0	0
GntImpliesValid_A	421213935	218467	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	218467	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	4821213	0	0
ReadyAndValidImplyGrant_A	421213935	218467	0	0
ReqAndReadyImplyGrant_A	421213935	218467	0	0
ReqImpliesValid_A	421213935	1140092	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	218467	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	218467	0	0
T1	407942	7	0	0
T2	263511	222	0	0
T3	7354	72	0	0
T7	314183	14	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	234	0	0
T11	394676	12	0	0
T12	47300	147	0	0
T13	16164	230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	218467	0	0
T1	407942	7	0	0
T2	263511	222	0	0
T3	7354	72	0	0
T7	314183	14	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	234	0	0
T11	394676	12	0	0
T12	47300	147	0	0
T13	16164	230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	218467	0	0
T1	407942	7	0	0
T2	263511	222	0	0
T3	7354	72	0	0
T7	314183	14	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	234	0	0
T11	394676	12	0	0
T12	47300	147	0	0
T13	16164	230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	4821213	0	0
T1	407942	2234	0	0
T2	263511	18445	0	0
T3	7354	292	0	0
T7	314183	133	0	0
T8	9197	151	0	0
T9	11380	145	0	0
T10	73989	4651	0	0
T11	394676	127	0	0
T12	47300	874	0	0
T13	16164	1480	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	218467	0	0
T1	407942	7	0	0
T2	263511	222	0	0
T3	7354	72	0	0
T7	314183	14	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	234	0	0
T11	394676	12	0	0
T12	47300	147	0	0
T13	16164	230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	218467	0	0
T1	407942	7	0	0
T2	263511	222	0	0
T3	7354	72	0	0
T7	314183	14	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	234	0	0
T11	394676	12	0	0
T12	47300	147	0	0
T13	16164	230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	1140092	0	0
T1	407942	7	0	0
T2	263511	1212	0	0
T3	7354	97	0	0
T7	314183	29	0	0
T8	9197	23	0	0
T9	11380	22	0	0
T10	73989	607	0	0
T11	394676	12	0	0
T12	47300	196	0	0
T13	16164	461	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	218467	0	0
T1	407942	7	0	0
T2	263511	222	0	0
T3	7354	72	0	0
T7	314183	14	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	234	0	0
T11	394676	12	0	0
T12	47300	147	0	0
T13	16164	230	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	209011	0	0
GntImpliesValid_A	421213935	209011	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	209011	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	4841164	0	0
ReadyAndValidImplyGrant_A	421213935	209011	0	0
ReqAndReadyImplyGrant_A	421213935	209011	0	0
ReqImpliesValid_A	421213935	1071978	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	209011	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209011	0	0
T1	407942	7	0	0
T2	263511	202	0	0
T3	7354	95	0	0
T7	314183	18	0	0
T8	9197	21	0	0
T9	11380	9	0	0
T10	73989	233	0	0
T11	394676	9	0	0
T12	47300	123	0	0
T13	16164	224	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209011	0	0
T1	407942	7	0	0
T2	263511	202	0	0
T3	7354	95	0	0
T7	314183	18	0	0
T8	9197	21	0	0
T9	11380	9	0	0
T10	73989	233	0	0
T11	394676	9	0	0
T12	47300	123	0	0
T13	16164	224	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209011	0	0
T1	407942	7	0	0
T2	263511	202	0	0
T3	7354	95	0	0
T7	314183	18	0	0
T8	9197	21	0	0
T9	11380	9	0	0
T10	73989	233	0	0
T11	394676	9	0	0
T12	47300	123	0	0
T13	16164	224	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	4841164	0	0
T1	407942	7665	0	0
T2	263511	31564	0	0
T3	7354	412	0	0
T7	314183	371	0	0
T8	9197	180	0	0
T9	11380	330	0	0
T10	73989	3355	0	0
T11	394676	158	0	0
T12	47300	2654	0	0
T13	16164	1434	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209011	0	0
T1	407942	7	0	0
T2	263511	202	0	0
T3	7354	95	0	0
T7	314183	18	0	0
T8	9197	21	0	0
T9	11380	9	0	0
T10	73989	233	0	0
T11	394676	9	0	0
T12	47300	123	0	0
T13	16164	224	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209011	0	0
T1	407942	7	0	0
T2	263511	202	0	0
T3	7354	95	0	0
T7	314183	18	0	0
T8	9197	21	0	0
T9	11380	9	0	0
T10	73989	233	0	0
T11	394676	9	0	0
T12	47300	123	0	0
T13	16164	224	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	1071978	0	0
T1	407942	636	0	0
T2	263511	713	0	0
T3	7354	130	0	0
T7	314183	74	0	0
T8	9197	21	0	0
T9	11380	43	0	0
T10	73989	530	0	0
T11	394676	45	0	0
T12	47300	250	0	0
T13	16164	417	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209011	0	0
T1	407942	7	0	0
T2	263511	202	0	0
T3	7354	95	0	0
T7	314183	18	0	0
T8	9197	21	0	0
T9	11380	9	0	0
T10	73989	233	0	0
T11	394676	9	0	0
T12	47300	123	0	0
T13	16164	224	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	204282	0	0
GntImpliesValid_A	421213935	204282	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	204282	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3163526	0	0
ReadyAndValidImplyGrant_A	421213935	204282	0	0
ReqAndReadyImplyGrant_A	421213935	204282	0	0
ReqImpliesValid_A	421213935	557691	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	204282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204282	0	0
T1	407942	11	0	0
T2	263511	214	0	0
T3	7354	81	0	0
T7	314183	14	0	0
T8	9197	50	0	0
T9	11380	7	0	0
T10	73989	234	0	0
T11	394676	10	0	0
T12	47300	124	0	0
T13	16164	250	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204282	0	0
T1	407942	11	0	0
T2	263511	214	0	0
T3	7354	81	0	0
T7	314183	14	0	0
T8	9197	50	0	0
T9	11380	7	0	0
T10	73989	234	0	0
T11	394676	10	0	0
T12	47300	124	0	0
T13	16164	250	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204282	0	0
T1	407942	11	0	0
T2	263511	214	0	0
T3	7354	81	0	0
T7	314183	14	0	0
T8	9197	50	0	0
T9	11380	7	0	0
T10	73989	234	0	0
T11	394676	10	0	0
T12	47300	124	0	0
T13	16164	250	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3163526	0	0
T1	407942	4245	0	0
T2	263511	67418	0	0
T3	7354	77	0	0
T7	314183	84	0	0
T8	9197	339	0	0
T9	11380	58	0	0
T10	73989	1760	0	0
T11	394676	40	0	0
T12	47300	1018	0	0
T13	16164	237	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204282	0	0
T1	407942	11	0	0
T2	263511	214	0	0
T3	7354	81	0	0
T7	314183	14	0	0
T8	9197	50	0	0
T9	11380	7	0	0
T10	73989	234	0	0
T11	394676	10	0	0
T12	47300	124	0	0
T13	16164	250	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204282	0	0
T1	407942	11	0	0
T2	263511	214	0	0
T3	7354	81	0	0
T7	314183	14	0	0
T8	9197	50	0	0
T9	11380	7	0	0
T10	73989	234	0	0
T11	394676	10	0	0
T12	47300	124	0	0
T13	16164	250	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	557691	0	0
T1	407942	11	0	0
T2	263511	7275	0	0
T3	7354	86	0	0
T7	314183	14	0	0
T8	9197	92	0	0
T9	11380	7	0	0
T10	73989	336	0	0
T11	394676	10	0	0
T12	47300	155	0	0
T13	16164	264	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204282	0	0
T1	407942	11	0	0
T2	263511	214	0	0
T3	7354	81	0	0
T7	314183	14	0	0
T8	9197	50	0	0
T9	11380	7	0	0
T10	73989	234	0	0
T11	394676	10	0	0
T12	47300	124	0	0
T13	16164	250	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	203162	0	0
GntImpliesValid_A	421213935	203162	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	203162	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3085832	0	0
ReadyAndValidImplyGrant_A	421213935	203162	0	0
ReqAndReadyImplyGrant_A	421213935	203162	0	0
ReqImpliesValid_A	421213935	530676	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	203162	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203162	0	0
T1	407942	13	0	0
T2	263511	206	0	0
T3	7354	74	0	0
T7	314183	13	0	0
T8	9197	19	0	0
T9	11380	11	0	0
T10	73989	235	0	0
T11	394676	14	0	0
T12	47300	134	0	0
T13	16164	259	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203162	0	0
T1	407942	13	0	0
T2	263511	206	0	0
T3	7354	74	0	0
T7	314183	13	0	0
T8	9197	19	0	0
T9	11380	11	0	0
T10	73989	235	0	0
T11	394676	14	0	0
T12	47300	134	0	0
T13	16164	259	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203162	0	0
T1	407942	13	0	0
T2	263511	206	0	0
T3	7354	74	0	0
T7	314183	13	0	0
T8	9197	19	0	0
T9	11380	11	0	0
T10	73989	235	0	0
T11	394676	14	0	0
T12	47300	134	0	0
T13	16164	259	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3085832	0	0
T1	407942	3362	0	0
T2	263511	69140	0	0
T3	7354	71	0	0
T7	314183	70	0	0
T8	9197	155	0	0
T9	11380	69	0	0
T10	73989	1638	0	0
T11	394676	73	0	0
T12	47300	1021	0	0
T13	16164	242	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203162	0	0
T1	407942	13	0	0
T2	263511	206	0	0
T3	7354	74	0	0
T7	314183	13	0	0
T8	9197	19	0	0
T9	11380	11	0	0
T10	73989	235	0	0
T11	394676	14	0	0
T12	47300	134	0	0
T13	16164	259	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203162	0	0
T1	407942	13	0	0
T2	263511	206	0	0
T3	7354	74	0	0
T7	314183	13	0	0
T8	9197	19	0	0
T9	11380	11	0	0
T10	73989	235	0	0
T11	394676	14	0	0
T12	47300	134	0	0
T13	16164	259	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	530676	0	0
T1	407942	13	0	0
T2	263511	5293	0	0
T3	7354	78	0	0
T7	314183	13	0	0
T8	9197	29	0	0
T9	11380	15	0	0
T10	73989	272	0	0
T11	394676	14	0	0
T12	47300	188	0	0
T13	16164	277	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203162	0	0
T1	407942	13	0	0
T2	263511	206	0	0
T3	7354	74	0	0
T7	314183	13	0	0
T8	9197	19	0	0
T9	11380	11	0	0
T10	73989	235	0	0
T11	394676	14	0	0
T12	47300	134	0	0
T13	16164	259	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	223326	0	0
GntImpliesValid_A	421213935	223326	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	223326	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3109134	0	0
ReadyAndValidImplyGrant_A	421213935	223326	0	0
ReqAndReadyImplyGrant_A	421213935	223326	0	0
ReqImpliesValid_A	421213935	624445	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	223326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	223326	0	0
T1	407942	6	0	0
T2	263511	209	0	0
T3	7354	65	0	0
T7	314183	13	0	0
T8	9197	6	0	0
T9	11380	7	0	0
T10	73989	221	0	0
T11	394676	15	0	0
T12	47300	108	0	0
T13	16164	237	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	223326	0	0
T1	407942	6	0	0
T2	263511	209	0	0
T3	7354	65	0	0
T7	314183	13	0	0
T8	9197	6	0	0
T9	11380	7	0	0
T10	73989	221	0	0
T11	394676	15	0	0
T12	47300	108	0	0
T13	16164	237	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	223326	0	0
T1	407942	6	0	0
T2	263511	209	0	0
T3	7354	65	0	0
T7	314183	13	0	0
T8	9197	6	0	0
T9	11380	7	0	0
T10	73989	221	0	0
T11	394676	15	0	0
T12	47300	108	0	0
T13	16164	237	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3109134	0	0
T1	407942	1607	0	0
T2	263511	63398	0	0
T3	7354	64	0	0
T7	314183	43	0	0
T8	9197	49	0	0
T9	11380	47	0	0
T10	73989	1694	0	0
T11	394676	66	0	0
T12	47300	805	0	0
T13	16164	230	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	223326	0	0
T1	407942	6	0	0
T2	263511	209	0	0
T3	7354	65	0	0
T7	314183	13	0	0
T8	9197	6	0	0
T9	11380	7	0	0
T10	73989	221	0	0
T11	394676	15	0	0
T12	47300	108	0	0
T13	16164	237	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	223326	0	0
T1	407942	6	0	0
T2	263511	209	0	0
T3	7354	65	0	0
T7	314183	13	0	0
T8	9197	6	0	0
T9	11380	7	0	0
T10	73989	221	0	0
T11	394676	15	0	0
T12	47300	108	0	0
T13	16164	237	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	624445	0	0
T1	407942	370	0	0
T2	263511	4193	0	0
T3	7354	67	0	0
T7	314183	13	0	0
T8	9197	12	0	0
T9	11380	23	0	0
T10	73989	363	0	0
T11	394676	15	0	0
T12	47300	127	0	0
T13	16164	245	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	223326	0	0
T1	407942	6	0	0
T2	263511	209	0	0
T3	7354	65	0	0
T7	314183	13	0	0
T8	9197	6	0	0
T9	11380	7	0	0
T10	73989	221	0	0
T11	394676	15	0	0
T12	47300	108	0	0
T13	16164	237	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	203884	0	0
GntImpliesValid_A	421213935	203884	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	203884	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3121766	0	0
ReadyAndValidImplyGrant_A	421213935	203884	0	0
ReqAndReadyImplyGrant_A	421213935	203884	0	0
ReqImpliesValid_A	421213935	534244	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	203884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203884	0	0
T1	407942	8	0	0
T2	263511	202	0	0
T3	7354	75	0	0
T7	314183	10	0	0
T8	9197	16	0	0
T9	11380	7	0	0
T10	73989	230	0	0
T11	394676	11	0	0
T12	47300	126	0	0
T13	16164	227	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203884	0	0
T1	407942	8	0	0
T2	263511	202	0	0
T3	7354	75	0	0
T7	314183	10	0	0
T8	9197	16	0	0
T9	11380	7	0	0
T10	73989	230	0	0
T11	394676	11	0	0
T12	47300	126	0	0
T13	16164	227	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203884	0	0
T1	407942	8	0	0
T2	263511	202	0	0
T3	7354	75	0	0
T7	314183	10	0	0
T8	9197	16	0	0
T9	11380	7	0	0
T10	73989	230	0	0
T11	394676	11	0	0
T12	47300	126	0	0
T13	16164	227	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3121766	0	0
T1	407942	1455	0	0
T2	263511	63638	0	0
T3	7354	73	0	0
T7	314183	53	0	0
T8	9197	110	0	0
T9	11380	52	0	0
T10	73989	1735	0	0
T11	394676	55	0	0
T12	47300	982	0	0
T13	16164	219	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203884	0	0
T1	407942	8	0	0
T2	263511	202	0	0
T3	7354	75	0	0
T7	314183	10	0	0
T8	9197	16	0	0
T9	11380	7	0	0
T10	73989	230	0	0
T11	394676	11	0	0
T12	47300	126	0	0
T13	16164	227	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203884	0	0
T1	407942	8	0	0
T2	263511	202	0	0
T3	7354	75	0	0
T7	314183	10	0	0
T8	9197	16	0	0
T9	11380	7	0	0
T10	73989	230	0	0
T11	394676	11	0	0
T12	47300	126	0	0
T13	16164	227	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	534244	0	0
T1	407942	8	0	0
T2	263511	3939	0	0
T3	7354	78	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	8	0	0
T10	73989	299	0	0
T11	394676	17	0	0
T12	47300	159	0	0
T13	16164	236	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203884	0	0
T1	407942	8	0	0
T2	263511	202	0	0
T3	7354	75	0	0
T7	314183	10	0	0
T8	9197	16	0	0
T9	11380	7	0	0
T10	73989	230	0	0
T11	394676	11	0	0
T12	47300	126	0	0
T13	16164	227	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	213020	0	0
GntImpliesValid_A	421213935	213020	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	213020	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3055250	0	0
ReadyAndValidImplyGrant_A	421213935	213020	0	0
ReqAndReadyImplyGrant_A	421213935	213020	0	0
ReqImpliesValid_A	421213935	561625	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	213020	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	213020	0	0
T1	407942	5	0	0
T2	263511	219	0	0
T3	7354	87	0	0
T7	314183	22	0	0
T8	9197	8	0	0
T9	11380	7	0	0
T10	73989	197	0	0
T11	394676	17	0	0
T12	47300	141	0	0
T13	16164	207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	213020	0	0
T1	407942	5	0	0
T2	263511	219	0	0
T3	7354	87	0	0
T7	314183	22	0	0
T8	9197	8	0	0
T9	11380	7	0	0
T10	73989	197	0	0
T11	394676	17	0	0
T12	47300	141	0	0
T13	16164	207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	213020	0	0
T1	407942	5	0	0
T2	263511	219	0	0
T3	7354	87	0	0
T7	314183	22	0	0
T8	9197	8	0	0
T9	11380	7	0	0
T10	73989	197	0	0
T11	394676	17	0	0
T12	47300	141	0	0
T13	16164	207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3055250	0	0
T1	407942	1136	0	0
T2	263511	70790	0	0
T3	7354	85	0	0
T7	314183	95	0	0
T8	9197	68	0	0
T9	11380	33	0	0
T10	73989	1359	0	0
T11	394676	73	0	0
T12	47300	1047	0	0
T13	16164	191	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	213020	0	0
T1	407942	5	0	0
T2	263511	219	0	0
T3	7354	87	0	0
T7	314183	22	0	0
T8	9197	8	0	0
T9	11380	7	0	0
T10	73989	197	0	0
T11	394676	17	0	0
T12	47300	141	0	0
T13	16164	207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	213020	0	0
T1	407942	5	0	0
T2	263511	219	0	0
T3	7354	87	0	0
T7	314183	22	0	0
T8	9197	8	0	0
T9	11380	7	0	0
T10	73989	197	0	0
T11	394676	17	0	0
T12	47300	141	0	0
T13	16164	207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	561625	0	0
T1	407942	5	0	0
T2	263511	3360	0	0
T3	7354	90	0	0
T7	314183	33	0	0
T8	9197	8	0	0
T9	11380	13	0	0
T10	73989	238	0	0
T11	394676	25	0	0
T12	47300	194	0	0
T13	16164	224	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	213020	0	0
T1	407942	5	0	0
T2	263511	219	0	0
T3	7354	87	0	0
T7	314183	22	0	0
T8	9197	8	0	0
T9	11380	7	0	0
T10	73989	197	0	0
T11	394676	17	0	0
T12	47300	141	0	0
T13	16164	207	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	203691	0	0
GntImpliesValid_A	421213935	203691	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	203691	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3063014	0	0
ReadyAndValidImplyGrant_A	421213935	203691	0	0
ReqAndReadyImplyGrant_A	421213935	203691	0	0
ReqImpliesValid_A	421213935	547027	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	203691	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203691	0	0
T1	407942	17	0	0
T2	263511	217	0	0
T3	7354	67	0	0
T7	314183	10	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	219	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	238	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203691	0	0
T1	407942	17	0	0
T2	263511	217	0	0
T3	7354	67	0	0
T7	314183	10	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	219	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	238	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203691	0	0
T1	407942	17	0	0
T2	263511	217	0	0
T3	7354	67	0	0
T7	314183	10	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	219	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	238	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3063014	0	0
T1	407942	5673	0	0
T2	263511	63407	0	0
T3	7354	66	0	0
T7	314183	45	0	0
T8	9197	157	0	0
T9	11380	86	0	0
T10	73989	1567	0	0
T11	394676	36	0	0
T12	47300	1038	0	0
T13	16164	234	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203691	0	0
T1	407942	17	0	0
T2	263511	217	0	0
T3	7354	67	0	0
T7	314183	10	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	219	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	238	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203691	0	0
T1	407942	17	0	0
T2	263511	217	0	0
T3	7354	67	0	0
T7	314183	10	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	219	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	238	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	547027	0	0
T1	407942	691	0	0
T2	263511	3802	0	0
T3	7354	69	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	19	0	0
T10	73989	339	0	0
T11	394676	9	0	0
T12	47300	180	0	0
T13	16164	243	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	203691	0	0
T1	407942	17	0	0
T2	263511	217	0	0
T3	7354	67	0	0
T7	314183	10	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	219	0	0
T11	394676	9	0	0
T12	47300	144	0	0
T13	16164	238	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	211105	0	0
GntImpliesValid_A	421213935	211105	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	211105	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3111157	0	0
ReadyAndValidImplyGrant_A	421213935	211105	0	0
ReqAndReadyImplyGrant_A	421213935	211105	0	0
ReqImpliesValid_A	421213935	576399	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	211105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	211105	0	0
T1	407942	10	0	0
T2	263511	199	0	0
T3	7354	87	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	15	0	0
T10	73989	219	0	0
T11	394676	10	0	0
T12	47300	137	0	0
T13	16164	265	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	211105	0	0
T1	407942	10	0	0
T2	263511	199	0	0
T3	7354	87	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	15	0	0
T10	73989	219	0	0
T11	394676	10	0	0
T12	47300	137	0	0
T13	16164	265	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	211105	0	0
T1	407942	10	0	0
T2	263511	199	0	0
T3	7354	87	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	15	0	0
T10	73989	219	0	0
T11	394676	10	0	0
T12	47300	137	0	0
T13	16164	265	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3111157	0	0
T1	407942	3434	0	0
T2	263511	64704	0	0
T3	7354	80	0	0
T7	314183	57	0	0
T8	9197	114	0	0
T9	11380	97	0	0
T10	73989	1680	0	0
T11	394676	39	0	0
T12	47300	1040	0	0
T13	16164	254	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	211105	0	0
T1	407942	10	0	0
T2	263511	199	0	0
T3	7354	87	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	15	0	0
T10	73989	219	0	0
T11	394676	10	0	0
T12	47300	137	0	0
T13	16164	265	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	211105	0	0
T1	407942	10	0	0
T2	263511	199	0	0
T3	7354	87	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	15	0	0
T10	73989	219	0	0
T11	394676	10	0	0
T12	47300	137	0	0
T13	16164	265	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	576399	0	0
T1	407942	344	0	0
T2	263511	5603	0	0
T3	7354	95	0	0
T7	314183	13	0	0
T8	9197	17	0	0
T9	11380	15	0	0
T10	73989	302	0	0
T11	394676	10	0	0
T12	47300	189	0	0
T13	16164	277	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	211105	0	0
T1	407942	10	0	0
T2	263511	199	0	0
T3	7354	87	0	0
T7	314183	13	0	0
T8	9197	16	0	0
T9	11380	15	0	0
T10	73989	219	0	0
T11	394676	10	0	0
T12	47300	137	0	0
T13	16164	265	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	217694	0	0
GntImpliesValid_A	421213935	217694	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	217694	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3137156	0	0
ReadyAndValidImplyGrant_A	421213935	217694	0	0
ReqAndReadyImplyGrant_A	421213935	217694	0	0
ReqImpliesValid_A	421213935	617034	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	217694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217694	0	0
T1	407942	12	0	0
T2	263511	193	0	0
T3	7354	64	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	220	0	0
T11	394676	14	0	0
T12	47300	127	0	0
T13	16164	219	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217694	0	0
T1	407942	12	0	0
T2	263511	193	0	0
T3	7354	64	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	220	0	0
T11	394676	14	0	0
T12	47300	127	0	0
T13	16164	219	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217694	0	0
T1	407942	12	0	0
T2	263511	193	0	0
T3	7354	64	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	220	0	0
T11	394676	14	0	0
T12	47300	127	0	0
T13	16164	219	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3137156	0	0
T1	407942	2892	0	0
T2	263511	54632	0	0
T3	7354	64	0	0
T7	314183	53	0	0
T8	9197	147	0	0
T9	11380	117	0	0
T10	73989	1737	0	0
T11	394676	50	0	0
T12	47300	988	0	0
T13	16164	205	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217694	0	0
T1	407942	12	0	0
T2	263511	193	0	0
T3	7354	64	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	220	0	0
T11	394676	14	0	0
T12	47300	127	0	0
T13	16164	219	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217694	0	0
T1	407942	12	0	0
T2	263511	193	0	0
T3	7354	64	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	220	0	0
T11	394676	14	0	0
T12	47300	127	0	0
T13	16164	219	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	617034	0	0
T1	407942	680	0	0
T2	263511	4075	0	0
T3	7354	65	0	0
T7	314183	15	0	0
T8	9197	23	0	0
T9	11380	10	0	0
T10	73989	305	0	0
T11	394676	14	0	0
T12	47300	158	0	0
T13	16164	234	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	217694	0	0
T1	407942	12	0	0
T2	263511	193	0	0
T3	7354	64	0	0
T7	314183	15	0	0
T8	9197	17	0	0
T9	11380	10	0	0
T10	73989	220	0	0
T11	394676	14	0	0
T12	47300	127	0	0
T13	16164	219	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	225563	0	0
GntImpliesValid_A	421213935	225563	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	225563	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3148653	0	0
ReadyAndValidImplyGrant_A	421213935	225563	0	0
ReqAndReadyImplyGrant_A	421213935	225563	0	0
ReqImpliesValid_A	421213935	601249	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	225563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	225563	0	0
T1	407942	9	0	0
T2	263511	224	0	0
T3	7354	153	0	0
T7	314183	12	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	252	0	0
T11	394676	16	0	0
T12	47300	112	0	0
T13	16164	242	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	225563	0	0
T1	407942	9	0	0
T2	263511	224	0	0
T3	7354	153	0	0
T7	314183	12	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	252	0	0
T11	394676	16	0	0
T12	47300	112	0	0
T13	16164	242	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	225563	0	0
T1	407942	9	0	0
T2	263511	224	0	0
T3	7354	153	0	0
T7	314183	12	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	252	0	0
T11	394676	16	0	0
T12	47300	112	0	0
T13	16164	242	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3148653	0	0
T1	407942	2197	0	0
T2	263511	77894	0	0
T3	7354	147	0	0
T7	314183	46	0	0
T8	9197	260	0	0
T9	11380	106	0	0
T10	73989	1789	0	0
T11	394676	80	0	0
T12	47300	867	0	0
T13	16164	226	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	225563	0	0
T1	407942	9	0	0
T2	263511	224	0	0
T3	7354	153	0	0
T7	314183	12	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	252	0	0
T11	394676	16	0	0
T12	47300	112	0	0
T13	16164	242	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	225563	0	0
T1	407942	9	0	0
T2	263511	224	0	0
T3	7354	153	0	0
T7	314183	12	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	252	0	0
T11	394676	16	0	0
T12	47300	112	0	0
T13	16164	242	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	601249	0	0
T1	407942	9	0	0
T2	263511	4295	0	0
T3	7354	160	0	0
T7	314183	15	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	372	0	0
T11	394676	20	0	0
T12	47300	142	0	0
T13	16164	259	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	225563	0	0
T1	407942	9	0	0
T2	263511	224	0	0
T3	7354	153	0	0
T7	314183	12	0	0
T8	9197	32	0	0
T9	11380	10	0	0
T10	73989	252	0	0
T11	394676	16	0	0
T12	47300	112	0	0
T13	16164	242	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	221894	0	0
GntImpliesValid_A	421213935	221894	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	221894	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3087873	0	0
ReadyAndValidImplyGrant_A	421213935	221894	0	0
ReqAndReadyImplyGrant_A	421213935	221894	0	0
ReqImpliesValid_A	421213935	620980	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	221894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	221894	0	0
T1	407942	12	0	0
T2	263511	215	0	0
T3	7354	85	0	0
T7	314183	15	0	0
T8	9197	78	0	0
T9	11380	8	0	0
T10	73989	207	0	0
T11	394676	7	0	0
T12	47300	130	0	0
T13	16164	240	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	221894	0	0
T1	407942	12	0	0
T2	263511	215	0	0
T3	7354	85	0	0
T7	314183	15	0	0
T8	9197	78	0	0
T9	11380	8	0	0
T10	73989	207	0	0
T11	394676	7	0	0
T12	47300	130	0	0
T13	16164	240	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	221894	0	0
T1	407942	12	0	0
T2	263511	215	0	0
T3	7354	85	0	0
T7	314183	15	0	0
T8	9197	78	0	0
T9	11380	8	0	0
T10	73989	207	0	0
T11	394676	7	0	0
T12	47300	130	0	0
T13	16164	240	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3087873	0	0
T1	407942	4119	0	0
T2	263511	66269	0	0
T3	7354	81	0	0
T7	314183	78	0	0
T8	9197	415	0	0
T9	11380	63	0	0
T10	73989	1573	0	0
T11	394676	32	0	0
T12	47300	808	0	0
T13	16164	228	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	221894	0	0
T1	407942	12	0	0
T2	263511	215	0	0
T3	7354	85	0	0
T7	314183	15	0	0
T8	9197	78	0	0
T9	11380	8	0	0
T10	73989	207	0	0
T11	394676	7	0	0
T12	47300	130	0	0
T13	16164	240	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	221894	0	0
T1	407942	12	0	0
T2	263511	215	0	0
T3	7354	85	0	0
T7	314183	15	0	0
T8	9197	78	0	0
T9	11380	8	0	0
T10	73989	207	0	0
T11	394676	7	0	0
T12	47300	130	0	0
T13	16164	240	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	620980	0	0
T1	407942	12	0	0
T2	263511	5268	0	0
T3	7354	90	0	0
T7	314183	15	0	0
T8	9197	217	0	0
T9	11380	9	0	0
T10	73989	293	0	0
T11	394676	7	0	0
T12	47300	173	0	0
T13	16164	253	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	221894	0	0
T1	407942	12	0	0
T2	263511	215	0	0
T3	7354	85	0	0
T7	314183	15	0	0
T8	9197	78	0	0
T9	11380	8	0	0
T10	73989	207	0	0
T11	394676	7	0	0
T12	47300	130	0	0
T13	16164	240	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	208001	0	0
GntImpliesValid_A	421213935	208001	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	208001	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3135798	0	0
ReadyAndValidImplyGrant_A	421213935	208001	0	0
ReqAndReadyImplyGrant_A	421213935	208001	0	0
ReqImpliesValid_A	421213935	557056	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	208001	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	208001	0	0
T1	407942	14	0	0
T2	263511	205	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	202	0	0
T11	394676	15	0	0
T12	47300	133	0	0
T13	16164	207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	208001	0	0
T1	407942	14	0	0
T2	263511	205	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	202	0	0
T11	394676	15	0	0
T12	47300	133	0	0
T13	16164	207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	208001	0	0
T1	407942	14	0	0
T2	263511	205	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	202	0	0
T11	394676	15	0	0
T12	47300	133	0	0
T13	16164	207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3135798	0	0
T1	407942	3531	0	0
T2	263511	71295	0	0
T3	7354	69	0	0
T7	314183	74	0	0
T8	9197	171	0	0
T9	11380	94	0	0
T10	73989	1531	0	0
T11	394676	69	0	0
T12	47300	991	0	0
T13	16164	189	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	208001	0	0
T1	407942	14	0	0
T2	263511	205	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	202	0	0
T11	394676	15	0	0
T12	47300	133	0	0
T13	16164	207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	208001	0	0
T1	407942	14	0	0
T2	263511	205	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	202	0	0
T11	394676	15	0	0
T12	47300	133	0	0
T13	16164	207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	557056	0	0
T1	407942	1066	0	0
T2	263511	1247	0	0
T3	7354	78	0	0
T7	314183	18	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	284	0	0
T11	394676	18	0	0
T12	47300	165	0	0
T13	16164	226	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	208001	0	0
T1	407942	14	0	0
T2	263511	205	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	18	0	0
T9	11380	13	0	0
T10	73989	202	0	0
T11	394676	15	0	0
T12	47300	133	0	0
T13	16164	207	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	209610	0	0
GntImpliesValid_A	421213935	209610	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	209610	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3111723	0	0
ReadyAndValidImplyGrant_A	421213935	209610	0	0
ReqAndReadyImplyGrant_A	421213935	209610	0	0
ReqImpliesValid_A	421213935	567199	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	209610	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209610	0	0
T1	407942	11	0	0
T2	263511	204	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	220	0	0
T11	394676	8	0	0
T12	47300	155	0	0
T13	16164	232	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209610	0	0
T1	407942	11	0	0
T2	263511	204	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	220	0	0
T11	394676	8	0	0
T12	47300	155	0	0
T13	16164	232	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209610	0	0
T1	407942	11	0	0
T2	263511	204	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	220	0	0
T11	394676	8	0	0
T12	47300	155	0	0
T13	16164	232	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3111723	0	0
T1	407942	4430	0	0
T2	263511	65409	0	0
T3	7354	72	0	0
T7	314183	55	0	0
T8	9197	187	0	0
T9	11380	43	0	0
T10	73989	1708	0	0
T11	394676	30	0	0
T12	47300	1177	0	0
T13	16164	225	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209610	0	0
T1	407942	11	0	0
T2	263511	204	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	220	0	0
T11	394676	8	0	0
T12	47300	155	0	0
T13	16164	232	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209610	0	0
T1	407942	11	0	0
T2	263511	204	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	220	0	0
T11	394676	8	0	0
T12	47300	155	0	0
T13	16164	232	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	567199	0	0
T1	407942	239	0	0
T2	263511	2807	0	0
T3	7354	75	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	262	0	0
T11	394676	8	0	0
T12	47300	222	0	0
T13	16164	240	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	209610	0	0
T1	407942	11	0	0
T2	263511	204	0	0
T3	7354	73	0	0
T7	314183	13	0	0
T8	9197	22	0	0
T9	11380	5	0	0
T10	73989	220	0	0
T11	394676	8	0	0
T12	47300	155	0	0
T13	16164	232	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	215436	0	0
GntImpliesValid_A	421213935	215436	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	215436	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3119043	0	0
ReadyAndValidImplyGrant_A	421213935	215436	0	0
ReqAndReadyImplyGrant_A	421213935	215436	0	0
ReqImpliesValid_A	421213935	561264	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	215436	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	215436	0	0
T1	407942	1	0	0
T2	263511	209	0	0
T3	7354	70	0	0
T7	314183	11	0	0
T8	9197	24	0	0
T9	11380	10	0	0
T10	73989	221	0	0
T11	394676	18	0	0
T12	47300	121	0	0
T13	16164	243	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	215436	0	0
T1	407942	1	0	0
T2	263511	209	0	0
T3	7354	70	0	0
T7	314183	11	0	0
T8	9197	24	0	0
T9	11380	10	0	0
T10	73989	221	0	0
T11	394676	18	0	0
T12	47300	121	0	0
T13	16164	243	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	215436	0	0
T1	407942	1	0	0
T2	263511	209	0	0
T3	7354	70	0	0
T7	314183	11	0	0
T8	9197	24	0	0
T9	11380	10	0	0
T10	73989	221	0	0
T11	394676	18	0	0
T12	47300	121	0	0
T13	16164	243	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3119043	0	0
T1	407942	732	0	0
T2	263511	69904	0	0
T3	7354	69	0	0
T7	314183	35	0	0
T8	9197	163	0	0
T9	11380	98	0	0
T10	73989	1577	0	0
T11	394676	57	0	0
T12	47300	856	0	0
T13	16164	234	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	215436	0	0
T1	407942	1	0	0
T2	263511	209	0	0
T3	7354	70	0	0
T7	314183	11	0	0
T8	9197	24	0	0
T9	11380	10	0	0
T10	73989	221	0	0
T11	394676	18	0	0
T12	47300	121	0	0
T13	16164	243	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	215436	0	0
T1	407942	1	0	0
T2	263511	209	0	0
T3	7354	70	0	0
T7	314183	11	0	0
T8	9197	24	0	0
T9	11380	10	0	0
T10	73989	221	0	0
T11	394676	18	0	0
T12	47300	121	0	0
T13	16164	243	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	561264	0	0
T1	407942	1	0	0
T2	263511	1707	0	0
T3	7354	72	0	0
T7	314183	11	0	0
T8	9197	26	0	0
T9	11380	10	0	0
T10	73989	322	0	0
T11	394676	18	0	0
T12	47300	171	0	0
T13	16164	253	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	215436	0	0
T1	407942	1	0	0
T2	263511	209	0	0
T3	7354	70	0	0
T7	314183	11	0	0
T8	9197	24	0	0
T9	11380	10	0	0
T10	73989	221	0	0
T11	394676	18	0	0
T12	47300	121	0	0
T13	16164	243	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	204227	0	0
GntImpliesValid_A	421213935	204227	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	204227	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	3029828	0	0
ReadyAndValidImplyGrant_A	421213935	204227	0	0
ReqAndReadyImplyGrant_A	421213935	204227	0	0
ReqImpliesValid_A	421213935	545535	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	0	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	204227	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204227	0	0
T1	407942	7	0	0
T2	263511	232	0	0
T3	7354	69	0	0
T7	314183	11	0	0
T8	9197	15	0	0
T9	11380	10	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	148	0	0
T13	16164	232	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204227	0	0
T1	407942	7	0	0
T2	263511	232	0	0
T3	7354	69	0	0
T7	314183	11	0	0
T8	9197	15	0	0
T9	11380	10	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	148	0	0
T13	16164	232	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204227	0	0
T1	407942	7	0	0
T2	263511	232	0	0
T3	7354	69	0	0
T7	314183	11	0	0
T8	9197	15	0	0
T9	11380	10	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	148	0	0
T13	16164	232	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	3029828	0	0
T1	407942	1537	0	0
T2	263511	72183	0	0
T3	7354	65	0	0
T7	314183	57	0	0
T8	9197	113	0	0
T9	11380	50	0	0
T10	73989	1484	0	0
T11	394676	50	0	0
T12	47300	1098	0	0
T13	16164	223	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204227	0	0
T1	407942	7	0	0
T2	263511	232	0	0
T3	7354	69	0	0
T7	314183	11	0	0
T8	9197	15	0	0
T9	11380	10	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	148	0	0
T13	16164	232	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204227	0	0
T1	407942	7	0	0
T2	263511	232	0	0
T3	7354	69	0	0
T7	314183	11	0	0
T8	9197	15	0	0
T9	11380	10	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	148	0	0
T13	16164	232	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	545535	0	0
T1	407942	7	0	0
T2	263511	5080	0	0
T3	7354	74	0	0
T7	314183	12	0	0
T8	9197	24	0	0
T9	11380	15	0	0
T10	73989	276	0	0
T11	394676	8	0	0
T12	47300	204	0	0
T13	16164	242	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	204227	0	0
T1	407942	7	0	0
T2	263511	232	0	0
T3	7354	69	0	0
T7	314183	11	0	0
T8	9197	15	0	0
T9	11380	10	0	0
T10	73989	198	0	0
T11	394676	8	0	0
T12	47300	148	0	0
T13	16164	232	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	845580	0	0
GntImpliesValid_A	421213935	845580	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	845580	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	11777816	0	0
ReadyAndValidImplyGrant_A	421213935	845580	0	0
ReqAndReadyImplyGrant_A	421213935	845580	0	0
ReqImpliesValid_A	421213935	2315278	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	14461	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	845580	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	845580	0	0
T1	407942	54	0	0
T2	263511	792	0	0
T3	7354	329	0	0
T7	314183	46	0	0
T8	9197	100	0	0
T9	11380	66	0	0
T10	73989	920	0	0
T11	394676	60	0	0
T12	47300	574	0	0
T13	16164	982	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	845580	0	0
T1	407942	54	0	0
T2	263511	792	0	0
T3	7354	329	0	0
T7	314183	46	0	0
T8	9197	100	0	0
T9	11380	66	0	0
T10	73989	920	0	0
T11	394676	60	0	0
T12	47300	574	0	0
T13	16164	982	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	845580	0	0
T1	407942	54	0	0
T2	263511	792	0	0
T3	7354	329	0	0
T7	314183	46	0	0
T8	9197	100	0	0
T9	11380	66	0	0
T10	73989	920	0	0
T11	394676	60	0	0
T12	47300	574	0	0
T13	16164	982	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	11777816	0	0
T1	407942	17120	0	0
T2	263511	256104	0	0
T3	7354	1	0	0
T7	314183	131	0	0
T8	9197	650	0	0
T9	11380	411	0	0
T10	73989	5955	0	0
T11	394676	200	0	0
T12	47300	3751	0	0
T13	16164	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	845580	0	0
T1	407942	54	0	0
T2	263511	792	0	0
T3	7354	329	0	0
T7	314183	46	0	0
T8	9197	100	0	0
T9	11380	66	0	0
T10	73989	920	0	0
T11	394676	60	0	0
T12	47300	574	0	0
T13	16164	982	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	845580	0	0
T1	407942	54	0	0
T2	263511	792	0	0
T3	7354	329	0	0
T7	314183	46	0	0
T8	9197	100	0	0
T9	11380	66	0	0
T10	73989	920	0	0
T11	394676	60	0	0
T12	47300	574	0	0
T13	16164	982	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	2315278	0	0
T1	407942	2173	0	0
T2	263511	30761	0	0
T3	7354	329	0	0
T7	314183	56	0	0
T8	9197	124	0	0
T9	11380	85	0	0
T10	73989	1567	0	0
T11	394676	74	0	0
T12	47300	984	0	0
T13	16164	982	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	14461	0	900
T3	7354	3	0	1
T6	0	10	0	0
T7	314183	0	0	1
T8	9197	0	0	1
T9	11380	0	0	1
T10	73989	2	0	1
T11	394676	0	0	1
T12	47300	0	0	1
T13	16164	13	0	1
T15	0	6	0	0
T18	0	66	0	0
T19	0	10	0	0
T20	0	1	0	0
T21	0	626	0	0
T22	0	6	0	0
T23	544783	0	0	1
T24	128564	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	845580	0	0
T1	407942	54	0	0
T2	263511	792	0	0
T3	7354	329	0	0
T7	314183	46	0	0
T8	9197	100	0	0
T9	11380	66	0	0
T10	73989	920	0	0
T11	394676	60	0	0
T12	47300	574	0	0
T13	16164	982	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421213935	421089918	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421213935	836175	0	0
GntImpliesValid_A	421213935	836175	0	0
GrantKnown_A	421213935	421089918	0	0
IdxKnown_A	421213935	421089918	0	0
IndexIsCorrect_A	421213935	836175	0	0
LockArbDecision_A	421213935	0	0	0
NoReadyValidNoGrant_A	421213935	353839401	0	0
ReadyAndValidImplyGrant_A	421213935	836175	0	0
ReqAndReadyImplyGrant_A	421213935	836175	0	0
ReqImpliesValid_A	421213935	13646524	0	0
ReqStaysHighUntilGranted0_M	421213935	0	0	0
RoundRobin_A	421213935	21612	0	900
ValidKnown_A	421213935	421089918	0	0
gen_data_port_assertion.DataFlow_A	421213935	836175	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	836175	0	0
T1	407942	55	0	0
T2	263511	762	0	0
T3	7354	317	0	0
T7	314183	40	0	0
T8	9197	86	0	0
T9	11380	57	0	0
T10	73989	853	0	0
T11	394676	66	0	0
T12	47300	514	0	0
T13	16164	909	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	836175	0	0
T1	407942	55	0	0
T2	263511	762	0	0
T3	7354	317	0	0
T7	314183	40	0	0
T8	9197	86	0	0
T9	11380	57	0	0
T10	73989	853	0	0
T11	394676	66	0	0
T12	47300	514	0	0
T13	16164	909	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	836175	0	0
T1	407942	55	0	0
T2	263511	762	0	0
T3	7354	317	0	0
T7	314183	40	0	0
T8	9197	86	0	0
T9	11380	57	0	0
T10	73989	853	0	0
T11	394676	66	0	0
T12	47300	514	0	0
T13	16164	909	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	353839401	0	0
T1	407942	387226	0	0
T2	263511	235397	0	0
T3	7354	1	0	0
T7	314183	261680	0	0
T8	9197	7325	0	0
T9	11380	9776	0	0
T10	73989	59210	0	0
T11	394676	328537	0	0
T12	47300	38158	0	0
T13	16164	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	836175	0	0
T1	407942	55	0	0
T2	263511	762	0	0
T3	7354	317	0	0
T7	314183	40	0	0
T8	9197	86	0	0
T9	11380	57	0	0
T10	73989	853	0	0
T11	394676	66	0	0
T12	47300	514	0	0
T13	16164	909	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	836175	0	0
T1	407942	55	0	0
T2	263511	762	0	0
T3	7354	317	0	0
T7	314183	40	0	0
T8	9197	86	0	0
T9	11380	57	0	0
T10	73989	853	0	0
T11	394676	66	0	0
T12	47300	514	0	0
T13	16164	909	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	13646524	0	0
T1	407942	19946	0	0
T2	263511	276621	0	0
T3	7354	317	0	0
T7	314183	153	0	0
T8	9197	591	0	0
T9	11380	463	0	0
T10	73989	6405	0	0
T11	394676	289	0	0
T12	47300	3786	0	0
T13	16164	909	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	21612	0	900
T3	7354	6	0	1
T6	0	8	0	0
T7	314183	0	0	1
T8	9197	0	0	1
T9	11380	0	0	1
T10	73989	2	0	1
T11	394676	0	0	1
T12	47300	0	0	1
T13	16164	17	0	1
T14	0	2	0	0
T15	0	6	0	0
T16	0	1	0	0
T17	0	7	0	0
T19	0	10	0	0
T21	0	472	0	0
T23	544783	0	0	1
T24	128564	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	421089918	0	0
T1	407942	407910	0	0
T2	263511	263509	0	0
T3	7354	7330	0	0
T7	314183	314120	0	0
T8	9197	8889	0	0
T9	11380	11332	0	0
T10	73989	73946	0	0
T11	394676	394634	0	0
T12	47300	47283	0	0
T13	16164	16107	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421213935	836175	0	0
T1	407942	55	0	0
T2	263511	762	0	0
T3	7354	317	0	0
T7	314183	40	0	0
T8	9197	86	0	0
T9	11380	57	0	0
T10	73989	853	0	0
T11	394676	66	0	0
T12	47300	514	0	0
T13	16164	909	0	0