Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sm1_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.51 98.68 85.92 92.73 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 92.21 97.50 82.14 89.19 100.00



Module Instance : tb.dut.u_sm1_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_40

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_42

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_43

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_44

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_45

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_46

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_47

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_48

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_49

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_50

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_51

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_52

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_53

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_54

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_55

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_56

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.78 100.00 98.39 100.00 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
SCORELINE
95.96 100.00
tb.dut.u_sm1_28

SCORELINE
95.96 100.00
tb.dut.u_sm1_29

SCORELINE
100.00 100.00
tb.dut.u_sm1_30

SCORELINE
95.96 100.00
tb.dut.u_sm1_31

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
SCORELINE
96.97 100.00
tb.dut.u_sm1_33

SCORELINE
96.97 100.00
tb.dut.u_sm1_34

SCORELINE
96.97 100.00
tb.dut.u_sm1_36

SCORELINE
96.97 100.00
tb.dut.u_sm1_38

SCORELINE
96.97 100.00
tb.dut.u_sm1_40

SCORELINE
96.97 100.00
tb.dut.u_sm1_42

SCORELINE
96.97 100.00
tb.dut.u_sm1_43

SCORELINE
96.97 100.00
tb.dut.u_sm1_44

SCORELINE
96.97 100.00
tb.dut.u_sm1_45

SCORELINE
96.97 100.00
tb.dut.u_sm1_46

SCORELINE
96.97 100.00
tb.dut.u_sm1_47

SCORELINE
96.97 100.00
tb.dut.u_sm1_48

SCORELINE
96.97 100.00
tb.dut.u_sm1_49

SCORELINE
96.97 100.00
tb.dut.u_sm1_50

SCORELINE
96.97 100.00
tb.dut.u_sm1_51

SCORELINE
96.97 100.00
tb.dut.u_sm1_52

SCORELINE
96.97 100.00
tb.dut.u_sm1_53

SCORELINE
96.97 100.00
tb.dut.u_sm1_54

SCORELINE
96.97 100.00
tb.dut.u_sm1_55

SCORELINE
96.97 100.00
tb.dut.u_sm1_56

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
SCORECOND
95.96 87.88
tb.dut.u_sm1_28

SCORECOND
95.96 87.88
tb.dut.u_sm1_29

SCORECOND
95.96 87.88
tb.dut.u_sm1_31

SCORECOND
100.00 100.00
tb.dut.u_sm1_30

TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T13,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T13,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT2,T13,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT2,T13,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
SCORECOND
96.97 90.91
tb.dut.u_sm1_33

SCORECOND
96.97 90.91
tb.dut.u_sm1_34

SCORECOND
96.97 90.91
tb.dut.u_sm1_43

SCORECOND
96.97 90.91
tb.dut.u_sm1_44

SCORECOND
96.97 90.91
tb.dut.u_sm1_45

SCORECOND
96.97 90.91
tb.dut.u_sm1_46

SCORECOND
96.97 90.91
tb.dut.u_sm1_47

SCORECOND
96.97 90.91
tb.dut.u_sm1_48

SCORECOND
96.97 90.91
tb.dut.u_sm1_49

SCORECOND
96.97 90.91
tb.dut.u_sm1_50

SCORECOND
96.97 90.91
tb.dut.u_sm1_51

SCORECOND
96.97 90.91
tb.dut.u_sm1_52

SCORECOND
96.97 90.91
tb.dut.u_sm1_53

SCORECOND
96.97 90.91
tb.dut.u_sm1_54

SCORECOND
96.97 90.91
tb.dut.u_sm1_55

SCORECOND
96.97 90.91
tb.dut.u_sm1_56

SCORECOND
96.97 90.91
tb.dut.u_sm1_36

SCORECOND
96.97 90.91
tb.dut.u_sm1_38

SCORECOND
96.97 90.91
tb.dut.u_sm1_40

SCORECOND
96.97 90.91
tb.dut.u_sm1_42

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Module : tlul_socket_m1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 2147483647 21212431 0 0
gen_host_fifo[1].idInRange 2147483647 12030677 0 0
gen_host_fifo[2].idInRange 1625105672 3236479 0 0
maxM 21600 21600 0 0
rspIdInRange 2147483647 159906736 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 21212431 0 0
T1 247272 825 0 0
T2 1638264 28953 0 0
T3 1017888 20947 0 0
T7 1271664 7082 0 0
T8 5964456 58735 0 0
T9 579120 12227 0 0
T10 49104 342 0 0
T11 150192 1534 0 0
T12 3481560 85088 0 0
T13 130248 1552 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 12030677 0 0
T1 247272 203 0 0
T2 1638264 15689 0 0
T3 1017888 11020 0 0
T7 1271664 3326 0 0
T8 5964456 47171 0 0
T9 579120 6383 0 0
T10 49104 192 0 0
T11 150192 740 0 0
T12 3481560 54860 0 0
T13 130248 902 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 1625105672 3236479 0 0
T1 41212 55 0 0
T2 273044 1878 0 0
T3 169648 1667 0 0
T7 211944 1059 0 0
T8 994076 18931 0 0
T9 96520 1059 0 0
T10 8184 33 0 0
T11 25032 130 0 0
T12 580260 8324 0 0
T13 21708 138 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 21600 21600 0 0
T1 24 24 0 0
T2 24 24 0 0
T3 24 24 0 0
T7 24 24 0 0
T8 24 24 0 0
T9 24 24 0 0
T10 24 24 0 0
T11 24 24 0 0
T12 24 24 0 0
T13 24 24 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 159906736 0 0
T1 247272 1803 0 0
T2 1638264 38646 0 0
T3 1017888 29085 0 0
T7 1271664 27869 0 0
T8 5964456 89303 0 0
T9 579120 16202 0 0
T10 49104 514 0 0
T11 150192 2092 0 0
T12 3481560 79167 0 0
T13 130248 2376 0 0

Line Coverage for Instance : tb.dut.u_sm1_28
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_28
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 1520017 0 0
gen_host_fifo[1].idInRange 406276418 342707 0 0
gen_host_fifo[2].idInRange 406276418 438385 0 0
maxM 900 900 0 0
rspIdInRange 406276418 18805911 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 1520017 0 0
T1 10303 77 0 0
T2 68261 3239 0 0
T3 42412 2806 0 0
T7 52986 766 0 0
T8 248519 6213 0 0
T9 24130 1407 0 0
T10 2046 42 0 0
T11 6258 198 0 0
T12 145065 6693 0 0
T13 5427 195 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 342707 0 0
T1 10303 4 0 0
T2 68261 420 0 0
T3 42412 528 0 0
T7 52986 161 0 0
T8 248519 3427 0 0
T9 24130 195 0 0
T10 2046 10 0 0
T11 6258 33 0 0
T12 145065 1357 0 0
T13 5427 36 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 438385 0 0
T1 10303 17 0 0
T2 68261 372 0 0
T3 42412 591 0 0
T7 52986 114 0 0
T8 248519 5108 0 0
T9 24130 191 0 0
T10 2046 8 0 0
T11 6258 33 0 0
T12 145065 1199 0 0
T13 5427 32 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 18805911 0 0
T1 10303 309 0 0
T2 68261 3996 0 0
T3 42412 3677 0 0
T7 52986 4108 0 0
T8 248519 17615 0 0
T9 24130 1760 0 0
T10 2046 60 0 0
T11 6258 261 0 0
T12 145065 8345 0 0
T13 5427 261 0 0

Line Coverage for Instance : tb.dut.u_sm1_29
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_29
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 1675982 0 0
gen_host_fifo[1].idInRange 406276418 429105 0 0
gen_host_fifo[2].idInRange 406276418 515813 0 0
maxM 900 900 0 0
rspIdInRange 406276418 18326990 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 1675982 0 0
T1 10303 60 0 0
T2 68261 3790 0 0
T3 42412 3075 0 0
T7 52986 693 0 0
T8 248519 4738 0 0
T9 24130 1816 0 0
T10 2046 70 0 0
T11 6258 227 0 0
T12 145065 12057 0 0
T13 5427 222 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 429105 0 0
T1 10303 11 0 0
T2 68261 444 0 0
T3 42412 404 0 0
T7 52986 85 0 0
T8 248519 1745 0 0
T9 24130 235 0 0
T10 2046 10 0 0
T11 6258 25 0 0
T12 145065 4531 0 0
T13 5427 33 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 515813 0 0
T1 10303 3 0 0
T2 68261 464 0 0
T3 42412 395 0 0
T7 52986 133 0 0
T8 248519 3187 0 0
T9 24130 220 0 0
T10 2046 9 0 0
T11 6258 27 0 0
T12 145065 3919 0 0
T13 5427 32 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 18326990 0 0
T1 10303 273 0 0
T2 68261 3889 0 0
T3 42412 3080 0 0
T7 52986 3289 0 0
T8 248519 14643 0 0
T9 24130 1836 0 0
T10 2046 68 0 0
T11 6258 229 0 0
T12 145065 10749 0 0
T13 5427 253 0 0

Line Coverage for Instance : tb.dut.u_sm1_31
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_31
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 1755777 0 0
gen_host_fifo[1].idInRange 406276418 465546 0 0
gen_host_fifo[2].idInRange 406276418 571994 0 0
maxM 900 900 0 0
rspIdInRange 406276418 18087612 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 1755777 0 0
T1 10303 83 0 0
T2 68261 3872 0 0
T3 42412 2996 0 0
T7 52986 642 0 0
T8 248519 2827 0 0
T9 24130 1764 0 0
T10 2046 38 0 0
T11 6258 231 0 0
T12 145065 9158 0 0
T13 5427 232 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 465546 0 0
T1 10303 7 0 0
T2 68261 458 0 0
T3 42412 345 0 0
T7 52986 95 0 0
T8 248519 303 0 0
T9 24130 214 0 0
T10 2046 3 0 0
T11 6258 32 0 0
T12 145065 2006 0 0
T13 5427 51 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 571994 0 0
T1 10303 5 0 0
T2 68261 406 0 0
T3 42412 375 0 0
T7 52986 152 0 0
T8 248519 352 0 0
T9 24130 231 0 0
T10 2046 10 0 0
T11 6258 34 0 0
T12 145065 1838 0 0
T13 5427 37 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 18087612 0 0
T1 10303 343 0 0
T2 68261 3924 0 0
T3 42412 2963 0 0
T7 52986 3428 0 0
T8 248519 12192 0 0
T9 24130 1802 0 0
T10 2046 45 0 0
T11 6258 254 0 0
T12 145065 8049 0 0
T13 5427 272 0 0

Line Coverage for Instance : tb.dut.u_sm1_33
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_33
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 307294 0 0
gen_host_fifo[1].idInRange 406276418 403797 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4469584 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 307294 0 0
T1 10303 7 0 0
T2 68261 395 0 0
T3 42412 335 0 0
T7 52986 97 0 0
T8 248519 168 0 0
T9 24130 202 0 0
T10 2046 8 0 0
T11 6258 42 0 0
T12 145065 2100 0 0
T13 5427 39 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 403797 0 0
T1 10303 5 0 0
T2 68261 405 0 0
T3 42412 355 0 0
T7 52986 80 0 0
T8 248519 183 0 0
T9 24130 231 0 0
T10 2046 7 0 0
T11 6258 31 0 0
T12 145065 1951 0 0
T13 5427 32 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4469584 0 0
T1 10303 15 0 0
T2 68261 779 0 0
T3 42412 665 0 0
T7 52986 601 0 0
T8 248519 569 0 0
T9 24130 412 0 0
T10 2046 14 0 0
T11 6258 69 0 0
T12 145065 2599 0 0
T13 5427 69 0 0

Line Coverage for Instance : tb.dut.u_sm1_34
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_34
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 280005 0 0
gen_host_fifo[1].idInRange 406276418 359878 0 0
maxM 900 900 0 0
rspIdInRange 406276418 3957728 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 280005 0 0
T1 10303 7 0 0
T2 68261 758 0 0
T3 42412 617 0 0
T7 52986 106 0 0
T8 248519 173 0 0
T9 24130 195 0 0
T10 2046 12 0 0
T11 6258 28 0 0
T12 145065 1902 0 0
T13 5427 31 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 359878 0 0
T1 10303 5 0 0
T2 68261 697 0 0
T3 42412 692 0 0
T7 52986 100 0 0
T8 248519 171 0 0
T9 24130 214 0 0
T10 2046 8 0 0
T11 6258 30 0 0
T12 145065 1587 0 0
T13 5427 32 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 3957728 0 0
T1 10303 22 0 0
T2 68261 1278 0 0
T3 42412 1112 0 0
T7 52986 654 0 0
T8 248519 495 0 0
T9 24130 392 0 0
T10 2046 20 0 0
T11 6258 58 0 0
T12 145065 2149 0 0
T13 5427 61 0 0

Line Coverage for Instance : tb.dut.u_sm1_36
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_36
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T8,T18
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 676742 0 0
gen_host_fifo[1].idInRange 406276418 802937 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4456849 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 676742 0 0
T1 10303 9 0 0
T2 68261 559 0 0
T3 42412 410 0 0
T7 52986 120 0 0
T8 248519 176 0 0
T9 24130 438 0 0
T10 2046 14 0 0
T11 6258 78 0 0
T12 145065 3470 0 0
T13 5427 39 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 802937 0 0
T1 10303 9 0 0
T2 68261 541 0 0
T3 42412 431 0 0
T7 52986 167 0 0
T8 248519 177 0 0
T9 24130 424 0 0
T10 2046 12 0 0
T11 6258 33 0 0
T12 145065 3496 0 0
T13 5427 46 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4456849 0 0
T1 10303 59 0 0
T2 68261 858 0 0
T3 42412 673 0 0
T7 52986 665 0 0
T8 248519 688 0 0
T9 24130 557 0 0
T10 2046 19 0 0
T11 6258 63 0 0
T12 145065 2026 0 0
T13 5427 64 0 0

Line Coverage for Instance : tb.dut.u_sm1_38
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_38
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 719310 0 0
gen_host_fifo[1].idInRange 406276418 822756 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4612832 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 719310 0 0
T1 10303 21 0 0
T2 68261 1474 0 0
T3 42412 418 0 0
T7 52986 66 0 0
T8 248519 152 0 0
T9 24130 286 0 0
T10 2046 6 0 0
T11 6258 32 0 0
T12 145065 7476 0 0
T13 5427 51 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 822756 0 0
T1 10303 10 0 0
T2 68261 1454 0 0
T3 42412 405 0 0
T7 52986 191 0 0
T8 248519 147 0 0
T9 24130 254 0 0
T10 2046 6 0 0
T11 6258 34 0 0
T12 145065 6311 0 0
T13 5427 54 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4612832 0 0
T1 10303 20 0 0
T2 68261 1316 0 0
T3 42412 651 0 0
T7 52986 543 0 0
T8 248519 579 0 0
T9 24130 432 0 0
T10 2046 12 0 0
T11 6258 49 0 0
T12 145065 2556 0 0
T13 5427 71 0 0

Line Coverage for Instance : tb.dut.u_sm1_40
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_40
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 601949 0 0
gen_host_fifo[1].idInRange 406276418 727651 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4318822 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 601949 0 0
T1 10303 9 0 0
T2 68261 566 0 0
T3 42412 374 0 0
T7 52986 98 0 0
T8 248519 1967 0 0
T9 24130 1052 0 0
T10 2046 19 0 0
T11 6258 99 0 0
T12 145065 6994 0 0
T13 5427 40 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 727651 0 0
T1 10303 2 0 0
T2 68261 531 0 0
T3 42412 404 0 0
T7 52986 118 0 0
T8 248519 2370 0 0
T9 24130 943 0 0
T10 2046 7 0 0
T11 6258 57 0 0
T12 145065 7040 0 0
T13 5427 25 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4318822 0 0
T1 10303 16 0 0
T2 68261 838 0 0
T3 42412 633 0 0
T7 52986 617 0 0
T8 248519 1895 0 0
T9 24130 511 0 0
T10 2046 18 0 0
T11 6258 59 0 0
T12 145065 2950 0 0
T13 5427 49 0 0

Line Coverage for Instance : tb.dut.u_sm1_42
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_42
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 727279 0 0
gen_host_fifo[1].idInRange 406276418 872297 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4077460 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 727279 0 0
T1 10303 11 0 0
T2 68261 1301 0 0
T3 42412 925 0 0
T7 52986 76 0 0
T8 248519 167 0 0
T9 24130 294 0 0
T10 2046 4 0 0
T11 6258 22 0 0
T12 145065 5575 0 0
T13 5427 33 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 872297 0 0
T1 10303 1 0 0
T2 68261 1408 0 0
T3 42412 895 0 0
T7 52986 94 0 0
T8 248519 163 0 0
T9 24130 259 0 0
T10 2046 8 0 0
T11 6258 49 0 0
T12 145065 5185 0 0
T13 5427 44 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4077460 0 0
T1 10303 74 0 0
T2 68261 1366 0 0
T3 42412 1033 0 0
T7 52986 590 0 0
T8 248519 522 0 0
T9 24130 401 0 0
T10 2046 12 0 0
T11 6258 46 0 0
T12 145065 2167 0 0
T13 5427 68 0 0

Line Coverage for Instance : tb.dut.u_sm1_43
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_43
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 297351 0 0
gen_host_fifo[1].idInRange 406276418 375265 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4172519 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 297351 0 0
T1 10303 8 0 0
T2 68261 883 0 0
T3 42412 359 0 0
T7 52986 109 0 0
T8 248519 646 0 0
T9 24130 200 0 0
T10 2046 4 0 0
T11 6258 22 0 0
T12 145065 1839 0 0
T13 5427 27 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 375265 0 0
T1 10303 5 0 0
T2 68261 707 0 0
T3 42412 348 0 0
T7 52986 154 0 0
T8 248519 916 0 0
T9 24130 200 0 0
T10 2046 10 0 0
T11 6258 17 0 0
T12 145065 1447 0 0
T13 5427 39 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4172519 0 0
T1 10303 18 0 0
T2 68261 1293 0 0
T3 42412 681 0 0
T7 52986 845 0 0
T8 248519 1584 0 0
T9 24130 382 0 0
T10 2046 14 0 0
T11 6258 39 0 0
T12 145065 2007 0 0
T13 5427 66 0 0

Line Coverage for Instance : tb.dut.u_sm1_44
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_44
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 276302 0 0
gen_host_fifo[1].idInRange 406276418 380186 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4792408 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 276302 0 0
T1 10303 5 0 0
T2 68261 446 0 0
T3 42412 337 0 0
T7 52986 93 0 0
T8 248519 2520 0 0
T9 24130 214 0 0
T10 2046 4 0 0
T11 6258 33 0 0
T12 145065 923 0 0
T13 5427 40 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 380186 0 0
T1 10303 4 0 0
T2 68261 425 0 0
T3 42412 304 0 0
T7 52986 65 0 0
T8 248519 4081 0 0
T9 24130 198 0 0
T10 2046 9 0 0
T11 6258 28 0 0
T12 145065 877 0 0
T13 5427 41 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4792408 0 0
T1 10303 15 0 0
T2 68261 844 0 0
T3 42412 623 0 0
T7 52986 701 0 0
T8 248519 2856 0 0
T9 24130 392 0 0
T10 2046 13 0 0
T11 6258 57 0 0
T12 145065 1657 0 0
T13 5427 76 0 0

Line Coverage for Instance : tb.dut.u_sm1_45
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_45
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 305846 0 0
gen_host_fifo[1].idInRange 406276418 376590 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4376977 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 305846 0 0
T1 10303 5 0 0
T2 68261 438 0 0
T3 42412 670 0 0
T7 52986 96 0 0
T8 248519 1179 0 0
T9 24130 216 0 0
T10 2046 10 0 0
T11 6258 17 0 0
T12 145065 1233 0 0
T13 5427 23 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 376590 0 0
T1 10303 22 0 0
T2 68261 409 0 0
T3 42412 641 0 0
T7 52986 128 0 0
T8 248519 892 0 0
T9 24130 235 0 0
T10 2046 5 0 0
T11 6258 24 0 0
T12 145065 1323 0 0
T13 5427 52 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4376977 0 0
T1 10303 20 0 0
T2 68261 813 0 0
T3 42412 1125 0 0
T7 52986 558 0 0
T8 248519 1322 0 0
T9 24130 428 0 0
T10 2046 14 0 0
T11 6258 41 0 0
T12 145065 2168 0 0
T13 5427 75 0 0

Line Coverage for Instance : tb.dut.u_sm1_46
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_46
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T11
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 282464 0 0
gen_host_fifo[1].idInRange 406276418 362564 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4629514 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 282464 0 0
T1 10303 9 0 0
T2 68261 482 0 0
T3 42412 346 0 0
T7 52986 107 0 0
T8 248519 206 0 0
T9 24130 200 0 0
T10 2046 5 0 0
T11 6258 25 0 0
T12 145065 978 0 0
T13 5427 22 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 362564 0 0
T1 10303 3 0 0
T2 68261 406 0 0
T3 42412 316 0 0
T7 52986 145 0 0
T8 248519 224 0 0
T9 24130 201 0 0
T10 2046 8 0 0
T11 6258 34 0 0
T12 145065 857 0 0
T13 5427 26 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4629514 0 0
T1 10303 12 0 0
T2 68261 859 0 0
T3 42412 641 0 0
T7 52986 640 0 0
T8 248519 572 0 0
T9 24130 391 0 0
T10 2046 13 0 0
T11 6258 58 0 0
T12 145065 1676 0 0
T13 5427 47 0 0

Line Coverage for Instance : tb.dut.u_sm1_47
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_47
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT8,T14,T19
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 262479 0 0
gen_host_fifo[1].idInRange 406276418 336677 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4086328 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 262479 0 0
T1 10303 9 0 0
T2 68261 764 0 0
T3 42412 327 0 0
T7 52986 119 0 0
T8 248519 546 0 0
T9 24130 207 0 0
T10 2046 4 0 0
T11 6258 29 0 0
T12 145065 925 0 0
T13 5427 36 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 336677 0 0
T1 10303 5 0 0
T2 68261 794 0 0
T3 42412 334 0 0
T7 52986 81 0 0
T8 248519 843 0 0
T9 24130 214 0 0
T10 2046 6 0 0
T11 6258 28 0 0
T12 145065 960 0 0
T13 5427 32 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4086328 0 0
T1 10303 37 0 0
T2 68261 1381 0 0
T3 42412 636 0 0
T7 52986 765 0 0
T8 248519 1982 0 0
T9 24130 406 0 0
T10 2046 10 0 0
T11 6258 54 0 0
T12 145065 1568 0 0
T13 5427 64 0 0

Line Coverage for Instance : tb.dut.u_sm1_48
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_48
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 283739 0 0
gen_host_fifo[1].idInRange 406276418 350208 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4085312 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 283739 0 0
T1 10303 13 0 0
T2 68261 891 0 0
T3 42412 368 0 0
T7 52986 107 0 0
T8 248519 154 0 0
T9 24130 210 0 0
T10 2046 10 0 0
T11 6258 34 0 0
T12 145065 1936 0 0
T13 5427 41 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 350208 0 0
T1 10303 11 0 0
T2 68261 702 0 0
T3 42412 312 0 0
T7 52986 87 0 0
T8 248519 151 0 0
T9 24130 197 0 0
T10 2046 6 0 0
T11 6258 24 0 0
T12 145065 1673 0 0
T13 5427 44 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4085312 0 0
T1 10303 28 0 0
T2 68261 1300 0 0
T3 42412 657 0 0
T7 52986 651 0 0
T8 248519 472 0 0
T9 24130 391 0 0
T10 2046 14 0 0
T11 6258 55 0 0
T12 145065 2176 0 0
T13 5427 78 0 0

Line Coverage for Instance : tb.dut.u_sm1_49
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_49
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 323083 0 0
gen_host_fifo[1].idInRange 406276418 405579 0 0
maxM 900 900 0 0
rspIdInRange 406276418 5594996 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 323083 0 0
T1 10303 26 0 0
T2 68261 410 0 0
T3 42412 675 0 0
T7 52986 82 0 0
T8 248519 1596 0 0
T9 24130 196 0 0
T10 2046 9 0 0
T11 6258 33 0 0
T12 145065 1577 0 0
T13 5427 33 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 405579 0 0
T1 10303 3 0 0
T2 68261 412 0 0
T3 42412 707 0 0
T7 52986 119 0 0
T8 248519 2302 0 0
T9 24130 213 0 0
T10 2046 3 0 0
T11 6258 34 0 0
T12 145065 1211 0 0
T13 5427 34 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 5594996 0 0
T1 10303 17 0 0
T2 68261 800 0 0
T3 42412 1154 0 0
T7 52986 667 0 0
T8 248519 1056 0 0
T9 24130 389 0 0
T10 2046 11 0 0
T11 6258 66 0 0
T12 145065 1602 0 0
T13 5427 61 0 0

Line Coverage for Instance : tb.dut.u_sm1_50
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_50
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 278408 0 0
gen_host_fifo[1].idInRange 406276418 361900 0 0
maxM 900 900 0 0
rspIdInRange 406276418 3745055 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 278408 0 0
T1 10303 7 0 0
T2 68261 410 0 0
T3 42412 338 0 0
T7 52986 107 0 0
T8 248519 1163 0 0
T9 24130 193 0 0
T10 2046 7 0 0
T11 6258 32 0 0
T12 145065 824 0 0
T13 5427 30 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 361900 0 0
T1 10303 4 0 0
T2 68261 454 0 0
T3 42412 293 0 0
T7 52986 177 0 0
T8 248519 2141 0 0
T9 24130 202 0 0
T10 2046 4 0 0
T11 6258 22 0 0
T12 145065 884 0 0
T13 5427 30 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 3745055 0 0
T1 10303 12 0 0
T2 68261 838 0 0
T3 42412 607 0 0
T7 52986 740 0 0
T8 248519 1529 0 0
T9 24130 373 0 0
T10 2046 10 0 0
T11 6258 51 0 0
T12 145065 1563 0 0
T13 5427 59 0 0

Line Coverage for Instance : tb.dut.u_sm1_51
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_51
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T10
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 321282 0 0
gen_host_fifo[1].idInRange 406276418 415514 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4815763 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 321282 0 0
T1 10303 18 0 0
T2 68261 982 0 0
T3 42412 351 0 0
T7 52986 98 0 0
T8 248519 3832 0 0
T9 24130 228 0 0
T10 2046 15 0 0
T11 6258 53 0 0
T12 145065 2810 0 0
T13 5427 43 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 415514 0 0
T1 10303 5 0 0
T2 68261 866 0 0
T3 42412 305 0 0
T7 52986 95 0 0
T8 248519 5735 0 0
T9 24130 201 0 0
T10 2046 11 0 0
T11 6258 40 0 0
T12 145065 2248 0 0
T13 5427 59 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4815763 0 0
T1 10303 12 0 0
T2 68261 1479 0 0
T3 42412 637 0 0
T7 52986 735 0 0
T8 248519 3617 0 0
T9 24130 399 0 0
T10 2046 22 0 0
T11 6258 90 0 0
T12 145065 3171 0 0
T13 5427 98 0 0

Line Coverage for Instance : tb.dut.u_sm1_52
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_52
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T11
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 254043 0 0
gen_host_fifo[1].idInRange 406276418 325711 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4215194 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 254043 0 0
T1 10303 4 0 0
T2 68261 419 0 0
T3 42412 340 0 0
T7 52986 84 0 0
T8 248519 144 0 0
T9 24130 209 0 0
T10 2046 5 0 0
T11 6258 29 0 0
T12 145065 1296 0 0
T13 5427 27 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 325711 0 0
T1 10303 15 0 0
T2 68261 388 0 0
T3 42412 310 0 0
T7 52986 121 0 0
T8 248519 134 0 0
T9 24130 202 0 0
T10 2046 12 0 0
T11 6258 23 0 0
T12 145065 1173 0 0
T13 5427 36 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4215194 0 0
T1 10303 8 0 0
T2 68261 776 0 0
T3 42412 619 0 0
T7 52986 604 0 0
T8 248519 425 0 0
T9 24130 394 0 0
T10 2046 17 0 0
T11 6258 51 0 0
T12 145065 2112 0 0
T13 5427 60 0 0

Line Coverage for Instance : tb.dut.u_sm1_53
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_53
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 302804 0 0
gen_host_fifo[1].idInRange 406276418 384926 0 0
maxM 900 900 0 0
rspIdInRange 406276418 4809148 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 302804 0 0
T1 10303 10 0 0
T2 68261 682 0 0
T3 42412 650 0 0
T7 52986 98 0 0
T8 248519 4744 0 0
T9 24130 194 0 0
T10 2046 2 0 0
T11 6258 18 0 0
T12 145065 1228 0 0
T13 5427 29 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 384926 0 0
T1 10303 4 0 0
T2 68261 759 0 0
T3 42412 653 0 0
T7 52986 99 0 0
T8 248519 6156 0 0
T9 24130 208 0 0
T10 2046 9 0 0
T11 6258 33 0 0
T12 145065 1360 0 0
T13 5427 28 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 4809148 0 0
T1 10303 22 0 0
T2 68261 1314 0 0
T3 42412 1129 0 0
T7 52986 793 0 0
T8 248519 2475 0 0
T9 24130 392 0 0
T10 2046 11 0 0
T11 6258 51 0 0
T12 145065 2114 0 0
T13 5427 56 0 0

Line Coverage for Instance : tb.dut.u_sm1_54
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_54
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT2,T3,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 310235 0 0
gen_host_fifo[1].idInRange 406276418 391938 0 0
maxM 900 900 0 0
rspIdInRange 406276418 3986106 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 310235 0 0
T1 10303 5 0 0
T2 68261 799 0 0
T3 42412 822 0 0
T7 52986 65 0 0
T8 248519 144 0 0
T9 24130 189 0 0
T10 2046 5 0 0
T11 6258 28 0 0
T12 145065 1252 0 0
T13 5427 29 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 391938 0 0
T1 10303 3 0 0
T2 68261 726 0 0
T3 42412 772 0 0
T7 52986 112 0 0
T8 248519 145 0 0
T9 24130 173 0 0
T10 2046 13 0 0
T11 6258 25 0 0
T12 145065 1163 0 0
T13 5427 37 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 3986106 0 0
T1 10303 11 0 0
T2 68261 1368 0 0
T3 42412 1311 0 0
T7 52986 637 0 0
T8 248519 459 0 0
T9 24130 347 0 0
T10 2046 18 0 0
T11 6258 51 0 0
T12 145065 2033 0 0
T13 5427 63 0 0

Line Coverage for Instance : tb.dut.u_sm1_55
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_55
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 266111 0 0
gen_host_fifo[1].idInRange 406276418 340789 0 0
maxM 900 900 0 0
rspIdInRange 406276418 3692093 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 266111 0 0
T1 10303 18 0 0
T2 68261 1376 0 0
T3 42412 673 0 0
T7 52986 118 0 0
T8 248519 1053 0 0
T9 24130 193 0 0
T10 2046 8 0 0
T11 6258 24 0 0
T12 145065 1537 0 0
T13 5427 42 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 340789 0 0
T1 10303 4 0 0
T2 68261 1025 0 0
T3 42412 579 0 0
T7 52986 91 0 0
T8 248519 1698 0 0
T9 24130 199 0 0
T10 2046 9 0 0
T11 6258 34 0 0
T12 145065 1220 0 0
T13 5427 27 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 3692093 0 0
T1 10303 51 0 0
T2 68261 1711 0 0
T3 42412 1126 0 0
T7 52986 758 0 0
T8 248519 1411 0 0
T9 24130 379 0 0
T10 2046 16 0 0
T11 6258 57 0 0
T12 145065 1567 0 0
T13 5427 66 0 0

Line Coverage for Instance : tb.dut.u_sm1_56
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_56
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T14
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 311963 0 0
gen_host_fifo[1].idInRange 406276418 381333 0 0
maxM 900 900 0 0
rspIdInRange 406276418 3508503 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 311963 0 0
T1 10303 5 0 0
T2 68261 384 0 0
T3 42412 339 0 0
T7 52986 121 0 0
T8 248519 1827 0 0
T9 24130 271 0 0
T10 2046 5 0 0
T11 6258 27 0 0
T12 145065 4224 0 0
T13 5427 34 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 381333 0 0
T1 10303 4 0 0
T2 68261 448 0 0
T3 42412 336 0 0
T7 52986 154 0 0
T8 248519 3086 0 0
T9 24130 296 0 0
T10 2046 11 0 0
T11 6258 25 0 0
T12 145065 3387 0 0
T13 5427 38 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 3508503 0 0
T1 10303 14 0 0
T2 68261 808 0 0
T3 42412 653 0 0
T7 52986 646 0 0
T8 248519 2469 0 0
T9 24130 502 0 0
T10 2046 16 0 0
T11 6258 51 0 0
T12 145065 3503 0 0
T13 5427 68 0 0

Line Coverage for Instance : tb.dut.u_sm1_30
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_30
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T13,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T13,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T13,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT2,T13,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T7,T8
101CoveredT1,T2,T3
110CoveredT2,T13,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT2,T13,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 406276418 8871966 0 0
gen_host_fifo[1].idInRange 406276418 1614823 0 0
gen_host_fifo[2].idInRange 406276418 1710287 0 0
maxM 900 900 0 0
rspIdInRange 406276418 18283032 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 8871966 0 0
T1 10303 399 0 0
T2 68261 3633 0 0
T3 42412 2396 0 0
T7 52986 3014 0 0
T8 248519 22400 0 0
T9 24130 1853 0 0
T10 2046 36 0 0
T11 6258 173 0 0
T12 145065 7081 0 0
T13 5427 214 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 1614823 0 0
T1 10303 57 0 0
T2 68261 810 0 0
T3 42412 351 0 0
T7 52986 607 0 0
T8 248519 9981 0 0
T9 24130 475 0 0
T10 2046 5 0 0
T11 6258 25 0 0
T12 145065 1613 0 0
T13 5427 26 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 1710287 0 0
T1 10303 30 0 0
T2 68261 636 0 0
T3 42412 306 0 0
T7 52986 660 0 0
T8 248519 10284 0 0
T9 24130 417 0 0
T10 2046 6 0 0
T11 6258 36 0 0
T12 145065 1368 0 0
T13 5427 37 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 406276418 18283032 0 0
T1 10303 395 0 0
T2 68261 4818 0 0
T3 42412 2999 0 0
T7 52986 3634 0 0
T8 248519 17876 0 0
T9 24130 2534 0 0
T10 2046 47 0 0
T11 6258 232 0 0
T12 145065 8660 0 0
T13 5427 271 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%