Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8009249	0	0
GntImpliesValid_A	2147483647	8009249	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8009249	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	432470227	0	0
ReadyAndValidImplyGrant_A	2147483647	8009249	0	0
ReqAndReadyImplyGrant_A	2147483647	8009249	0	0
ReqImpliesValid_A	2147483647	31665274	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48144	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8009249	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	247272	247032	0	0
T2	1638264	1633944	0	0
T3	1017888	1017360	0	0
T7	1271664	1271256	0	0
T8	5964456	5959056	0	0
T9	579120	570960	0	0
T10	49104	48888	0	0
T11	150192	148536	0	0
T12	3481560	3480072	0	0
T13	130248	129816	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8009249	0	0
T1	247272	466	0	0
T2	1638264	38646	0	0
T3	1017888	29085	0	0
T7	1271664	5048	0	0
T8	5964456	25112	0	0
T9	579120	16221	0	0
T10	49104	514	0	0
T11	150192	2092	0	0
T12	3481560	79167	0	0
T13	130248	2376	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8009249	0	0
T1	247272	466	0	0
T2	1638264	38646	0	0
T3	1017888	29085	0	0
T7	1271664	5048	0	0
T8	5964456	25112	0	0
T9	579120	16221	0	0
T10	49104	514	0	0
T11	150192	2092	0	0
T12	3481560	79167	0	0
T13	130248	2376	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	247272	247032	0	0
T2	1638264	1633944	0	0
T3	1017888	1017360	0	0
T7	1271664	1271256	0	0
T8	5964456	5959056	0	0
T9	579120	570960	0	0
T10	49104	48888	0	0
T11	150192	148536	0	0
T12	3481560	3480072	0	0
T13	130248	129816	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	247272	247032	0	0
T2	1638264	1633944	0	0
T3	1017888	1017360	0	0
T7	1271664	1271256	0	0
T8	5964456	5959056	0	0
T9	579120	570960	0	0
T10	49104	48888	0	0
T11	150192	148536	0	0
T12	3481560	3480072	0	0
T13	130248	129816	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8009249	0	0
T1	247272	466	0	0
T2	1638264	38646	0	0
T3	1017888	29085	0	0
T7	1271664	5048	0	0
T8	5964456	25112	0	0
T9	579120	16221	0	0
T10	49104	514	0	0
T11	150192	2092	0	0
T12	3481560	79167	0	0
T13	130248	2376	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	432470227	0	0
T1	247272	12110	0	0
T2	1638264	44912	0	0
T3	1017888	26589	0	0
T7	1271664	79617	0	0
T8	5964456	327844	0	0
T9	579120	16182	0	0
T10	49104	629	0	0
T11	150192	3406	0	0
T12	3481560	69971	0	0
T13	130248	2422	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8009249	0	0
T1	247272	466	0	0
T2	1638264	38646	0	0
T3	1017888	29085	0	0
T7	1271664	5048	0	0
T8	5964456	25112	0	0
T9	579120	16221	0	0
T10	49104	514	0	0
T11	150192	2092	0	0
T12	3481560	79167	0	0
T13	130248	2376	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8009249	0	0
T1	247272	466	0	0
T2	1638264	38646	0	0
T3	1017888	29085	0	0
T7	1271664	5048	0	0
T8	5964456	25112	0	0
T9	579120	16221	0	0
T10	49104	514	0	0
T11	150192	2092	0	0
T12	3481560	79167	0	0
T13	130248	2376	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31665274	0	0
T1	247272	1083	0	0
T2	1638264	44964	0	0
T3	1017888	32499	0	0
T7	1271664	11372	0	0
T8	5964456	99426	0	0
T9	579120	18543	0	0
T10	49104	567	0	0
T11	150192	2389	0	0
T12	3481560	115096	0	0
T13	130248	2568	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48144	0	21600
T2	136522	302	0	2
T3	84824	275	0	2
T7	105972	0	0	2
T8	497038	36	0	2
T9	48260	223	0	2
T10	4092	0	0	2
T11	12516	4	0	2
T12	290130	1311	0	2
T13	10854	6	0	2
T14	625972	21	0	2
T15	0	321	0	0
T16	0	3	0	0
T17	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	247272	247032	0	0
T2	1638264	1633944	0	0
T3	1017888	1017360	0	0
T7	1271664	1271256	0	0
T8	5964456	5959056	0	0
T9	579120	570960	0	0
T10	49104	48888	0	0
T11	150192	148536	0	0
T12	3481560	3480072	0	0
T13	130248	129816	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8009249	0	0
T1	247272	466	0	0
T2	1638264	38646	0	0
T3	1017888	29085	0	0
T7	1271664	5048	0	0
T8	5964456	25112	0	0
T9	579120	16221	0	0
T10	49104	514	0	0
T11	150192	2092	0	0
T12	3481560	79167	0	0
T13	130248	2376	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	883964	0	0
GntImpliesValid_A	406276418	883964	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	883964	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	10338472	0	0
ReadyAndValidImplyGrant_A	406276418	883964	0	0
ReqAndReadyImplyGrant_A	406276418	883964	0	0
ReqImpliesValid_A	406276418	2208180	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	883964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	883964	0	0
T1	10303	53	0	0
T2	68261	3889	0	0
T3	42412	3080	0	0
T7	52986	508	0	0
T8	248519	2763	0	0
T9	24130	1839	0	0
T10	2046	68	0	0
T11	6258	229	0	0
T12	145065	10749	0	0
T13	5427	253	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	883964	0	0
T1	10303	53	0	0
T2	68261	3889	0	0
T3	42412	3080	0	0
T7	52986	508	0	0
T8	248519	2763	0	0
T9	24130	1839	0	0
T10	2046	68	0	0
T11	6258	229	0	0
T12	145065	10749	0	0
T13	5427	253	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	883964	0	0
T1	10303	53	0	0
T2	68261	3889	0	0
T3	42412	3080	0	0
T7	52986	508	0	0
T8	248519	2763	0	0
T9	24130	1839	0	0
T10	2046	68	0	0
T11	6258	229	0	0
T12	145065	10749	0	0
T13	5427	253	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	10338472	0	0
T1	10303	394	0	0
T2	68261	3154	0	0
T3	42412	2362	0	0
T7	52986	3808	0	0
T8	248519	18576	0	0
T9	24130	1452	0	0
T10	2046	48	0	0
T11	6258	185	0	0
T12	145065	6552	0	0
T13	5427	222	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	883964	0	0
T1	10303	53	0	0
T2	68261	3889	0	0
T3	42412	3080	0	0
T7	52986	508	0	0
T8	248519	2763	0	0
T9	24130	1839	0	0
T10	2046	68	0	0
T11	6258	229	0	0
T12	145065	10749	0	0
T13	5427	253	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	883964	0	0
T1	10303	53	0	0
T2	68261	3889	0	0
T3	42412	3080	0	0
T7	52986	508	0	0
T8	248519	2763	0	0
T9	24130	1839	0	0
T10	2046	68	0	0
T11	6258	229	0	0
T12	145065	10749	0	0
T13	5427	253	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2208180	0	0
T1	10303	74	0	0
T2	68261	4628	0	0
T3	42412	3800	0	0
T7	52986	910	0	0
T8	248519	8003	0	0
T9	24130	2233	0	0
T10	2046	89	0	0
T11	6258	274	0	0
T12	145065	14951	0	0
T13	5427	285	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	883964	0	0
T1	10303	53	0	0
T2	68261	3889	0	0
T3	42412	3080	0	0
T7	52986	508	0	0
T8	248519	2763	0	0
T9	24130	1839	0	0
T10	2046	68	0	0
T11	6258	229	0	0
T12	145065	10749	0	0
T13	5427	253	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	889230	0	0
GntImpliesValid_A	406276418	889230	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	889230	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	10391816	0	0
ReadyAndValidImplyGrant_A	406276418	889230	0	0
ReqAndReadyImplyGrant_A	406276418	889230	0	0
ReqImpliesValid_A	406276418	2333910	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	889230	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	889230	0	0
T1	10303	59	0	0
T2	68261	3924	0	0
T3	42412	2963	0	0
T7	52986	495	0	0
T8	248519	2054	0	0
T9	24130	1804	0	0
T10	2046	45	0	0
T11	6258	254	0	0
T12	145065	8049	0	0
T13	5427	272	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	889230	0	0
T1	10303	59	0	0
T2	68261	3924	0	0
T3	42412	2963	0	0
T7	52986	495	0	0
T8	248519	2054	0	0
T9	24130	1804	0	0
T10	2046	45	0	0
T11	6258	254	0	0
T12	145065	8049	0	0
T13	5427	272	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	889230	0	0
T1	10303	59	0	0
T2	68261	3924	0	0
T3	42412	2963	0	0
T7	52986	495	0	0
T8	248519	2054	0	0
T9	24130	1804	0	0
T10	2046	45	0	0
T11	6258	254	0	0
T12	145065	8049	0	0
T13	5427	272	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	10391816	0	0
T1	10303	426	0	0
T2	68261	3181	0	0
T3	42412	2300	0	0
T7	52986	3540	0	0
T8	248519	15106	0	0
T9	24130	1449	0	0
T10	2046	40	0	0
T11	6258	215	0	0
T12	145065	5721	0	0
T13	5427	228	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	889230	0	0
T1	10303	59	0	0
T2	68261	3924	0	0
T3	42412	2963	0	0
T7	52986	495	0	0
T8	248519	2054	0	0
T9	24130	1804	0	0
T10	2046	45	0	0
T11	6258	254	0	0
T12	145065	8049	0	0
T13	5427	272	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	889230	0	0
T1	10303	59	0	0
T2	68261	3924	0	0
T3	42412	2963	0	0
T7	52986	495	0	0
T8	248519	2054	0	0
T9	24130	1804	0	0
T10	2046	45	0	0
T11	6258	254	0	0
T12	145065	8049	0	0
T13	5427	272	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2333910	0	0
T1	10303	95	0	0
T2	68261	4671	0	0
T3	42412	3628	0	0
T7	52986	880	0	0
T8	248519	3408	0	0
T9	24130	2168	0	0
T10	2046	51	0	0
T11	6258	294	0	0
T12	145065	10382	0	0
T13	5427	317	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	889230	0	0
T1	10303	59	0	0
T2	68261	3924	0	0
T3	42412	2963	0	0
T7	52986	495	0	0
T8	248519	2054	0	0
T9	24130	1804	0	0
T10	2046	45	0	0
T11	6258	254	0	0
T12	145065	8049	0	0
T13	5427	272	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	225044	0	0
GntImpliesValid_A	406276418	225044	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	225044	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2712875	0	0
ReadyAndValidImplyGrant_A	406276418	225044	0	0
ReqAndReadyImplyGrant_A	406276418	225044	0	0
ReqImpliesValid_A	406276418	585110	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	225044	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	225044	0	0
T1	10303	12	0	0
T2	68261	779	0	0
T3	42412	665	0	0
T7	52986	128	0	0
T8	248519	296	0	0
T9	24130	413	0	0
T10	2046	14	0	0
T11	6258	69	0	0
T12	145065	2599	0	0
T13	5427	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	225044	0	0
T1	10303	12	0	0
T2	68261	779	0	0
T3	42412	665	0	0
T7	52986	128	0	0
T8	248519	296	0	0
T9	24130	413	0	0
T10	2046	14	0	0
T11	6258	69	0	0
T12	145065	2599	0	0
T13	5427	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	225044	0	0
T1	10303	12	0	0
T2	68261	779	0	0
T3	42412	665	0	0
T7	52986	128	0	0
T8	248519	296	0	0
T9	24130	413	0	0
T10	2046	14	0	0
T11	6258	69	0	0
T12	145065	2599	0	0
T13	5427	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2712875	0	0
T1	10303	102	0	0
T2	68261	764	0	0
T3	42412	643	0	0
T7	52986	931	0	0
T8	248519	2149	0	0
T9	24130	404	0	0
T10	2046	14	0	0
T11	6258	66	0	0
T12	145065	1952	0	0
T13	5427	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	225044	0	0
T1	10303	12	0	0
T2	68261	779	0	0
T3	42412	665	0	0
T7	52986	128	0	0
T8	248519	296	0	0
T9	24130	413	0	0
T10	2046	14	0	0
T11	6258	69	0	0
T12	145065	2599	0	0
T13	5427	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	225044	0	0
T1	10303	12	0	0
T2	68261	779	0	0
T3	42412	665	0	0
T7	52986	128	0	0
T8	248519	296	0	0
T9	24130	413	0	0
T10	2046	14	0	0
T11	6258	69	0	0
T12	145065	2599	0	0
T13	5427	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	585110	0	0
T1	10303	12	0	0
T2	68261	798	0	0
T3	42412	689	0	0
T7	52986	177	0	0
T8	248519	351	0	0
T9	24130	432	0	0
T10	2046	15	0	0
T11	6258	73	0	0
T12	145065	3251	0	0
T13	5427	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	225044	0	0
T1	10303	12	0	0
T2	68261	779	0	0
T3	42412	665	0	0
T7	52986	128	0	0
T8	248519	296	0	0
T9	24130	413	0	0
T10	2046	14	0	0
T11	6258	69	0	0
T12	145065	2599	0	0
T13	5427	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	219867	0	0
GntImpliesValid_A	406276418	219867	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	219867	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2610532	0	0
ReadyAndValidImplyGrant_A	406276418	219867	0	0
ReqAndReadyImplyGrant_A	406276418	219867	0	0
ReqImpliesValid_A	406276418	535265	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	219867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219867	0	0
T1	10303	11	0	0
T2	68261	1278	0	0
T3	42412	1112	0	0
T7	52986	157	0	0
T8	248519	286	0	0
T9	24130	392	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2149	0	0
T13	5427	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219867	0	0
T1	10303	11	0	0
T2	68261	1278	0	0
T3	42412	1112	0	0
T7	52986	157	0	0
T8	248519	286	0	0
T9	24130	392	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2149	0	0
T13	5427	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219867	0	0
T1	10303	11	0	0
T2	68261	1278	0	0
T3	42412	1112	0	0
T7	52986	157	0	0
T8	248519	286	0	0
T9	24130	392	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2149	0	0
T13	5427	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2610532	0	0
T1	10303	87	0	0
T2	68261	1159	0	0
T3	42412	992	0	0
T7	52986	1251	0	0
T8	248519	2091	0	0
T9	24130	388	0	0
T10	2046	21	0	0
T11	6258	59	0	0
T12	145065	1544	0	0
T13	5427	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219867	0	0
T1	10303	11	0	0
T2	68261	1278	0	0
T3	42412	1112	0	0
T7	52986	157	0	0
T8	248519	286	0	0
T9	24130	392	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2149	0	0
T13	5427	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219867	0	0
T1	10303	11	0	0
T2	68261	1278	0	0
T3	42412	1112	0	0
T7	52986	157	0	0
T8	248519	286	0	0
T9	24130	392	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2149	0	0
T13	5427	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	535265	0	0
T1	10303	12	0	0
T2	68261	1401	0	0
T3	42412	1234	0	0
T7	52986	206	0	0
T8	248519	343	0	0
T9	24130	406	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2759	0	0
T13	5427	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219867	0	0
T1	10303	11	0	0
T2	68261	1278	0	0
T3	42412	1112	0	0
T7	52986	157	0	0
T8	248519	286	0	0
T9	24130	392	0	0
T10	2046	20	0	0
T11	6258	58	0	0
T12	145065	2149	0	0
T13	5427	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	230731	0	0
GntImpliesValid_A	406276418	230731	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	230731	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	4245408	0	0
ReadyAndValidImplyGrant_A	406276418	230731	0	0
ReqAndReadyImplyGrant_A	406276418	230731	0	0
ReqImpliesValid_A	406276418	1121513	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	230731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	230731	0	0
T1	10303	16	0	0
T2	68261	858	0	0
T3	42412	673	0	0
T7	52986	152	0	0
T8	248519	307	0	0
T9	24130	558	0	0
T10	2046	19	0	0
T11	6258	63	0	0
T12	145065	2026	0	0
T13	5427	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	230731	0	0
T1	10303	16	0	0
T2	68261	858	0	0
T3	42412	673	0	0
T7	52986	152	0	0
T8	248519	307	0	0
T9	24130	558	0	0
T10	2046	19	0	0
T11	6258	63	0	0
T12	145065	2026	0	0
T13	5427	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	230731	0	0
T1	10303	16	0	0
T2	68261	858	0	0
T3	42412	673	0	0
T7	52986	152	0	0
T8	248519	307	0	0
T9	24130	558	0	0
T10	2046	19	0	0
T11	6258	63	0	0
T12	145065	2026	0	0
T13	5427	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	4245408	0	0
T1	10303	110	0	0
T2	68261	5103	0	0
T3	42412	2213	0	0
T7	52986	2509	0	0
T8	248519	2332	0	0
T9	24130	2157	0	0
T10	2046	68	0	0
T11	6258	525	0	0
T12	145065	10160	0	0
T13	5427	261	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	230731	0	0
T1	10303	16	0	0
T2	68261	858	0	0
T3	42412	673	0	0
T7	52986	152	0	0
T8	248519	307	0	0
T9	24130	558	0	0
T10	2046	19	0	0
T11	6258	63	0	0
T12	145065	2026	0	0
T13	5427	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	230731	0	0
T1	10303	16	0	0
T2	68261	858	0	0
T3	42412	673	0	0
T7	52986	152	0	0
T8	248519	307	0	0
T9	24130	558	0	0
T10	2046	19	0	0
T11	6258	63	0	0
T12	145065	2026	0	0
T13	5427	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	1121513	0	0
T1	10303	18	0	0
T2	68261	1098	0	0
T3	42412	834	0	0
T7	52986	287	0	0
T8	248519	353	0	0
T9	24130	844	0	0
T10	2046	26	0	0
T11	6258	111	0	0
T12	145065	5994	0	0
T13	5427	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	230731	0	0
T1	10303	16	0	0
T2	68261	858	0	0
T3	42412	673	0	0
T7	52986	152	0	0
T8	248519	307	0	0
T9	24130	558	0	0
T10	2046	19	0	0
T11	6258	63	0	0
T12	145065	2026	0	0
T13	5427	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	218897	0	0
GntImpliesValid_A	406276418	218897	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	218897	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	5250418	0	0
ReadyAndValidImplyGrant_A	406276418	218897	0	0
ReqAndReadyImplyGrant_A	406276418	218897	0	0
ReqImpliesValid_A	406276418	1204218	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	218897	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	218897	0	0
T1	10303	16	0	0
T2	68261	1316	0	0
T3	42412	651	0	0
T7	52986	131	0	0
T8	248519	273	0	0
T9	24130	435	0	0
T10	2046	12	0	0
T11	6258	49	0	0
T12	145065	2556	0	0
T13	5427	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	218897	0	0
T1	10303	16	0	0
T2	68261	1316	0	0
T3	42412	651	0	0
T7	52986	131	0	0
T8	248519	273	0	0
T9	24130	435	0	0
T10	2046	12	0	0
T11	6258	49	0	0
T12	145065	2556	0	0
T13	5427	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	218897	0	0
T1	10303	16	0	0
T2	68261	1316	0	0
T3	42412	651	0	0
T7	52986	131	0	0
T8	248519	273	0	0
T9	24130	435	0	0
T10	2046	12	0	0
T11	6258	49	0	0
T12	145065	2556	0	0
T13	5427	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	5250418	0	0
T1	10303	179	0	0
T2	68261	6141	0	0
T3	42412	2122	0	0
T7	52986	1449	0	0
T8	248519	1947	0	0
T9	24130	1843	0	0
T10	2046	90	0	0
T11	6258	264	0	0
T12	145065	9535	0	0
T13	5427	238	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	218897	0	0
T1	10303	16	0	0
T2	68261	1316	0	0
T3	42412	651	0	0
T7	52986	131	0	0
T8	248519	273	0	0
T9	24130	435	0	0
T10	2046	12	0	0
T11	6258	49	0	0
T12	145065	2556	0	0
T13	5427	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	218897	0	0
T1	10303	16	0	0
T2	68261	1316	0	0
T3	42412	651	0	0
T7	52986	131	0	0
T8	248519	273	0	0
T9	24130	435	0	0
T10	2046	12	0	0
T11	6258	49	0	0
T12	145065	2556	0	0
T13	5427	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	1204218	0	0
T1	10303	31	0	0
T2	68261	2673	0	0
T3	42412	820	0	0
T7	52986	257	0	0
T8	248519	299	0	0
T9	24130	539	0	0
T10	2046	12	0	0
T11	6258	66	0	0
T12	145065	9551	0	0
T13	5427	100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	218897	0	0
T1	10303	16	0	0
T2	68261	1316	0	0
T3	42412	651	0	0
T7	52986	131	0	0
T8	248519	273	0	0
T9	24130	435	0	0
T10	2046	12	0	0
T11	6258	49	0	0
T12	145065	2556	0	0
T13	5427	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	219080	0	0
GntImpliesValid_A	406276418	219080	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	219080	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	4347755	0	0
ReadyAndValidImplyGrant_A	406276418	219080	0	0
ReqAndReadyImplyGrant_A	406276418	219080	0	0
ReqImpliesValid_A	406276418	1030330	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	219080	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219080	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	633	0	0
T7	52986	135	0	0
T8	248519	823	0	0
T9	24130	512	0	0
T10	2046	18	0	0
T11	6258	59	0	0
T12	145065	2950	0	0
T13	5427	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219080	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	633	0	0
T7	52986	135	0	0
T8	248519	823	0	0
T9	24130	512	0	0
T10	2046	18	0	0
T11	6258	59	0	0
T12	145065	2950	0	0
T13	5427	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219080	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	633	0	0
T7	52986	135	0	0
T8	248519	823	0	0
T9	24130	512	0	0
T10	2046	18	0	0
T11	6258	59	0	0
T12	145065	2950	0	0
T13	5427	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	4347755	0	0
T1	10303	164	0	0
T2	68261	4711	0	0
T3	42412	2094	0	0
T7	52986	1352	0	0
T8	248519	3058	0	0
T9	24130	1643	0	0
T10	2046	59	0	0
T11	6258	1056	0	0
T12	145065	7847	0	0
T13	5427	179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219080	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	633	0	0
T7	52986	135	0	0
T8	248519	823	0	0
T9	24130	512	0	0
T10	2046	18	0	0
T11	6258	59	0	0
T12	145065	2950	0	0
T13	5427	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219080	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	633	0	0
T7	52986	135	0	0
T8	248519	823	0	0
T9	24130	512	0	0
T10	2046	18	0	0
T11	6258	59	0	0
T12	145065	2950	0	0
T13	5427	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	1030330	0	0
T1	10303	11	0	0
T2	68261	1094	0	0
T3	42412	767	0	0
T7	52986	216	0	0
T8	248519	3342	0	0
T9	24130	1267	0	0
T10	2046	26	0	0
T11	6258	156	0	0
T12	145065	9236	0	0
T13	5427	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219080	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	633	0	0
T7	52986	135	0	0
T8	248519	823	0	0
T9	24130	512	0	0
T10	2046	18	0	0
T11	6258	59	0	0
T12	145065	2950	0	0
T13	5427	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	222100	0	0
GntImpliesValid_A	406276418	222100	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	222100	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	5649042	0	0
ReadyAndValidImplyGrant_A	406276418	222100	0	0
ReqAndReadyImplyGrant_A	406276418	222100	0	0
ReqImpliesValid_A	406276418	1247135	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	222100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	222100	0	0
T1	10303	12	0	0
T2	68261	1366	0	0
T3	42412	1033	0	0
T7	52986	139	0	0
T8	248519	300	0	0
T9	24130	402	0	0
T10	2046	12	0	0
T11	6258	46	0	0
T12	145065	2167	0	0
T13	5427	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	222100	0	0
T1	10303	12	0	0
T2	68261	1366	0	0
T3	42412	1033	0	0
T7	52986	139	0	0
T8	248519	300	0	0
T9	24130	402	0	0
T10	2046	12	0	0
T11	6258	46	0	0
T12	145065	2167	0	0
T13	5427	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	222100	0	0
T1	10303	12	0	0
T2	68261	1366	0	0
T3	42412	1033	0	0
T7	52986	139	0	0
T8	248519	300	0	0
T9	24130	402	0	0
T10	2046	12	0	0
T11	6258	46	0	0
T12	145065	2167	0	0
T13	5427	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	5649042	0	0
T1	10303	69	0	0
T2	68261	6639	0	0
T3	42412	3045	0	0
T7	52986	920	0	0
T8	248519	2390	0	0
T9	24130	1365	0	0
T10	2046	84	0	0
T11	6258	270	0	0
T12	145065	4299	0	0
T13	5427	250	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	222100	0	0
T1	10303	12	0	0
T2	68261	1366	0	0
T3	42412	1033	0	0
T7	52986	139	0	0
T8	248519	300	0	0
T9	24130	402	0	0
T10	2046	12	0	0
T11	6258	46	0	0
T12	145065	2167	0	0
T13	5427	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	222100	0	0
T1	10303	12	0	0
T2	68261	1366	0	0
T3	42412	1033	0	0
T7	52986	139	0	0
T8	248519	300	0	0
T9	24130	402	0	0
T10	2046	12	0	0
T11	6258	46	0	0
T12	145065	2167	0	0
T13	5427	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	1247135	0	0
T1	10303	12	0	0
T2	68261	2618	0	0
T3	42412	1640	0	0
T7	52986	170	0	0
T8	248519	330	0	0
T9	24130	550	0	0
T10	2046	12	0	0
T11	6258	70	0	0
T12	145065	6418	0	0
T13	5427	77	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	222100	0	0
T1	10303	12	0	0
T2	68261	1366	0	0
T3	42412	1033	0	0
T7	52986	139	0	0
T8	248519	300	0	0
T9	24130	402	0	0
T10	2046	12	0	0
T11	6258	46	0	0
T12	145065	2167	0	0
T13	5427	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	219053	0	0
GntImpliesValid_A	406276418	219053	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	219053	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2621161	0	0
ReadyAndValidImplyGrant_A	406276418	219053	0	0
ReqAndReadyImplyGrant_A	406276418	219053	0	0
ReqImpliesValid_A	406276418	557816	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	219053	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219053	0	0
T1	10303	13	0	0
T2	68261	1293	0	0
T3	42412	681	0	0
T7	52986	162	0	0
T8	248519	789	0	0
T9	24130	382	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2007	0	0
T13	5427	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219053	0	0
T1	10303	13	0	0
T2	68261	1293	0	0
T3	42412	681	0	0
T7	52986	162	0	0
T8	248519	789	0	0
T9	24130	382	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2007	0	0
T13	5427	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219053	0	0
T1	10303	13	0	0
T2	68261	1293	0	0
T3	42412	681	0	0
T7	52986	162	0	0
T8	248519	789	0	0
T9	24130	382	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2007	0	0
T13	5427	66	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2621161	0	0
T1	10303	102	0	0
T2	68261	1096	0	0
T3	42412	660	0	0
T7	52986	1125	0	0
T8	248519	4893	0	0
T9	24130	378	0	0
T10	2046	15	0	0
T11	6258	40	0	0
T12	145065	1415	0	0
T13	5427	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219053	0	0
T1	10303	13	0	0
T2	68261	1293	0	0
T3	42412	681	0	0
T7	52986	162	0	0
T8	248519	789	0	0
T9	24130	382	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2007	0	0
T13	5427	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219053	0	0
T1	10303	13	0	0
T2	68261	1293	0	0
T3	42412	681	0	0
T7	52986	162	0	0
T8	248519	789	0	0
T9	24130	382	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2007	0	0
T13	5427	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	557816	0	0
T1	10303	13	0	0
T2	68261	1494	0	0
T3	42412	704	0	0
T7	52986	263	0	0
T8	248519	1480	0	0
T9	24130	396	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2604	0	0
T13	5427	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	219053	0	0
T1	10303	13	0	0
T2	68261	1293	0	0
T3	42412	681	0	0
T7	52986	162	0	0
T8	248519	789	0	0
T9	24130	382	0	0
T10	2046	14	0	0
T11	6258	39	0	0
T12	145065	2007	0	0
T13	5427	66	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	223820	0	0
GntImpliesValid_A	406276418	223820	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	223820	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2642228	0	0
ReadyAndValidImplyGrant_A	406276418	223820	0	0
ReqAndReadyImplyGrant_A	406276418	223820	0	0
ReqImpliesValid_A	406276418	553187	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	223820	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	223820	0	0
T1	10303	9	0	0
T2	68261	844	0	0
T3	42412	623	0	0
T7	52986	148	0	0
T8	248519	1285	0	0
T9	24130	393	0	0
T10	2046	13	0	0
T11	6258	57	0	0
T12	145065	1657	0	0
T13	5427	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	223820	0	0
T1	10303	9	0	0
T2	68261	844	0	0
T3	42412	623	0	0
T7	52986	148	0	0
T8	248519	1285	0	0
T9	24130	393	0	0
T10	2046	13	0	0
T11	6258	57	0	0
T12	145065	1657	0	0
T13	5427	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	223820	0	0
T1	10303	9	0	0
T2	68261	844	0	0
T3	42412	623	0	0
T7	52986	148	0	0
T8	248519	1285	0	0
T9	24130	393	0	0
T10	2046	13	0	0
T11	6258	57	0	0
T12	145065	1657	0	0
T13	5427	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2642228	0	0
T1	10303	66	0	0
T2	68261	823	0	0
T3	42412	609	0	0
T7	52986	1142	0	0
T8	248519	7171	0	0
T9	24130	386	0	0
T10	2046	14	0	0
T11	6258	54	0	0
T12	145065	1554	0	0
T13	5427	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	223820	0	0
T1	10303	9	0	0
T2	68261	844	0	0
T3	42412	623	0	0
T7	52986	148	0	0
T8	248519	1285	0	0
T9	24130	393	0	0
T10	2046	13	0	0
T11	6258	57	0	0
T12	145065	1657	0	0
T13	5427	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	223820	0	0
T1	10303	9	0	0
T2	68261	844	0	0
T3	42412	623	0	0
T7	52986	148	0	0
T8	248519	1285	0	0
T9	24130	393	0	0
T10	2046	13	0	0
T11	6258	57	0	0
T12	145065	1657	0	0
T13	5427	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	553187	0	0
T1	10303	9	0	0
T2	68261	869	0	0
T3	42412	639	0	0
T7	52986	158	0	0
T8	248519	5792	0	0
T9	24130	410	0	0
T10	2046	13	0	0
T11	6258	61	0	0
T12	145065	1765	0	0
T13	5427	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	223820	0	0
T1	10303	9	0	0
T2	68261	844	0	0
T3	42412	623	0	0
T7	52986	148	0	0
T8	248519	1285	0	0
T9	24130	393	0	0
T10	2046	13	0	0
T11	6258	57	0	0
T12	145065	1657	0	0
T13	5427	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	227538	0	0
GntImpliesValid_A	406276418	227538	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	227538	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2676363	0	0
ReadyAndValidImplyGrant_A	406276418	227538	0	0
ReqAndReadyImplyGrant_A	406276418	227538	0	0
ReqImpliesValid_A	406276418	562129	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	227538	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	227538	0	0
T1	10303	10	0	0
T2	68261	813	0	0
T3	42412	1125	0	0
T7	52986	155	0	0
T8	248519	712	0	0
T9	24130	428	0	0
T10	2046	14	0	0
T11	6258	41	0	0
T12	145065	2168	0	0
T13	5427	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	227538	0	0
T1	10303	10	0	0
T2	68261	813	0	0
T3	42412	1125	0	0
T7	52986	155	0	0
T8	248519	712	0	0
T9	24130	428	0	0
T10	2046	14	0	0
T11	6258	41	0	0
T12	145065	2168	0	0
T13	5427	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	227538	0	0
T1	10303	10	0	0
T2	68261	813	0	0
T3	42412	1125	0	0
T7	52986	155	0	0
T8	248519	712	0	0
T9	24130	428	0	0
T10	2046	14	0	0
T11	6258	41	0	0
T12	145065	2168	0	0
T13	5427	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2676363	0	0
T1	10303	60	0	0
T2	68261	789	0	0
T3	42412	1005	0	0
T7	52986	1088	0	0
T8	248519	4907	0	0
T9	24130	419	0	0
T10	2046	14	0	0
T11	6258	42	0	0
T12	145065	1940	0	0
T13	5427	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	227538	0	0
T1	10303	10	0	0
T2	68261	813	0	0
T3	42412	1125	0	0
T7	52986	155	0	0
T8	248519	712	0	0
T9	24130	428	0	0
T10	2046	14	0	0
T11	6258	41	0	0
T12	145065	2168	0	0
T13	5427	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	227538	0	0
T1	10303	10	0	0
T2	68261	813	0	0
T3	42412	1125	0	0
T7	52986	155	0	0
T8	248519	712	0	0
T9	24130	428	0	0
T10	2046	14	0	0
T11	6258	41	0	0
T12	145065	2168	0	0
T13	5427	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	562129	0	0
T1	10303	27	0	0
T2	68261	841	0	0
T3	42412	1247	0	0
T7	52986	224	0	0
T8	248519	1870	0	0
T9	24130	447	0	0
T10	2046	15	0	0
T11	6258	41	0	0
T12	145065	2401	0	0
T13	5427	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	227538	0	0
T1	10303	10	0	0
T2	68261	813	0	0
T3	42412	1125	0	0
T7	52986	155	0	0
T8	248519	712	0	0
T9	24130	428	0	0
T10	2046	14	0	0
T11	6258	41	0	0
T12	145065	2168	0	0
T13	5427	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	228481	0	0
GntImpliesValid_A	406276418	228481	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	228481	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2646108	0	0
ReadyAndValidImplyGrant_A	406276418	228481	0	0
ReqAndReadyImplyGrant_A	406276418	228481	0	0
ReqImpliesValid_A	406276418	539859	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	228481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	228481	0	0
T1	10303	12	0	0
T2	68261	859	0	0
T3	42412	641	0	0
T7	52986	146	0	0
T8	248519	310	0	0
T9	24130	391	0	0
T10	2046	13	0	0
T11	6258	58	0	0
T12	145065	1676	0	0
T13	5427	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	228481	0	0
T1	10303	12	0	0
T2	68261	859	0	0
T3	42412	641	0	0
T7	52986	146	0	0
T8	248519	310	0	0
T9	24130	391	0	0
T10	2046	13	0	0
T11	6258	58	0	0
T12	145065	1676	0	0
T13	5427	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	228481	0	0
T1	10303	12	0	0
T2	68261	859	0	0
T3	42412	641	0	0
T7	52986	146	0	0
T8	248519	310	0	0
T9	24130	391	0	0
T10	2046	13	0	0
T11	6258	58	0	0
T12	145065	1676	0	0
T13	5427	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2646108	0	0
T1	10303	76	0	0
T2	68261	836	0	0
T3	42412	623	0	0
T7	52986	1077	0	0
T8	248519	2376	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	58	0	0
T12	145065	1570	0	0
T13	5427	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	228481	0	0
T1	10303	12	0	0
T2	68261	859	0	0
T3	42412	641	0	0
T7	52986	146	0	0
T8	248519	310	0	0
T9	24130	391	0	0
T10	2046	13	0	0
T11	6258	58	0	0
T12	145065	1676	0	0
T13	5427	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	228481	0	0
T1	10303	12	0	0
T2	68261	859	0	0
T3	42412	641	0	0
T7	52986	146	0	0
T8	248519	310	0	0
T9	24130	391	0	0
T10	2046	13	0	0
T11	6258	58	0	0
T12	145065	1676	0	0
T13	5427	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	539859	0	0
T1	10303	12	0	0
T2	68261	886	0	0
T3	42412	661	0	0
T7	52986	252	0	0
T8	248519	422	0	0
T9	24130	401	0	0
T10	2046	13	0	0
T11	6258	59	0	0
T12	145065	1787	0	0
T13	5427	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	228481	0	0
T1	10303	12	0	0
T2	68261	859	0	0
T3	42412	641	0	0
T7	52986	146	0	0
T8	248519	310	0	0
T9	24130	391	0	0
T10	2046	13	0	0
T11	6258	58	0	0
T12	145065	1676	0	0
T13	5427	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	209377	0	0
GntImpliesValid_A	406276418	209377	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	209377	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2611515	0	0
ReadyAndValidImplyGrant_A	406276418	209377	0	0
ReqAndReadyImplyGrant_A	406276418	209377	0	0
ReqImpliesValid_A	406276418	506777	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	209377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	209377	0	0
T1	10303	14	0	0
T2	68261	1381	0	0
T3	42412	636	0	0
T7	52986	160	0	0
T8	248519	820	0	0
T9	24130	407	0	0
T10	2046	10	0	0
T11	6258	54	0	0
T12	145065	1568	0	0
T13	5427	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	209377	0	0
T1	10303	14	0	0
T2	68261	1381	0	0
T3	42412	636	0	0
T7	52986	160	0	0
T8	248519	820	0	0
T9	24130	407	0	0
T10	2046	10	0	0
T11	6258	54	0	0
T12	145065	1568	0	0
T13	5427	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	209377	0	0
T1	10303	14	0	0
T2	68261	1381	0	0
T3	42412	636	0	0
T7	52986	160	0	0
T8	248519	820	0	0
T9	24130	407	0	0
T10	2046	10	0	0
T11	6258	54	0	0
T12	145065	1568	0	0
T13	5427	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2611515	0	0
T1	10303	100	0	0
T2	68261	1272	0	0
T3	42412	621	0	0
T7	52986	1285	0	0
T8	248519	4633	0	0
T9	24130	405	0	0
T10	2046	11	0	0
T11	6258	52	0	0
T12	145065	1382	0	0
T13	5427	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	209377	0	0
T1	10303	14	0	0
T2	68261	1381	0	0
T3	42412	636	0	0
T7	52986	160	0	0
T8	248519	820	0	0
T9	24130	407	0	0
T10	2046	10	0	0
T11	6258	54	0	0
T12	145065	1568	0	0
T13	5427	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	209377	0	0
T1	10303	14	0	0
T2	68261	1381	0	0
T3	42412	636	0	0
T7	52986	160	0	0
T8	248519	820	0	0
T9	24130	407	0	0
T10	2046	10	0	0
T11	6258	54	0	0
T12	145065	1568	0	0
T13	5427	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	506777	0	0
T1	10303	14	0	0
T2	68261	1494	0	0
T3	42412	653	0	0
T7	52986	200	0	0
T8	248519	1380	0	0
T9	24130	419	0	0
T10	2046	10	0	0
T11	6258	57	0	0
T12	145065	1759	0	0
T13	5427	68	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	209377	0	0
T1	10303	14	0	0
T2	68261	1381	0	0
T3	42412	636	0	0
T7	52986	160	0	0
T8	248519	820	0	0
T9	24130	407	0	0
T10	2046	10	0	0
T11	6258	54	0	0
T12	145065	1568	0	0
T13	5427	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	221200	0	0
GntImpliesValid_A	406276418	221200	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	221200	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2615144	0	0
ReadyAndValidImplyGrant_A	406276418	221200	0	0
ReqAndReadyImplyGrant_A	406276418	221200	0	0
ReqImpliesValid_A	406276418	530604	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	221200	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	221200	0	0
T1	10303	16	0	0
T2	68261	1300	0	0
T3	42412	657	0	0
T7	52986	132	0	0
T8	248519	259	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	55	0	0
T12	145065	2176	0	0
T13	5427	78	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	221200	0	0
T1	10303	16	0	0
T2	68261	1300	0	0
T3	42412	657	0	0
T7	52986	132	0	0
T8	248519	259	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	55	0	0
T12	145065	2176	0	0
T13	5427	78	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	221200	0	0
T1	10303	16	0	0
T2	68261	1300	0	0
T3	42412	657	0	0
T7	52986	132	0	0
T8	248519	259	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	55	0	0
T12	145065	2176	0	0
T13	5427	78	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2615144	0	0
T1	10303	150	0	0
T2	68261	1086	0	0
T3	42412	639	0	0
T7	52986	969	0	0
T8	248519	2024	0	0
T9	24130	385	0	0
T10	2046	13	0	0
T11	6258	54	0	0
T12	145065	1520	0	0
T13	5427	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	221200	0	0
T1	10303	16	0	0
T2	68261	1300	0	0
T3	42412	657	0	0
T7	52986	132	0	0
T8	248519	259	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	55	0	0
T12	145065	2176	0	0
T13	5427	78	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	221200	0	0
T1	10303	16	0	0
T2	68261	1300	0	0
T3	42412	657	0	0
T7	52986	132	0	0
T8	248519	259	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	55	0	0
T12	145065	2176	0	0
T13	5427	78	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	530604	0	0
T1	10303	24	0	0
T2	68261	1518	0	0
T3	42412	677	0	0
T7	52986	189	0	0
T8	248519	305	0	0
T9	24130	407	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	2837	0	0
T13	5427	82	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	221200	0	0
T1	10303	16	0	0
T2	68261	1300	0	0
T3	42412	657	0	0
T7	52986	132	0	0
T8	248519	259	0	0
T9	24130	391	0	0
T10	2046	14	0	0
T11	6258	55	0	0
T12	145065	2176	0	0
T13	5427	78	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	231413	0	0
GntImpliesValid_A	406276418	231413	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	231413	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2652340	0	0
ReadyAndValidImplyGrant_A	406276418	231413	0	0
ReqAndReadyImplyGrant_A	406276418	231413	0	0
ReqImpliesValid_A	406276418	598793	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	231413	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231413	0	0
T1	10303	11	0	0
T2	68261	800	0	0
T3	42412	1154	0	0
T7	52986	147	0	0
T8	248519	541	0	0
T9	24130	389	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1602	0	0
T13	5427	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231413	0	0
T1	10303	11	0	0
T2	68261	800	0	0
T3	42412	1154	0	0
T7	52986	147	0	0
T8	248519	541	0	0
T9	24130	389	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1602	0	0
T13	5427	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231413	0	0
T1	10303	11	0	0
T2	68261	800	0	0
T3	42412	1154	0	0
T7	52986	147	0	0
T8	248519	541	0	0
T9	24130	389	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1602	0	0
T13	5427	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2652340	0	0
T1	10303	76	0	0
T2	68261	785	0	0
T3	42412	1013	0	0
T7	52986	1194	0	0
T8	248519	2501	0	0
T9	24130	381	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1078	0	0
T13	5427	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231413	0	0
T1	10303	11	0	0
T2	68261	800	0	0
T3	42412	1154	0	0
T7	52986	147	0	0
T8	248519	541	0	0
T9	24130	389	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1602	0	0
T13	5427	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231413	0	0
T1	10303	11	0	0
T2	68261	800	0	0
T3	42412	1154	0	0
T7	52986	147	0	0
T8	248519	541	0	0
T9	24130	389	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1602	0	0
T13	5427	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	598793	0	0
T1	10303	29	0	0
T2	68261	819	0	0
T3	42412	1297	0	0
T7	52986	201	0	0
T8	248519	2800	0	0
T9	24130	407	0	0
T10	2046	12	0	0
T11	6258	67	0	0
T12	145065	2131	0	0
T13	5427	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231413	0	0
T1	10303	11	0	0
T2	68261	800	0	0
T3	42412	1154	0	0
T7	52986	147	0	0
T8	248519	541	0	0
T9	24130	389	0	0
T10	2046	11	0	0
T11	6258	66	0	0
T12	145065	1602	0	0
T13	5427	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	216385	0	0
GntImpliesValid_A	406276418	216385	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	216385	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2641795	0	0
ReadyAndValidImplyGrant_A	406276418	216385	0	0
ReqAndReadyImplyGrant_A	406276418	216385	0	0
ReqImpliesValid_A	406276418	537089	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	216385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	216385	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	607	0	0
T7	52986	159	0	0
T8	248519	802	0	0
T9	24130	373	0	0
T10	2046	10	0	0
T11	6258	51	0	0
T12	145065	1563	0	0
T13	5427	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	216385	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	607	0	0
T7	52986	159	0	0
T8	248519	802	0	0
T9	24130	373	0	0
T10	2046	10	0	0
T11	6258	51	0	0
T12	145065	1563	0	0
T13	5427	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	216385	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	607	0	0
T7	52986	159	0	0
T8	248519	802	0	0
T9	24130	373	0	0
T10	2046	10	0	0
T11	6258	51	0	0
T12	145065	1563	0	0
T13	5427	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2641795	0	0
T1	10303	105	0	0
T2	68261	820	0	0
T3	42412	590	0	0
T7	52986	1164	0	0
T8	248519	4898	0	0
T9	24130	364	0	0
T10	2046	10	0	0
T11	6258	49	0	0
T12	145065	1463	0	0
T13	5427	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	216385	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	607	0	0
T7	52986	159	0	0
T8	248519	802	0	0
T9	24130	373	0	0
T10	2046	10	0	0
T11	6258	51	0	0
T12	145065	1563	0	0
T13	5427	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	216385	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	607	0	0
T7	52986	159	0	0
T8	248519	802	0	0
T9	24130	373	0	0
T10	2046	10	0	0
T11	6258	51	0	0
T12	145065	1563	0	0
T13	5427	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	537089	0	0
T1	10303	11	0	0
T2	68261	860	0	0
T3	42412	626	0	0
T7	52986	284	0	0
T8	248519	2857	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	54	0	0
T12	145065	1668	0	0
T13	5427	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	216385	0	0
T1	10303	11	0	0
T2	68261	838	0	0
T3	42412	607	0	0
T7	52986	159	0	0
T8	248519	802	0	0
T9	24130	373	0	0
T10	2046	10	0	0
T11	6258	51	0	0
T12	145065	1563	0	0
T13	5427	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	252269	0	0
GntImpliesValid_A	406276418	252269	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	252269	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2805427	0	0
ReadyAndValidImplyGrant_A	406276418	252269	0	0
ReqAndReadyImplyGrant_A	406276418	252269	0	0
ReqImpliesValid_A	406276418	616312	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	252269	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	252269	0	0
T1	10303	12	0	0
T2	68261	1479	0	0
T3	42412	637	0	0
T7	52986	148	0	0
T8	248519	1742	0	0
T9	24130	400	0	0
T10	2046	22	0	0
T11	6258	90	0	0
T12	145065	3171	0	0
T13	5427	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	252269	0	0
T1	10303	12	0	0
T2	68261	1479	0	0
T3	42412	637	0	0
T7	52986	148	0	0
T8	248519	1742	0	0
T9	24130	400	0	0
T10	2046	22	0	0
T11	6258	90	0	0
T12	145065	3171	0	0
T13	5427	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	252269	0	0
T1	10303	12	0	0
T2	68261	1479	0	0
T3	42412	637	0	0
T7	52986	148	0	0
T8	248519	1742	0	0
T9	24130	400	0	0
T10	2046	22	0	0
T11	6258	90	0	0
T12	145065	3171	0	0
T13	5427	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2805427	0	0
T1	10303	94	0	0
T2	68261	1244	0	0
T3	42412	622	0	0
T7	52986	1078	0	0
T8	248519	9335	0	0
T9	24130	386	0	0
T10	2046	19	0	0
T11	6258	88	0	0
T12	145065	2211	0	0
T13	5427	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	252269	0	0
T1	10303	12	0	0
T2	68261	1479	0	0
T3	42412	637	0	0
T7	52986	148	0	0
T8	248519	1742	0	0
T9	24130	400	0	0
T10	2046	22	0	0
T11	6258	90	0	0
T12	145065	3171	0	0
T13	5427	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	252269	0	0
T1	10303	12	0	0
T2	68261	1479	0	0
T3	42412	637	0	0
T7	52986	148	0	0
T8	248519	1742	0	0
T9	24130	400	0	0
T10	2046	22	0	0
T11	6258	90	0	0
T12	145065	3171	0	0
T13	5427	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	616312	0	0
T1	10303	23	0	0
T2	68261	1718	0	0
T3	42412	654	0	0
T7	52986	193	0	0
T8	248519	7605	0	0
T9	24130	423	0	0
T10	2046	26	0	0
T11	6258	93	0	0
T12	145065	4136	0	0
T13	5427	102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	252269	0	0
T1	10303	12	0	0
T2	68261	1479	0	0
T3	42412	637	0	0
T7	52986	148	0	0
T8	248519	1742	0	0
T9	24130	400	0	0
T10	2046	22	0	0
T11	6258	90	0	0
T12	145065	3171	0	0
T13	5427	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	214682	0	0
GntImpliesValid_A	406276418	214682	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	214682	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2618698	0	0
ReadyAndValidImplyGrant_A	406276418	214682	0	0
ReqAndReadyImplyGrant_A	406276418	214682	0	0
ReqImpliesValid_A	406276418	495251	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	214682	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	214682	0	0
T1	10303	8	0	0
T2	68261	776	0	0
T3	42412	619	0	0
T7	52986	146	0	0
T8	248519	264	0	0
T9	24130	394	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	2112	0	0
T13	5427	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	214682	0	0
T1	10303	8	0	0
T2	68261	776	0	0
T3	42412	619	0	0
T7	52986	146	0	0
T8	248519	264	0	0
T9	24130	394	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	2112	0	0
T13	5427	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	214682	0	0
T1	10303	8	0	0
T2	68261	776	0	0
T3	42412	619	0	0
T7	52986	146	0	0
T8	248519	264	0	0
T9	24130	394	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	2112	0	0
T13	5427	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2618698	0	0
T1	10303	74	0	0
T2	68261	754	0	0
T3	42412	595	0	0
T7	52986	1025	0	0
T8	248519	2072	0	0
T9	24130	389	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	1870	0	0
T13	5427	58	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	214682	0	0
T1	10303	8	0	0
T2	68261	776	0	0
T3	42412	619	0	0
T7	52986	146	0	0
T8	248519	264	0	0
T9	24130	394	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	2112	0	0
T13	5427	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	214682	0	0
T1	10303	8	0	0
T2	68261	776	0	0
T3	42412	619	0	0
T7	52986	146	0	0
T8	248519	264	0	0
T9	24130	394	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	2112	0	0
T13	5427	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	495251	0	0
T1	10303	19	0	0
T2	68261	802	0	0
T3	42412	645	0	0
T7	52986	205	0	0
T8	248519	278	0	0
T9	24130	409	0	0
T10	2046	17	0	0
T11	6258	52	0	0
T12	145065	2359	0	0
T13	5427	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	214682	0	0
T1	10303	8	0	0
T2	68261	776	0	0
T3	42412	619	0	0
T7	52986	146	0	0
T8	248519	264	0	0
T9	24130	394	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	2112	0	0
T13	5427	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	231733	0	0
GntImpliesValid_A	406276418	231733	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	231733	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2681891	0	0
ReadyAndValidImplyGrant_A	406276418	231733	0	0
ReqAndReadyImplyGrant_A	406276418	231733	0	0
ReqImpliesValid_A	406276418	576000	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	231733	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231733	0	0
T1	10303	13	0	0
T2	68261	1314	0	0
T3	42412	1129	0	0
T7	52986	159	0	0
T8	248519	1173	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2114	0	0
T13	5427	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231733	0	0
T1	10303	13	0	0
T2	68261	1314	0	0
T3	42412	1129	0	0
T7	52986	159	0	0
T8	248519	1173	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2114	0	0
T13	5427	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231733	0	0
T1	10303	13	0	0
T2	68261	1314	0	0
T3	42412	1129	0	0
T7	52986	159	0	0
T8	248519	1173	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2114	0	0
T13	5427	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2681891	0	0
T1	10303	96	0	0
T2	68261	1224	0	0
T3	42412	1022	0	0
T7	52986	1120	0	0
T8	248519	4558	0	0
T9	24130	393	0	0
T10	2046	12	0	0
T11	6258	52	0	0
T12	145065	1813	0	0
T13	5427	56	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231733	0	0
T1	10303	13	0	0
T2	68261	1314	0	0
T3	42412	1129	0	0
T7	52986	159	0	0
T8	248519	1173	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2114	0	0
T13	5427	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231733	0	0
T1	10303	13	0	0
T2	68261	1314	0	0
T3	42412	1129	0	0
T7	52986	159	0	0
T8	248519	1173	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2114	0	0
T13	5427	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	576000	0	0
T1	10303	14	0	0
T2	68261	1408	0	0
T3	42412	1238	0	0
T7	52986	197	0	0
T8	248519	7584	0	0
T9	24130	401	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2420	0	0
T13	5427	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	231733	0	0
T1	10303	13	0	0
T2	68261	1314	0	0
T3	42412	1129	0	0
T7	52986	159	0	0
T8	248519	1173	0	0
T9	24130	392	0	0
T10	2046	11	0	0
T11	6258	51	0	0
T12	145065	2114	0	0
T13	5427	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	224020	0	0
GntImpliesValid_A	406276418	224020	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	224020	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2638496	0	0
ReadyAndValidImplyGrant_A	406276418	224020	0	0
ReqAndReadyImplyGrant_A	406276418	224020	0	0
ReqImpliesValid_A	406276418	571562	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	224020	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	224020	0	0
T1	10303	8	0	0
T2	68261	1368	0	0
T3	42412	1311	0	0
T7	52986	133	0	0
T8	248519	254	0	0
T9	24130	347	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	2033	0	0
T13	5427	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	224020	0	0
T1	10303	8	0	0
T2	68261	1368	0	0
T3	42412	1311	0	0
T7	52986	133	0	0
T8	248519	254	0	0
T9	24130	347	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	2033	0	0
T13	5427	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	224020	0	0
T1	10303	8	0	0
T2	68261	1368	0	0
T3	42412	1311	0	0
T7	52986	133	0	0
T8	248519	254	0	0
T9	24130	347	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	2033	0	0
T13	5427	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2638496	0	0
T1	10303	63	0	0
T2	68261	1261	0	0
T3	42412	1139	0	0
T7	52986	1015	0	0
T8	248519	1878	0	0
T9	24130	344	0	0
T10	2046	19	0	0
T11	6258	50	0	0
T12	145065	1776	0	0
T13	5427	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	224020	0	0
T1	10303	8	0	0
T2	68261	1368	0	0
T3	42412	1311	0	0
T7	52986	133	0	0
T8	248519	254	0	0
T9	24130	347	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	2033	0	0
T13	5427	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	224020	0	0
T1	10303	8	0	0
T2	68261	1368	0	0
T3	42412	1311	0	0
T7	52986	133	0	0
T8	248519	254	0	0
T9	24130	347	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	2033	0	0
T13	5427	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	571562	0	0
T1	10303	8	0	0
T2	68261	1479	0	0
T3	42412	1485	0	0
T7	52986	177	0	0
T8	248519	289	0	0
T9	24130	360	0	0
T10	2046	18	0	0
T11	6258	53	0	0
T12	145065	2295	0	0
T13	5427	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	224020	0	0
T1	10303	8	0	0
T2	68261	1368	0	0
T3	42412	1311	0	0
T7	52986	133	0	0
T8	248519	254	0	0
T9	24130	347	0	0
T10	2046	18	0	0
T11	6258	51	0	0
T12	145065	2033	0	0
T13	5427	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	213318	0	0
GntImpliesValid_A	406276418	213318	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	213318	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2630872	0	0
ReadyAndValidImplyGrant_A	406276418	213318	0	0
ReqAndReadyImplyGrant_A	406276418	213318	0	0
ReqImpliesValid_A	406276418	515046	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	213318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	213318	0	0
T1	10303	17	0	0
T2	68261	1711	0	0
T3	42412	1126	0	0
T7	52986	155	0	0
T8	248519	810	0	0
T9	24130	380	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1567	0	0
T13	5427	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	213318	0	0
T1	10303	17	0	0
T2	68261	1711	0	0
T3	42412	1126	0	0
T7	52986	155	0	0
T8	248519	810	0	0
T9	24130	380	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1567	0	0
T13	5427	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	213318	0	0
T1	10303	17	0	0
T2	68261	1711	0	0
T3	42412	1126	0	0
T7	52986	155	0	0
T8	248519	810	0	0
T9	24130	380	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1567	0	0
T13	5427	66	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2630872	0	0
T1	10303	113	0	0
T2	68261	1274	0	0
T3	42412	1041	0	0
T7	52986	1276	0	0
T8	248519	5308	0	0
T9	24130	381	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1078	0	0
T13	5427	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	213318	0	0
T1	10303	17	0	0
T2	68261	1711	0	0
T3	42412	1126	0	0
T7	52986	155	0	0
T8	248519	810	0	0
T9	24130	380	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1567	0	0
T13	5427	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	213318	0	0
T1	10303	17	0	0
T2	68261	1711	0	0
T3	42412	1126	0	0
T7	52986	155	0	0
T8	248519	810	0	0
T9	24130	380	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1567	0	0
T13	5427	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	515046	0	0
T1	10303	22	0	0
T2	68261	2152	0	0
T3	42412	1213	0	0
T7	52986	209	0	0
T8	248519	2425	0	0
T9	24130	389	0	0
T10	2046	17	0	0
T11	6258	58	0	0
T12	145065	2061	0	0
T13	5427	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	213318	0	0
T1	10303	17	0	0
T2	68261	1711	0	0
T3	42412	1126	0	0
T7	52986	155	0	0
T8	248519	810	0	0
T9	24130	380	0	0
T10	2046	16	0	0
T11	6258	57	0	0
T12	145065	1567	0	0
T13	5427	66	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	215996	0	0
GntImpliesValid_A	406276418	215996	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	215996	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	2651550	0	0
ReadyAndValidImplyGrant_A	406276418	215996	0	0
ReqAndReadyImplyGrant_A	406276418	215996	0	0
ReqImpliesValid_A	406276418	567313	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	0	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	215996	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	215996	0	0
T1	10303	9	0	0
T2	68261	808	0	0
T3	42412	653	0	0
T7	52986	160	0	0
T8	248519	1172	0	0
T9	24130	502	0	0
T10	2046	16	0	0
T11	6258	51	0	0
T12	145065	3503	0	0
T13	5427	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	215996	0	0
T1	10303	9	0	0
T2	68261	808	0	0
T3	42412	653	0	0
T7	52986	160	0	0
T8	248519	1172	0	0
T9	24130	502	0	0
T10	2046	16	0	0
T11	6258	51	0	0
T12	145065	3503	0	0
T13	5427	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	215996	0	0
T1	10303	9	0	0
T2	68261	808	0	0
T3	42412	653	0	0
T7	52986	160	0	0
T8	248519	1172	0	0
T9	24130	502	0	0
T10	2046	16	0	0
T11	6258	51	0	0
T12	145065	3503	0	0
T13	5427	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2651550	0	0
T1	10303	68	0	0
T2	68261	791	0	0
T3	42412	636	0	0
T7	52986	1229	0	0
T8	248519	6928	0	0
T9	24130	468	0	0
T10	2046	17	0	0
T11	6258	51	0	0
T12	145065	1685	0	0
T13	5427	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	215996	0	0
T1	10303	9	0	0
T2	68261	808	0	0
T3	42412	653	0	0
T7	52986	160	0	0
T8	248519	1172	0	0
T9	24130	502	0	0
T10	2046	16	0	0
T11	6258	51	0	0
T12	145065	3503	0	0
T13	5427	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	215996	0	0
T1	10303	9	0	0
T2	68261	808	0	0
T3	42412	653	0	0
T7	52986	160	0	0
T8	248519	1172	0	0
T9	24130	502	0	0
T10	2046	16	0	0
T11	6258	51	0	0
T12	145065	3503	0	0
T13	5427	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	567313	0	0
T1	10303	9	0	0
T2	68261	829	0	0
T3	42412	672	0	0
T7	52986	275	0	0
T8	248519	4323	0	0
T9	24130	546	0	0
T10	2046	16	0	0
T11	6258	52	0	0
T12	145065	5326	0	0
T13	5427	72	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	215996	0	0
T1	10303	9	0	0
T2	68261	808	0	0
T3	42412	653	0	0
T7	52986	160	0	0
T8	248519	1172	0	0
T9	24130	502	0	0
T10	2046	16	0	0
T11	6258	51	0	0
T12	145065	3503	0	0
T13	5427	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	892006	0	0
GntImpliesValid_A	406276418	892006	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	892006	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	9908839	0	0
ReadyAndValidImplyGrant_A	406276418	892006	0	0
ReqAndReadyImplyGrant_A	406276418	892006	0	0
ReqImpliesValid_A	406276418	2051602	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	19855	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	892006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	892006	0	0
T1	10303	55	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	555	0	0
T8	248519	3534	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	892006	0	0
T1	10303	55	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	555	0	0
T8	248519	3534	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	892006	0	0
T1	10303	55	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	555	0	0
T8	248519	3534	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	9908839	0	0
T1	10303	383	0	0
T2	68261	4	0	0
T3	42412	2	0	0
T7	52986	3595	0	0
T8	248519	19457	0	0
T9	24130	10	0	0
T10	2046	1	0	0
T11	6258	1	0	0
T12	145065	5	0	0
T13	5427	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	892006	0	0
T1	10303	55	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	555	0	0
T8	248519	3534	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	892006	0	0
T1	10303	55	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	555	0	0
T8	248519	3534	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	2051602	0	0
T1	10303	98	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	1027	0	0
T8	248519	11418	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	19855	0	900
T2	68261	59	0	1
T3	42412	221	0	1
T7	52986	0	0	1
T8	248519	15	0	1
T9	24130	32	0	1
T10	2046	0	0	1
T11	6258	2	0	1
T12	145065	515	0	1
T13	5427	3	0	1
T14	312986	0	0	1
T15	0	233	0	0
T16	0	2	0	0
T17	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	892006	0	0
T1	10303	55	0	0
T2	68261	3996	0	0
T3	42412	3677	0	0
T7	52986	555	0	0
T8	248519	3534	0	0
T9	24130	1762	0	0
T10	2046	60	0	0
T11	6258	261	0	0
T12	145065	8345	0	0
T13	5427	261	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406276418	406152952	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406276418	879045	0	0
GntImpliesValid_A	406276418	879045	0	0
GrantKnown_A	406276418	406152952	0	0
IdxKnown_A	406276418	406152952	0	0
IndexIsCorrect_A	406276418	879045	0	0
LockArbDecision_A	406276418	0	0	0
NoReadyValidNoGrant_A	406276418	339881482	0	0
ReadyAndValidImplyGrant_A	406276418	879045	0	0
ReqAndReadyImplyGrant_A	406276418	879045	0	0
ReqImpliesValid_A	406276418	11620273	0	0
ReqStaysHighUntilGranted0_M	406276418	0	0	0
RoundRobin_A	406276418	28289	0	900
ValidKnown_A	406276418	406152952	0	0
gen_data_port_assertion.DataFlow_A	406276418	879045	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	879045	0	0
T1	10303	58	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	538	0	0
T8	248519	3543	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	879045	0	0
T1	10303	58	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	538	0	0
T8	248519	3543	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	879045	0	0
T1	10303	58	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	538	0	0
T8	248519	3543	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	339881482	0	0
T1	10303	8953	0	0
T2	68261	1	0	0
T3	42412	1	0	0
T7	52986	44475	0	0
T8	248519	197256	0	0
T9	24130	1	0	0
T10	2046	1	0	0
T11	6258	1	0	0
T12	145065	1	0	0
T13	5427	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	879045	0	0
T1	10303	58	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	538	0	0
T8	248519	3543	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	879045	0	0
T1	10303	58	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	538	0	0
T8	248519	3543	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	11620273	0	0
T1	10303	486	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	4215	0	0
T8	248519	32169	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	28289	0	900
T2	68261	243	0	1
T3	42412	54	0	1
T7	52986	0	0	1
T8	248519	21	0	1
T9	24130	191	0	1
T10	2046	0	0	1
T11	6258	2	0	1
T12	145065	796	0	1
T13	5427	3	0	1
T14	312986	21	0	1
T15	0	88	0	0
T16	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	406152952	0	0
T1	10303	10293	0	0
T2	68261	68081	0	0
T3	42412	42390	0	0
T7	52986	52969	0	0
T8	248519	248294	0	0
T9	24130	23790	0	0
T10	2046	2037	0	0
T11	6258	6189	0	0
T12	145065	145003	0	0
T13	5427	5409	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406276418	879045	0	0
T1	10303	58	0	0
T2	68261	4818	0	0
T3	42412	2999	0	0
T7	52986	538	0	0
T8	248519	3543	0	0
T9	24130	2535	0	0
T10	2046	47	0	0
T11	6258	232	0	0
T12	145065	8660	0	0
T13	5427	271	0	0