Line Coverage for Module :
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Line Coverage for Module :
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Module :
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T10 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T10 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T5,T10 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T5,T10 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
tlul_socket_m1
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
24662122 |
0 |
0 |
T1 |
10603344 |
108947 |
0 |
0 |
T2 |
2212584 |
47620 |
0 |
0 |
T3 |
7396920 |
13192 |
0 |
0 |
T4 |
169344 |
1191 |
0 |
0 |
T5 |
16543488 |
27175 |
0 |
0 |
T7 |
56808 |
714 |
0 |
0 |
T8 |
115992 |
792 |
0 |
0 |
T9 |
7970616 |
321092 |
0 |
0 |
T10 |
1638240 |
32670 |
0 |
0 |
T11 |
295632 |
5965 |
0 |
0 |
T12 |
0 |
166 |
0 |
0 |
T13 |
0 |
17239 |
0 |
0 |
T14 |
0 |
780 |
0 |
0 |
T15 |
0 |
731 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13465458 |
0 |
0 |
T1 |
10603344 |
84735 |
0 |
0 |
T2 |
2212584 |
46389 |
0 |
0 |
T3 |
7396920 |
9542 |
0 |
0 |
T4 |
169344 |
606 |
0 |
0 |
T5 |
16543488 |
21029 |
0 |
0 |
T7 |
56808 |
371 |
0 |
0 |
T8 |
115992 |
326 |
0 |
0 |
T9 |
7970616 |
130205 |
0 |
0 |
T10 |
1638240 |
35432 |
0 |
0 |
T11 |
295632 |
3035 |
0 |
0 |
T12 |
0 |
176 |
0 |
0 |
T13 |
0 |
23864 |
0 |
0 |
T14 |
0 |
949 |
0 |
0 |
T15 |
0 |
2005 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1708226724 |
3902899 |
0 |
0 |
T1 |
1767224 |
10160 |
0 |
0 |
T2 |
368764 |
9375 |
0 |
0 |
T3 |
1232820 |
1871 |
0 |
0 |
T4 |
28224 |
242 |
0 |
0 |
T5 |
2757248 |
7341 |
0 |
0 |
T7 |
9468 |
53 |
0 |
0 |
T8 |
19332 |
75 |
0 |
0 |
T9 |
1328436 |
65227 |
0 |
0 |
T10 |
273040 |
4492 |
0 |
0 |
T11 |
49272 |
457 |
0 |
0 |
T12 |
0 |
21 |
0 |
0 |
T13 |
0 |
6371 |
0 |
0 |
T14 |
0 |
254 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21600 |
21600 |
0 |
0 |
T1 |
24 |
24 |
0 |
0 |
T2 |
24 |
24 |
0 |
0 |
T3 |
24 |
24 |
0 |
0 |
T4 |
24 |
24 |
0 |
0 |
T5 |
24 |
24 |
0 |
0 |
T7 |
24 |
24 |
0 |
0 |
T8 |
24 |
24 |
0 |
0 |
T9 |
24 |
24 |
0 |
0 |
T10 |
24 |
24 |
0 |
0 |
T11 |
24 |
24 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
170819903 |
0 |
0 |
T1 |
10603344 |
86109 |
0 |
0 |
T2 |
2212584 |
33430 |
0 |
0 |
T3 |
7396920 |
1269427 |
0 |
0 |
T4 |
169344 |
1634 |
0 |
0 |
T5 |
16543488 |
2459747 |
0 |
0 |
T7 |
56808 |
992 |
0 |
0 |
T8 |
115992 |
1629 |
0 |
0 |
T9 |
7970616 |
1039189 |
0 |
0 |
T10 |
1638240 |
28722 |
0 |
0 |
T11 |
295632 |
8162 |
0 |
0 |
T12 |
0 |
287 |
0 |
0 |
T13 |
0 |
69556 |
0 |
0 |
T14 |
0 |
5279 |
0 |
0 |
T15 |
0 |
105551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_28
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_28
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T9,T13 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_28
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
1747709 |
0 |
0 |
T1 |
441806 |
4588 |
0 |
0 |
T2 |
92191 |
1183 |
0 |
0 |
T3 |
308205 |
745 |
0 |
0 |
T4 |
7056 |
60 |
0 |
0 |
T5 |
689312 |
2160 |
0 |
0 |
T7 |
2367 |
86 |
0 |
0 |
T8 |
4833 |
48 |
0 |
0 |
T9 |
332109 |
15471 |
0 |
0 |
T10 |
68260 |
632 |
0 |
0 |
T11 |
12318 |
719 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
421083 |
0 |
0 |
T1 |
441806 |
341 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
41 |
0 |
0 |
T5 |
689312 |
968 |
0 |
0 |
T7 |
2367 |
13 |
0 |
0 |
T8 |
4833 |
7 |
0 |
0 |
T9 |
332109 |
757 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
123 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
440 |
0 |
0 |
T14 |
0 |
63 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
540850 |
0 |
0 |
T1 |
441806 |
462 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
16 |
0 |
0 |
T5 |
689312 |
1064 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
10 |
0 |
0 |
T9 |
332109 |
3355 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
96 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
582 |
0 |
0 |
T14 |
0 |
88 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
20596606 |
0 |
0 |
T1 |
441806 |
9624 |
0 |
0 |
T2 |
92191 |
1966 |
0 |
0 |
T3 |
308205 |
742 |
0 |
0 |
T4 |
7056 |
147 |
0 |
0 |
T5 |
689312 |
147598 |
0 |
0 |
T7 |
2367 |
111 |
0 |
0 |
T8 |
4833 |
134 |
0 |
0 |
T9 |
332109 |
225866 |
0 |
0 |
T10 |
68260 |
1043 |
0 |
0 |
T11 |
12318 |
923 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_29
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_29
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T9 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_29
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
1935802 |
0 |
0 |
T1 |
441806 |
10460 |
0 |
0 |
T2 |
92191 |
2851 |
0 |
0 |
T3 |
308205 |
965 |
0 |
0 |
T4 |
7056 |
153 |
0 |
0 |
T5 |
689312 |
1221 |
0 |
0 |
T7 |
2367 |
99 |
0 |
0 |
T8 |
4833 |
64 |
0 |
0 |
T9 |
332109 |
20630 |
0 |
0 |
T10 |
68260 |
598 |
0 |
0 |
T11 |
12318 |
996 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
509590 |
0 |
0 |
T1 |
441806 |
4112 |
0 |
0 |
T2 |
92191 |
1505 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
13 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
10 |
0 |
0 |
T8 |
4833 |
0 |
0 |
0 |
T9 |
332109 |
5388 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
148 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
474 |
0 |
0 |
T14 |
0 |
81 |
0 |
0 |
T15 |
0 |
1141 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
645332 |
0 |
0 |
T1 |
441806 |
5797 |
0 |
0 |
T2 |
92191 |
1789 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
35 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
5 |
0 |
0 |
T9 |
332109 |
5090 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
114 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
566 |
0 |
0 |
T14 |
0 |
74 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
20282400 |
0 |
0 |
T1 |
441806 |
11865 |
0 |
0 |
T2 |
92191 |
5314 |
0 |
0 |
T3 |
308205 |
3390 |
0 |
0 |
T4 |
7056 |
176 |
0 |
0 |
T5 |
689312 |
1173 |
0 |
0 |
T7 |
2367 |
100 |
0 |
0 |
T8 |
4833 |
83 |
0 |
0 |
T9 |
332109 |
224085 |
0 |
0 |
T10 |
68260 |
961 |
0 |
0 |
T11 |
12318 |
943 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_31
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_31
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T5,T13 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_31
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
1944287 |
0 |
0 |
T1 |
441806 |
5869 |
0 |
0 |
T2 |
92191 |
1286 |
0 |
0 |
T3 |
308205 |
734 |
0 |
0 |
T4 |
7056 |
75 |
0 |
0 |
T5 |
689312 |
2326 |
0 |
0 |
T7 |
2367 |
102 |
0 |
0 |
T8 |
4833 |
47 |
0 |
0 |
T9 |
332109 |
28878 |
0 |
0 |
T10 |
68260 |
657 |
0 |
0 |
T11 |
12318 |
980 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
489885 |
0 |
0 |
T1 |
441806 |
1489 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
37 |
0 |
0 |
T5 |
689312 |
1219 |
0 |
0 |
T7 |
2367 |
17 |
0 |
0 |
T8 |
4833 |
9 |
0 |
0 |
T9 |
332109 |
4486 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
186 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T13 |
0 |
1770 |
0 |
0 |
T14 |
0 |
130 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
629114 |
0 |
0 |
T1 |
441806 |
1967 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
12 |
0 |
0 |
T5 |
689312 |
1266 |
0 |
0 |
T7 |
2367 |
14 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
5614 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
138 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
5223 |
0 |
0 |
T14 |
0 |
92 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
21170019 |
0 |
0 |
T1 |
441806 |
12166 |
0 |
0 |
T2 |
92191 |
1803 |
0 |
0 |
T3 |
308205 |
1603 |
0 |
0 |
T4 |
7056 |
208 |
0 |
0 |
T5 |
689312 |
185054 |
0 |
0 |
T7 |
2367 |
116 |
0 |
0 |
T8 |
4833 |
150 |
0 |
0 |
T9 |
332109 |
236999 |
0 |
0 |
T10 |
68260 |
893 |
0 |
0 |
T11 |
12318 |
978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_33
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_33
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_33
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
322145 |
0 |
0 |
T1 |
441806 |
2998 |
0 |
0 |
T2 |
92191 |
2875 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
10 |
0 |
0 |
T5 |
689312 |
1559 |
0 |
0 |
T7 |
2367 |
11 |
0 |
0 |
T8 |
4833 |
6 |
0 |
0 |
T9 |
332109 |
102 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
123 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
0 |
382 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
431381 |
0 |
0 |
T1 |
441806 |
3511 |
0 |
0 |
T2 |
92191 |
3764 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
38 |
0 |
0 |
T5 |
689312 |
1770 |
0 |
0 |
T7 |
2367 |
17 |
0 |
0 |
T8 |
4833 |
4 |
0 |
0 |
T9 |
332109 |
2082 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
126 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
390 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
3720796 |
0 |
0 |
T1 |
441806 |
3131 |
0 |
0 |
T2 |
92191 |
1451 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
44 |
0 |
0 |
T5 |
689312 |
220333 |
0 |
0 |
T7 |
2367 |
28 |
0 |
0 |
T8 |
4833 |
52 |
0 |
0 |
T9 |
332109 |
6041 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
240 |
0 |
0 |
T12 |
0 |
19 |
0 |
0 |
T13 |
0 |
3116 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_34
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_34
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_34
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
303105 |
0 |
0 |
T1 |
441806 |
838 |
0 |
0 |
T2 |
92191 |
9714 |
0 |
0 |
T3 |
308205 |
693 |
0 |
0 |
T4 |
7056 |
4 |
0 |
0 |
T5 |
689312 |
741 |
0 |
0 |
T7 |
2367 |
24 |
0 |
0 |
T8 |
4833 |
22 |
0 |
0 |
T9 |
332109 |
1508 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
120 |
0 |
0 |
T12 |
0 |
13 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
406992 |
0 |
0 |
T1 |
441806 |
1002 |
0 |
0 |
T2 |
92191 |
12693 |
0 |
0 |
T3 |
308205 |
733 |
0 |
0 |
T4 |
7056 |
14 |
0 |
0 |
T5 |
689312 |
801 |
0 |
0 |
T7 |
2367 |
20 |
0 |
0 |
T8 |
4833 |
19 |
0 |
0 |
T9 |
332109 |
3240 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
99 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
3833883 |
0 |
0 |
T1 |
441806 |
1724 |
0 |
0 |
T2 |
92191 |
4164 |
0 |
0 |
T3 |
308205 |
117908 |
0 |
0 |
T4 |
7056 |
24 |
0 |
0 |
T5 |
689312 |
92034 |
0 |
0 |
T7 |
2367 |
41 |
0 |
0 |
T8 |
4833 |
109 |
0 |
0 |
T9 |
332109 |
5983 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
207 |
0 |
0 |
T12 |
0 |
23 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_36
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_36
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T8,T9 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_36
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
743473 |
0 |
0 |
T1 |
441806 |
540 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
872 |
0 |
0 |
T4 |
7056 |
25 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
28 |
0 |
0 |
T8 |
4833 |
5 |
0 |
0 |
T9 |
332109 |
1243 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
176 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T13 |
0 |
615 |
0 |
0 |
T14 |
0 |
97 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
910570 |
0 |
0 |
T1 |
441806 |
361 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
1000 |
0 |
0 |
T4 |
7056 |
28 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
29 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
2225 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
173 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T13 |
0 |
792 |
0 |
0 |
T14 |
0 |
54 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4342761 |
0 |
0 |
T1 |
441806 |
754 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
117868 |
0 |
0 |
T4 |
7056 |
64 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
25 |
0 |
0 |
T8 |
4833 |
43 |
0 |
0 |
T9 |
332109 |
6131 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
242 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
2525 |
0 |
0 |
T14 |
0 |
613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_38
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_38
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T9 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_38
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
714712 |
0 |
0 |
T1 |
441806 |
6278 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
1172 |
0 |
0 |
T4 |
7056 |
28 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
23 |
0 |
0 |
T8 |
4833 |
2 |
0 |
0 |
T9 |
332109 |
520 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
154 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
2671 |
0 |
0 |
T14 |
0 |
69 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
817639 |
0 |
0 |
T1 |
441806 |
5583 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
1390 |
0 |
0 |
T4 |
7056 |
36 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
16 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
1718 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
175 |
0 |
0 |
T12 |
0 |
22 |
0 |
0 |
T13 |
0 |
3471 |
0 |
0 |
T14 |
0 |
65 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4273131 |
0 |
0 |
T1 |
441806 |
1575 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
126780 |
0 |
0 |
T4 |
7056 |
36 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
26 |
0 |
0 |
T8 |
4833 |
10 |
0 |
0 |
T9 |
332109 |
8734 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
223 |
0 |
0 |
T12 |
0 |
18 |
0 |
0 |
T13 |
0 |
5329 |
0 |
0 |
T14 |
0 |
531 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_40
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_40
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T13,T14 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_40
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
747208 |
0 |
0 |
T1 |
441806 |
14256 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
42 |
0 |
0 |
T5 |
689312 |
1240 |
0 |
0 |
T7 |
2367 |
39 |
0 |
0 |
T8 |
4833 |
4 |
0 |
0 |
T9 |
332109 |
21238 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
129 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
347 |
0 |
0 |
T14 |
0 |
71 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
887909 |
0 |
0 |
T1 |
441806 |
14684 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
66 |
0 |
0 |
T5 |
689312 |
1509 |
0 |
0 |
T7 |
2367 |
36 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
31102 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
98 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
407 |
0 |
0 |
T14 |
0 |
73 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4414549 |
0 |
0 |
T1 |
441806 |
1353 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
30 |
0 |
0 |
T5 |
689312 |
89389 |
0 |
0 |
T7 |
2367 |
38 |
0 |
0 |
T8 |
4833 |
40 |
0 |
0 |
T9 |
332109 |
2522 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
184 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
2831 |
0 |
0 |
T14 |
0 |
518 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_42
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_42
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_42
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
629123 |
0 |
0 |
T1 |
441806 |
13463 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
9 |
0 |
0 |
T5 |
689312 |
1459 |
0 |
0 |
T7 |
2367 |
11 |
0 |
0 |
T8 |
4833 |
0 |
0 |
0 |
T9 |
332109 |
4328 |
0 |
0 |
T10 |
68260 |
4095 |
0 |
0 |
T11 |
12318 |
154 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
0 |
381 |
0 |
0 |
T14 |
0 |
83 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
757491 |
0 |
0 |
T1 |
441806 |
14168 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
24 |
0 |
0 |
T5 |
689312 |
1593 |
0 |
0 |
T7 |
2367 |
19 |
0 |
0 |
T8 |
4833 |
6 |
0 |
0 |
T9 |
332109 |
6829 |
0 |
0 |
T10 |
68260 |
5745 |
0 |
0 |
T11 |
12318 |
200 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
455 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4568174 |
0 |
0 |
T1 |
441806 |
5233 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
35 |
0 |
0 |
T5 |
689312 |
109246 |
0 |
0 |
T7 |
2367 |
24 |
0 |
0 |
T8 |
4833 |
7 |
0 |
0 |
T9 |
332109 |
1334 |
0 |
0 |
T10 |
68260 |
2337 |
0 |
0 |
T11 |
12318 |
225 |
0 |
0 |
T12 |
0 |
21 |
0 |
0 |
T13 |
0 |
2949 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_43
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T9 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_43
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
332297 |
0 |
0 |
T1 |
441806 |
2008 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
28 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
9 |
0 |
0 |
T8 |
4833 |
2 |
0 |
0 |
T9 |
332109 |
2621 |
0 |
0 |
T10 |
68260 |
2968 |
0 |
0 |
T11 |
12318 |
105 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T13 |
0 |
1235 |
0 |
0 |
T14 |
0 |
63 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
441585 |
0 |
0 |
T1 |
441806 |
3814 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
14 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
13 |
0 |
0 |
T8 |
4833 |
6 |
0 |
0 |
T9 |
332109 |
3966 |
0 |
0 |
T10 |
68260 |
3971 |
0 |
0 |
T11 |
12318 |
127 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T13 |
0 |
858 |
0 |
0 |
T14 |
0 |
53 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4094434 |
0 |
0 |
T1 |
441806 |
2521 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
61 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
22 |
0 |
0 |
T8 |
4833 |
10 |
0 |
0 |
T9 |
332109 |
7135 |
0 |
0 |
T10 |
68260 |
1799 |
0 |
0 |
T11 |
12318 |
221 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
0 |
5625 |
0 |
0 |
T14 |
0 |
507 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_44
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_44
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
318069 |
0 |
0 |
T1 |
441806 |
4316 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
683 |
0 |
0 |
T4 |
7056 |
14 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
16 |
0 |
0 |
T8 |
4833 |
2 |
0 |
0 |
T9 |
332109 |
431 |
0 |
0 |
T10 |
68260 |
3917 |
0 |
0 |
T11 |
12318 |
130 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T13 |
0 |
321 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
428833 |
0 |
0 |
T1 |
441806 |
5716 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
840 |
0 |
0 |
T4 |
7056 |
20 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
14 |
0 |
0 |
T8 |
4833 |
5 |
0 |
0 |
T9 |
332109 |
4429 |
0 |
0 |
T10 |
68260 |
5303 |
0 |
0 |
T11 |
12318 |
114 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
512 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4672384 |
0 |
0 |
T1 |
441806 |
2125 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
127753 |
0 |
0 |
T4 |
7056 |
53 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
24 |
0 |
0 |
T8 |
4833 |
15 |
0 |
0 |
T9 |
332109 |
7296 |
0 |
0 |
T10 |
68260 |
2466 |
0 |
0 |
T11 |
12318 |
223 |
0 |
0 |
T12 |
0 |
19 |
0 |
0 |
T13 |
0 |
2613 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_45
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_45
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
301599 |
0 |
0 |
T1 |
441806 |
2206 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
775 |
0 |
0 |
T4 |
7056 |
17 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
9 |
0 |
0 |
T8 |
4833 |
7 |
0 |
0 |
T9 |
332109 |
1829 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
133 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
413 |
0 |
0 |
T14 |
0 |
81 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
397076 |
0 |
0 |
T1 |
441806 |
3559 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
894 |
0 |
0 |
T4 |
7056 |
12 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
6 |
0 |
0 |
T9 |
332109 |
1500 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
113 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
424 |
0 |
0 |
T14 |
0 |
56 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4798885 |
0 |
0 |
T1 |
441806 |
3626 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
123479 |
0 |
0 |
T4 |
7056 |
44 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
21 |
0 |
0 |
T8 |
4833 |
73 |
0 |
0 |
T9 |
332109 |
11013 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
231 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
0 |
2958 |
0 |
0 |
T14 |
0 |
630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_46
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T9,T13 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_46
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
288082 |
0 |
0 |
T1 |
441806 |
291 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
12 |
0 |
0 |
T5 |
689312 |
791 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
25 |
0 |
0 |
T9 |
332109 |
1725 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
126 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
1806 |
0 |
0 |
T14 |
0 |
56 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
395347 |
0 |
0 |
T1 |
441806 |
367 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
3 |
0 |
0 |
T5 |
689312 |
812 |
0 |
0 |
T7 |
2367 |
8 |
0 |
0 |
T8 |
4833 |
50 |
0 |
0 |
T9 |
332109 |
2700 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
105 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
1707 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4163221 |
0 |
0 |
T1 |
441806 |
842 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
45 |
0 |
0 |
T5 |
689312 |
103592 |
0 |
0 |
T7 |
2367 |
19 |
0 |
0 |
T8 |
4833 |
154 |
0 |
0 |
T9 |
332109 |
7201 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
220 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
0 |
8139 |
0 |
0 |
T14 |
0 |
526 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_47
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_47
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
316653 |
0 |
0 |
T1 |
441806 |
255 |
0 |
0 |
T2 |
92191 |
3803 |
0 |
0 |
T3 |
308205 |
573 |
0 |
0 |
T4 |
7056 |
8 |
0 |
0 |
T5 |
689312 |
716 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
6 |
0 |
0 |
T9 |
332109 |
1300 |
0 |
0 |
T10 |
68260 |
3689 |
0 |
0 |
T11 |
12318 |
111 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
405946 |
0 |
0 |
T1 |
441806 |
280 |
0 |
0 |
T2 |
92191 |
4093 |
0 |
0 |
T3 |
308205 |
706 |
0 |
0 |
T4 |
7056 |
10 |
0 |
0 |
T5 |
689312 |
844 |
0 |
0 |
T7 |
2367 |
13 |
0 |
0 |
T8 |
4833 |
7 |
0 |
0 |
T9 |
332109 |
2557 |
0 |
0 |
T10 |
68260 |
4902 |
0 |
0 |
T11 |
12318 |
121 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4299765 |
0 |
0 |
T1 |
441806 |
918 |
0 |
0 |
T2 |
92191 |
6821 |
0 |
0 |
T3 |
308205 |
119465 |
0 |
0 |
T4 |
7056 |
37 |
0 |
0 |
T5 |
689312 |
91798 |
0 |
0 |
T7 |
2367 |
24 |
0 |
0 |
T8 |
4833 |
49 |
0 |
0 |
T9 |
332109 |
4907 |
0 |
0 |
T10 |
68260 |
2741 |
0 |
0 |
T11 |
12318 |
220 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_48
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_48
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
321775 |
0 |
0 |
T1 |
441806 |
3916 |
0 |
0 |
T2 |
92191 |
3249 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
12 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
12 |
0 |
0 |
T9 |
332109 |
871 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
118 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
1435 |
0 |
0 |
T14 |
0 |
80 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
421834 |
0 |
0 |
T1 |
441806 |
5093 |
0 |
0 |
T2 |
92191 |
4250 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
36 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
14 |
0 |
0 |
T8 |
4833 |
11 |
0 |
0 |
T9 |
332109 |
697 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
131 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
1147 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4393691 |
0 |
0 |
T1 |
441806 |
2130 |
0 |
0 |
T2 |
92191 |
1294 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
61 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
26 |
0 |
0 |
T8 |
4833 |
23 |
0 |
0 |
T9 |
332109 |
6241 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
241 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T13 |
0 |
5190 |
0 |
0 |
T14 |
0 |
479 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_49
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_49
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
301426 |
0 |
0 |
T1 |
441806 |
3581 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
656 |
0 |
0 |
T4 |
7056 |
11 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
15 |
0 |
0 |
T8 |
4833 |
5 |
0 |
0 |
T9 |
332109 |
556 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
101 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
340 |
0 |
0 |
T14 |
0 |
45 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
398651 |
0 |
0 |
T1 |
441806 |
4269 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
812 |
0 |
0 |
T4 |
7056 |
34 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
20 |
0 |
0 |
T8 |
4833 |
16 |
0 |
0 |
T9 |
332109 |
3444 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
111 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
410 |
0 |
0 |
T14 |
0 |
53 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4115224 |
0 |
0 |
T1 |
441806 |
2265 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
99193 |
0 |
0 |
T4 |
7056 |
33 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
34 |
0 |
0 |
T8 |
4833 |
32 |
0 |
0 |
T9 |
332109 |
4345 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
202 |
0 |
0 |
T12 |
0 |
15 |
0 |
0 |
T13 |
0 |
2868 |
0 |
0 |
T14 |
0 |
383 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_50
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_50
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
343983 |
0 |
0 |
T1 |
441806 |
257 |
0 |
0 |
T2 |
92191 |
5855 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
19 |
0 |
0 |
T5 |
689312 |
1583 |
0 |
0 |
T7 |
2367 |
24 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
1168 |
0 |
0 |
T10 |
68260 |
2978 |
0 |
0 |
T11 |
12318 |
112 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
458711 |
0 |
0 |
T1 |
441806 |
328 |
0 |
0 |
T2 |
92191 |
7230 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
14 |
0 |
0 |
T5 |
689312 |
1731 |
0 |
0 |
T7 |
2367 |
14 |
0 |
0 |
T8 |
4833 |
2 |
0 |
0 |
T9 |
332109 |
4851 |
0 |
0 |
T10 |
68260 |
3827 |
0 |
0 |
T11 |
12318 |
107 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4431730 |
0 |
0 |
T1 |
441806 |
920 |
0 |
0 |
T2 |
92191 |
2773 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
48 |
0 |
0 |
T5 |
689312 |
234301 |
0 |
0 |
T7 |
2367 |
35 |
0 |
0 |
T8 |
4833 |
28 |
0 |
0 |
T9 |
332109 |
8235 |
0 |
0 |
T10 |
68260 |
2055 |
0 |
0 |
T11 |
12318 |
204 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_51
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_51
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
315580 |
0 |
0 |
T1 |
441806 |
5794 |
0 |
0 |
T2 |
92191 |
3461 |
0 |
0 |
T3 |
308205 |
759 |
0 |
0 |
T4 |
7056 |
35 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
25 |
0 |
0 |
T8 |
4833 |
7 |
0 |
0 |
T9 |
332109 |
887 |
0 |
0 |
T10 |
68260 |
2981 |
0 |
0 |
T11 |
12318 |
104 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
422709 |
0 |
0 |
T1 |
441806 |
9693 |
0 |
0 |
T2 |
92191 |
4614 |
0 |
0 |
T3 |
308205 |
883 |
0 |
0 |
T4 |
7056 |
15 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
21 |
0 |
0 |
T8 |
4833 |
4 |
0 |
0 |
T9 |
332109 |
2245 |
0 |
0 |
T10 |
68260 |
3626 |
0 |
0 |
T11 |
12318 |
114 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4242873 |
0 |
0 |
T1 |
441806 |
4952 |
0 |
0 |
T2 |
92191 |
1428 |
0 |
0 |
T3 |
308205 |
123117 |
0 |
0 |
T4 |
7056 |
37 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
44 |
0 |
0 |
T8 |
4833 |
58 |
0 |
0 |
T9 |
332109 |
8861 |
0 |
0 |
T10 |
68260 |
2414 |
0 |
0 |
T11 |
12318 |
212 |
0 |
0 |
T12 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_52
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T13 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_52
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
304984 |
0 |
0 |
T1 |
441806 |
266 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
9 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
13 |
0 |
0 |
T8 |
4833 |
2 |
0 |
0 |
T9 |
332109 |
1634 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
140 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
1564 |
0 |
0 |
T14 |
0 |
71 |
0 |
0 |
T15 |
0 |
731 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
408955 |
0 |
0 |
T1 |
441806 |
298 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
13 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
24 |
0 |
0 |
T9 |
332109 |
3576 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
105 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T13 |
0 |
1844 |
0 |
0 |
T14 |
0 |
72 |
0 |
0 |
T15 |
0 |
864 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4452052 |
0 |
0 |
T1 |
441806 |
1006 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
34 |
0 |
0 |
T5 |
689312 |
0 |
0 |
0 |
T7 |
2367 |
25 |
0 |
0 |
T8 |
4833 |
19 |
0 |
0 |
T9 |
332109 |
6361 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
227 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
0 |
5587 |
0 |
0 |
T14 |
0 |
586 |
0 |
0 |
T15 |
0 |
105551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_53
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T5 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_53
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
320822 |
0 |
0 |
T1 |
441806 |
790 |
0 |
0 |
T2 |
92191 |
1410 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
10 |
0 |
0 |
T5 |
689312 |
1333 |
0 |
0 |
T7 |
2367 |
14 |
0 |
0 |
T8 |
4833 |
83 |
0 |
0 |
T9 |
332109 |
1206 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
125 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
1203 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
411997 |
0 |
0 |
T1 |
441806 |
1419 |
0 |
0 |
T2 |
92191 |
1726 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
5 |
0 |
0 |
T5 |
689312 |
1598 |
0 |
0 |
T7 |
2367 |
9 |
0 |
0 |
T8 |
4833 |
82 |
0 |
0 |
T9 |
332109 |
3139 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
105 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
1443 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4620207 |
0 |
0 |
T1 |
441806 |
1794 |
0 |
0 |
T2 |
92191 |
1902 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
14 |
0 |
0 |
T5 |
689312 |
206025 |
0 |
0 |
T7 |
2367 |
23 |
0 |
0 |
T8 |
4833 |
278 |
0 |
0 |
T9 |
332109 |
4490 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
208 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T13 |
0 |
5466 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_54
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_sm1_54
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
299639 |
0 |
0 |
T1 |
441806 |
272 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
704 |
0 |
0 |
T4 |
7056 |
22 |
0 |
0 |
T5 |
689312 |
777 |
0 |
0 |
T7 |
2367 |
16 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
3448 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
125 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
368 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
388818 |
0 |
0 |
T1 |
441806 |
334 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
890 |
0 |
0 |
T4 |
7056 |
26 |
0 |
0 |
T5 |
689312 |
894 |
0 |
0 |
T7 |
2367 |
8 |
0 |
0 |
T8 |
4833 |
7 |
0 |
0 |
T9 |
332109 |
2022 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
112 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
559 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4375566 |
0 |
0 |
T1 |
441806 |
898 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
144032 |
0 |
0 |
T4 |
7056 |
41 |
0 |
0 |
T5 |
689312 |
88326 |
0 |
0 |
T7 |
2367 |
22 |
0 |
0 |
T8 |
4833 |
22 |
0 |
0 |
T9 |
332109 |
4427 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
218 |
0 |
0 |
T12 |
0 |
19 |
0 |
0 |
T13 |
0 |
3197 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_55
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_55
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
321269 |
0 |
0 |
T1 |
441806 |
1232 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
13 |
0 |
0 |
T5 |
689312 |
629 |
0 |
0 |
T7 |
2367 |
9 |
0 |
0 |
T8 |
4833 |
5 |
0 |
0 |
T9 |
332109 |
398 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
121 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
2966 |
0 |
0 |
T14 |
0 |
64 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
419814 |
0 |
0 |
T1 |
441806 |
2057 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
18 |
0 |
0 |
T5 |
689312 |
775 |
0 |
0 |
T7 |
2367 |
15 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
2393 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
131 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
3886 |
0 |
0 |
T14 |
0 |
79 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
3963055 |
0 |
0 |
T1 |
441806 |
1768 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
26 |
0 |
0 |
T5 |
689312 |
100277 |
0 |
0 |
T7 |
2367 |
24 |
0 |
0 |
T8 |
4833 |
29 |
0 |
0 |
T9 |
332109 |
5414 |
0 |
0 |
T10 |
68260 |
0 |
0 |
0 |
T11 |
12318 |
232 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
5389 |
0 |
0 |
T14 |
0 |
506 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_56
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T7 |
1 | 1 | Covered | T1,T4,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T8 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Covered | T1,T4,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_56
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
340389 |
0 |
0 |
T1 |
441806 |
287 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
14 |
0 |
0 |
T5 |
689312 |
1668 |
0 |
0 |
T7 |
2367 |
9 |
0 |
0 |
T8 |
4833 |
3 |
0 |
0 |
T9 |
332109 |
944 |
0 |
0 |
T10 |
68260 |
3050 |
0 |
0 |
T11 |
12318 |
143 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
1192 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
430958 |
0 |
0 |
T1 |
441806 |
299 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
13 |
0 |
0 |
T5 |
689312 |
1774 |
0 |
0 |
T7 |
2367 |
9 |
0 |
0 |
T8 |
4833 |
11 |
0 |
0 |
T9 |
332109 |
4371 |
0 |
0 |
T10 |
68260 |
3696 |
0 |
0 |
T11 |
12318 |
92 |
0 |
0 |
T12 |
0 |
9 |
0 |
0 |
T13 |
0 |
2875 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
4184755 |
0 |
0 |
T1 |
441806 |
940 |
0 |
0 |
T2 |
92191 |
0 |
0 |
0 |
T3 |
308205 |
0 |
0 |
0 |
T4 |
7056 |
38 |
0 |
0 |
T5 |
689312 |
209342 |
0 |
0 |
T7 |
2367 |
18 |
0 |
0 |
T8 |
4833 |
27 |
0 |
0 |
T9 |
332109 |
5929 |
0 |
0 |
T10 |
68260 |
2512 |
0 |
0 |
T11 |
12318 |
215 |
0 |
0 |
T12 |
0 |
16 |
0 |
0 |
T13 |
0 |
5774 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_30
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_30
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T10 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T10 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T10 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T5,T10 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T5,T10 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T5,T10 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_30
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
11147991 |
0 |
0 |
T1 |
441806 |
24186 |
0 |
0 |
T2 |
92191 |
11933 |
0 |
0 |
T3 |
308205 |
3861 |
0 |
0 |
T4 |
7056 |
561 |
0 |
0 |
T5 |
689312 |
8972 |
0 |
0 |
T7 |
2367 |
96 |
0 |
0 |
T8 |
4833 |
429 |
0 |
0 |
T9 |
332109 |
208156 |
0 |
0 |
T10 |
68260 |
7105 |
0 |
0 |
T11 |
12318 |
720 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
2001684 |
0 |
0 |
T1 |
441806 |
1958 |
0 |
0 |
T2 |
92191 |
6514 |
0 |
0 |
T3 |
308205 |
1394 |
0 |
0 |
T4 |
7056 |
76 |
0 |
0 |
T5 |
689312 |
4741 |
0 |
0 |
T7 |
2367 |
12 |
0 |
0 |
T8 |
4833 |
38 |
0 |
0 |
T9 |
332109 |
30488 |
0 |
0 |
T10 |
68260 |
4362 |
0 |
0 |
T11 |
12318 |
119 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
2087603 |
0 |
0 |
T1 |
441806 |
1934 |
0 |
0 |
T2 |
92191 |
7586 |
0 |
0 |
T3 |
308205 |
1871 |
0 |
0 |
T4 |
7056 |
179 |
0 |
0 |
T5 |
689312 |
5011 |
0 |
0 |
T7 |
2367 |
15 |
0 |
0 |
T8 |
4833 |
57 |
0 |
0 |
T9 |
332109 |
51168 |
0 |
0 |
T10 |
68260 |
4492 |
0 |
0 |
T11 |
12318 |
109 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427056681 |
22809742 |
0 |
0 |
T1 |
441806 |
11979 |
0 |
0 |
T2 |
92191 |
4514 |
0 |
0 |
T3 |
308205 |
164097 |
0 |
0 |
T4 |
7056 |
298 |
0 |
0 |
T5 |
689312 |
581259 |
0 |
0 |
T7 |
2367 |
122 |
0 |
0 |
T8 |
4833 |
184 |
0 |
0 |
T9 |
332109 |
229639 |
0 |
0 |
T10 |
68260 |
9501 |
0 |
0 |
T11 |
12318 |
923 |
0 |
0 |