Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7983059	0	0
GntImpliesValid_A	2147483647	7983059	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7983059	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	473872290	0	0
ReadyAndValidImplyGrant_A	2147483647	7983059	0	0
ReqAndReadyImplyGrant_A	2147483647	7983059	0	0
ReqImpliesValid_A	2147483647	36708331	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	39084	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7983059	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10603344	10601064	0	0
T2	2212584	2212176	0	0
T3	7396920	7396848	0	0
T4	169344	168096	0	0
T5	16543488	16543344	0	0
T7	56808	56280	0	0
T8	115992	111840	0	0
T9	7970616	7970520	0	0
T10	1638240	1637688	0	0
T11	295632	295416	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7983059	0	0
T1	10603344	38687	0	0
T2	2212584	10472	0	0
T3	7396920	7668	0	0
T4	169344	802	0	0
T5	16543488	14708	0	0
T7	56808	992	0	0
T8	115992	506	0	0
T9	7970616	7553	0	0
T10	1638240	6582	0	0
T11	295632	8162	0	0
T12	0	287	0	0
T13	0	14446	0	0
T14	0	1110	0	0
T15	0	482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7983059	0	0
T1	10603344	38687	0	0
T2	2212584	10472	0	0
T3	7396920	7668	0	0
T4	169344	802	0	0
T5	16543488	14708	0	0
T7	56808	992	0	0
T8	115992	506	0	0
T9	7970616	7553	0	0
T10	1638240	6582	0	0
T11	295632	8162	0	0
T12	0	287	0	0
T13	0	14446	0	0
T14	0	1110	0	0
T15	0	482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10603344	10601064	0	0
T2	2212584	2212176	0	0
T3	7396920	7396848	0	0
T4	169344	168096	0	0
T5	16543488	16543344	0	0
T7	56808	56280	0	0
T8	115992	111840	0	0
T9	7970616	7970520	0	0
T10	1638240	1637688	0	0
T11	295632	295416	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10603344	10601064	0	0
T2	2212584	2212176	0	0
T3	7396920	7396848	0	0
T4	169344	168096	0	0
T5	16543488	16543344	0	0
T7	56808	56280	0	0
T8	115992	111840	0	0
T9	7970616	7970520	0	0
T10	1638240	1637688	0	0
T11	295632	295416	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7983059	0	0
T1	10603344	38687	0	0
T2	2212584	10472	0	0
T3	7396920	7668	0	0
T4	169344	802	0	0
T5	16543488	14708	0	0
T7	56808	992	0	0
T8	115992	506	0	0
T9	7970616	7553	0	0
T10	1638240	6582	0	0
T11	295632	8162	0	0
T12	0	287	0	0
T13	0	14446	0	0
T14	0	1110	0	0
T15	0	482	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	473872290	0	0
T1	10603344	652725	0	0
T2	2212584	97333	0	0
T3	7396920	281631	0	0
T4	169344	11105	0	0
T5	16543488	615718	0	0
T7	56808	1157	0	0
T8	115992	7029	0	0
T9	7970616	2802496	0	0
T10	1638240	59270	0	0
T11	295632	7650	0	0
T12	0	200	0	0
T13	0	28939	0	0
T14	0	3362	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7983059	0	0
T1	10603344	38687	0	0
T2	2212584	10472	0	0
T3	7396920	7668	0	0
T4	169344	802	0	0
T5	16543488	14708	0	0
T7	56808	992	0	0
T8	115992	506	0	0
T9	7970616	7553	0	0
T10	1638240	6582	0	0
T11	295632	8162	0	0
T12	0	287	0	0
T13	0	14446	0	0
T14	0	1110	0	0
T15	0	482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7983059	0	0
T1	10603344	38687	0	0
T2	2212584	10472	0	0
T3	7396920	7668	0	0
T4	169344	802	0	0
T5	16543488	14708	0	0
T7	56808	992	0	0
T8	115992	506	0	0
T9	7970616	7553	0	0
T10	1638240	6582	0	0
T11	295632	8162	0	0
T12	0	287	0	0
T13	0	14446	0	0
T14	0	1110	0	0
T15	0	482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36708331	0	0
T1	10603344	165697	0	0
T2	2212584	67009	0	0
T3	7396920	18884	0	0
T4	169344	1980	0	0
T5	16543488	40059	0	0
T7	56808	1130	0	0
T8	115992	1181	0	0
T9	7970616	503111	0	0
T10	1638240	48916	0	0
T11	295632	9283	0	0
T12	0	313	0	0
T13	0	33195	0	0
T14	0	1370	0	0
T15	0	1144	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39084	0	21600
T1	441806	1	0	1
T2	92191	21	0	1
T3	308205	12	0	1
T4	7056	0	0	1
T5	1378624	49	0	2
T7	4734	4	0	2
T8	9666	0	0	2
T9	664218	0	0	2
T10	136520	145	0	2
T11	24636	38	0	2
T12	2068	0	0	1
T13	327785	5	0	1
T14	58439	0	0	1
T15	339042	0	0	1
T16	0	12	0	0
T17	0	7	0	0
T18	0	1151	0	0
T19	0	4	0	0
T20	0	684	0	0
T21	0	17	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10603344	10601064	0	0
T2	2212584	2212176	0	0
T3	7396920	7396848	0	0
T4	169344	168096	0	0
T5	16543488	16543344	0	0
T7	56808	56280	0	0
T8	115992	111840	0	0
T9	7970616	7970520	0	0
T10	1638240	1637688	0	0
T11	295632	295416	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7983059	0	0
T1	10603344	38687	0	0
T2	2212584	10472	0	0
T3	7396920	7668	0	0
T4	169344	802	0	0
T5	16543488	14708	0	0
T7	56808	992	0	0
T8	115992	506	0	0
T9	7970616	7553	0	0
T10	1638240	6582	0	0
T11	295632	8162	0	0
T12	0	287	0	0
T13	0	14446	0	0
T14	0	1110	0	0
T15	0	482	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	887726	0	0
GntImpliesValid_A	427056681	887726	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	887726	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	13434583	0	0
ReadyAndValidImplyGrant_A	427056681	887726	0	0
ReqAndReadyImplyGrant_A	427056681	887726	0	0
ReqImpliesValid_A	427056681	2613434	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	887726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	887726	0	0
T1	441806	4975	0	0
T2	92191	1538	0	0
T3	308205	633	0	0
T4	7056	76	0	0
T5	689312	868	0	0
T7	2367	100	0	0
T8	4833	51	0	0
T9	332109	839	0	0
T10	68260	390	0	0
T11	12318	943	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	887726	0	0
T1	441806	4975	0	0
T2	92191	1538	0	0
T3	308205	633	0	0
T4	7056	76	0	0
T5	689312	868	0	0
T7	2367	100	0	0
T8	4833	51	0	0
T9	332109	839	0	0
T10	68260	390	0	0
T11	12318	943	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	887726	0	0
T1	441806	4975	0	0
T2	92191	1538	0	0
T3	308205	633	0	0
T4	7056	76	0	0
T5	689312	868	0	0
T7	2367	100	0	0
T8	4833	51	0	0
T9	332109	839	0	0
T10	68260	390	0	0
T11	12318	943	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	13434583	0	0
T1	441806	32195	0	0
T2	92191	6936	0	0
T3	308205	2527	0	0
T4	7056	546	0	0
T5	689312	3561	0	0
T7	2367	81	0	0
T8	4833	357	0	0
T9	332109	245608	0	0
T10	68260	2957	0	0
T11	12318	666	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	887726	0	0
T1	441806	4975	0	0
T2	92191	1538	0	0
T3	308205	633	0	0
T4	7056	76	0	0
T5	689312	868	0	0
T7	2367	100	0	0
T8	4833	51	0	0
T9	332109	839	0	0
T10	68260	390	0	0
T11	12318	943	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	887726	0	0
T1	441806	4975	0	0
T2	92191	1538	0	0
T3	308205	633	0	0
T4	7056	76	0	0
T5	689312	868	0	0
T7	2367	100	0	0
T8	4833	51	0	0
T9	332109	839	0	0
T10	68260	390	0	0
T11	12318	943	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	2613434	0	0
T1	441806	15717	0	0
T2	92191	4238	0	0
T3	308205	965	0	0
T4	7056	184	0	0
T5	689312	1221	0	0
T7	2367	120	0	0
T8	4833	69	0	0
T9	332109	29946	0	0
T10	68260	598	0	0
T11	12318	1221	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	887726	0	0
T1	441806	4975	0	0
T2	92191	1538	0	0
T3	308205	633	0	0
T4	7056	76	0	0
T5	689312	868	0	0
T7	2367	100	0	0
T8	4833	51	0	0
T9	332109	839	0	0
T10	68260	390	0	0
T11	12318	943	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	890095	0	0
GntImpliesValid_A	427056681	890095	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	890095	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	13551913	0	0
ReadyAndValidImplyGrant_A	427056681	890095	0	0
ReqAndReadyImplyGrant_A	427056681	890095	0	0
ReqImpliesValid_A	427056681	2615160	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	890095	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	890095	0	0
T1	441806	4866	0	0
T2	92191	791	0	0
T3	308205	538	0	0
T4	7056	75	0	0
T5	689312	1662	0	0
T7	2367	116	0	0
T8	4833	47	0	0
T9	332109	861	0	0
T10	68260	409	0	0
T11	12318	978	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	890095	0	0
T1	441806	4866	0	0
T2	92191	791	0	0
T3	308205	538	0	0
T4	7056	75	0	0
T5	689312	1662	0	0
T7	2367	116	0	0
T8	4833	47	0	0
T9	332109	861	0	0
T10	68260	409	0	0
T11	12318	978	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	890095	0	0
T1	441806	4866	0	0
T2	92191	791	0	0
T3	308205	538	0	0
T4	7056	75	0	0
T5	689312	1662	0	0
T7	2367	116	0	0
T8	4833	47	0	0
T9	332109	861	0	0
T10	68260	409	0	0
T11	12318	978	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	13551913	0	0
T1	441806	30217	0	0
T2	92191	5763	0	0
T3	308205	2135	0	0
T4	7056	519	0	0
T5	689312	6163	0	0
T7	2367	100	0	0
T8	4833	390	0	0
T9	332109	288846	0	0
T10	68260	2784	0	0
T11	12318	708	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	890095	0	0
T1	441806	4866	0	0
T2	92191	791	0	0
T3	308205	538	0	0
T4	7056	75	0	0
T5	689312	1662	0	0
T7	2367	116	0	0
T8	4833	47	0	0
T9	332109	861	0	0
T10	68260	409	0	0
T11	12318	978	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	890095	0	0
T1	441806	4866	0	0
T2	92191	791	0	0
T3	308205	538	0	0
T4	7056	75	0	0
T5	689312	1662	0	0
T7	2367	116	0	0
T8	4833	47	0	0
T9	332109	861	0	0
T10	68260	409	0	0
T11	12318	978	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	2615160	0	0
T1	441806	8966	0	0
T2	92191	1286	0	0
T3	308205	734	0	0
T4	7056	124	0	0
T5	689312	3047	0	0
T7	2367	133	0	0
T8	4833	59	0	0
T9	332109	37946	0	0
T10	68260	657	0	0
T11	12318	1249	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	890095	0	0
T1	441806	4866	0	0
T2	92191	791	0	0
T3	308205	538	0	0
T4	7056	75	0	0
T5	689312	1662	0	0
T7	2367	116	0	0
T8	4833	47	0	0
T9	332109	861	0	0
T10	68260	409	0	0
T11	12318	978	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	218692	0	0
GntImpliesValid_A	427056681	218692	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	218692	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3335534	0	0
ReadyAndValidImplyGrant_A	427056681	218692	0	0
ReqAndReadyImplyGrant_A	427056681	218692	0	0
ReqImpliesValid_A	427056681	627280	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	218692	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	218692	0	0
T1	441806	1589	0	0
T2	92191	455	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	1027	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	210	0	0
T10	68260	0	0	0
T11	12318	240	0	0
T12	0	19	0	0
T13	0	643	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	218692	0	0
T1	441806	1589	0	0
T2	92191	455	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	1027	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	210	0	0
T10	68260	0	0	0
T11	12318	240	0	0
T12	0	19	0	0
T13	0	643	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	218692	0	0
T1	441806	1589	0	0
T2	92191	455	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	1027	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	210	0	0
T10	68260	0	0	0
T11	12318	240	0	0
T12	0	19	0	0
T13	0	643	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3335534	0	0
T1	441806	9530	0	0
T2	92191	651	0	0
T3	308205	1	0	0
T4	7056	119	0	0
T5	689312	3435	0	0
T7	2367	29	0	0
T8	4833	85	0	0
T9	332109	65045	0	0
T10	68260	1	0	0
T11	12318	233	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	218692	0	0
T1	441806	1589	0	0
T2	92191	455	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	1027	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	210	0	0
T10	68260	0	0	0
T11	12318	240	0	0
T12	0	19	0	0
T13	0	643	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	218692	0	0
T1	441806	1589	0	0
T2	92191	455	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	1027	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	210	0	0
T10	68260	0	0	0
T11	12318	240	0	0
T12	0	19	0	0
T13	0	643	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	627280	0	0
T1	441806	5904	0	0
T2	92191	4433	0	0
T3	308205	0	0	0
T4	7056	48	0	0
T5	689312	2413	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	2184	0	0
T10	68260	0	0	0
T11	12318	248	0	0
T12	0	21	0	0
T13	0	758	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	218692	0	0
T1	441806	1589	0	0
T2	92191	455	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	1027	0	0
T7	2367	28	0	0
T8	4833	10	0	0
T9	332109	210	0	0
T10	68260	0	0	0
T11	12318	240	0	0
T12	0	19	0	0
T13	0	643	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	217525	0	0
GntImpliesValid_A	427056681	217525	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	217525	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3323880	0	0
ReadyAndValidImplyGrant_A	427056681	217525	0	0
ReqAndReadyImplyGrant_A	427056681	217525	0	0
ReqImpliesValid_A	427056681	593061	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	217525	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217525	0	0
T1	441806	1024	0	0
T2	92191	1440	0	0
T3	308205	479	0	0
T4	7056	17	0	0
T5	689312	456	0	0
T7	2367	41	0	0
T8	4833	28	0	0
T9	332109	204	0	0
T10	68260	0	0	0
T11	12318	207	0	0
T12	0	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217525	0	0
T1	441806	1024	0	0
T2	92191	1440	0	0
T3	308205	479	0	0
T4	7056	17	0	0
T5	689312	456	0	0
T7	2367	41	0	0
T8	4833	28	0	0
T9	332109	204	0	0
T10	68260	0	0	0
T11	12318	207	0	0
T12	0	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217525	0	0
T1	441806	1024	0	0
T2	92191	1440	0	0
T3	308205	479	0	0
T4	7056	17	0	0
T5	689312	456	0	0
T7	2367	41	0	0
T8	4833	28	0	0
T9	332109	204	0	0
T10	68260	0	0	0
T11	12318	207	0	0
T12	0	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3323880	0	0
T1	441806	7926	0	0
T2	92191	1838	0	0
T3	308205	1534	0	0
T4	7056	146	0	0
T5	689312	1484	0	0
T7	2367	39	0	0
T8	4833	181	0	0
T9	332109	67783	0	0
T10	68260	1	0	0
T11	12318	197	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217525	0	0
T1	441806	1024	0	0
T2	92191	1440	0	0
T3	308205	479	0	0
T4	7056	17	0	0
T5	689312	456	0	0
T7	2367	41	0	0
T8	4833	28	0	0
T9	332109	204	0	0
T10	68260	0	0	0
T11	12318	207	0	0
T12	0	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217525	0	0
T1	441806	1024	0	0
T2	92191	1440	0	0
T3	308205	479	0	0
T4	7056	17	0	0
T5	689312	456	0	0
T7	2367	41	0	0
T8	4833	28	0	0
T9	332109	204	0	0
T10	68260	0	0	0
T11	12318	207	0	0
T12	0	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	593061	0	0
T1	441806	1821	0	0
T2	92191	14437	0	0
T3	308205	1056	0	0
T4	7056	18	0	0
T5	689312	1126	0	0
T7	2367	44	0	0
T8	4833	41	0	0
T9	332109	4748	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217525	0	0
T1	441806	1024	0	0
T2	92191	1440	0	0
T3	308205	479	0	0
T4	7056	17	0	0
T5	689312	456	0	0
T7	2367	41	0	0
T8	4833	28	0	0
T9	332109	204	0	0
T10	68260	0	0	0
T11	12318	207	0	0
T12	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	227097	0	0
GntImpliesValid_A	427056681	227097	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	227097	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	5625719	0	0
ReadyAndValidImplyGrant_A	427056681	227097	0	0
ReqAndReadyImplyGrant_A	427056681	227097	0	0
ReqImpliesValid_A	427056681	1258316	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	227097	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	227097	0	0
T1	441806	508	0	0
T2	92191	0	0	0
T3	308205	437	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	8	0	0
T9	332109	226	0	0
T10	68260	0	0	0
T11	12318	242	0	0
T12	0	10	0	0
T13	0	588	0	0
T14	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	227097	0	0
T1	441806	508	0	0
T2	92191	0	0	0
T3	308205	437	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	8	0	0
T9	332109	226	0	0
T10	68260	0	0	0
T11	12318	242	0	0
T12	0	10	0	0
T13	0	588	0	0
T14	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	227097	0	0
T1	441806	508	0	0
T2	92191	0	0	0
T3	308205	437	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	8	0	0
T9	332109	226	0	0
T10	68260	0	0	0
T11	12318	242	0	0
T12	0	10	0	0
T13	0	588	0	0
T14	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	5625719	0	0
T1	441806	12573	0	0
T2	92191	0	0	0
T3	308205	2296	0	0
T4	7056	314	0	0
T5	689312	0	0	0
T7	2367	177	0	0
T8	4833	48	0	0
T9	332109	90469	0	0
T10	68260	0	0	0
T11	12318	856	0	0
T12	0	33	0	0
T13	0	13362	0	0
T14	0	1074	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	227097	0	0
T1	441806	508	0	0
T2	92191	0	0	0
T3	308205	437	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	8	0	0
T9	332109	226	0	0
T10	68260	0	0	0
T11	12318	242	0	0
T12	0	10	0	0
T13	0	588	0	0
T14	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	227097	0	0
T1	441806	508	0	0
T2	92191	0	0	0
T3	308205	437	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	8	0	0
T9	332109	226	0	0
T10	68260	0	0	0
T11	12318	242	0	0
T12	0	10	0	0
T13	0	588	0	0
T14	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	1258316	0	0
T1	441806	901	0	0
T2	92191	0	0	0
T3	308205	1262	0	0
T4	7056	53	0	0
T5	689312	0	0	0
T7	2367	57	0	0
T8	4833	8	0	0
T9	332109	3468	0	0
T10	68260	0	0	0
T11	12318	344	0	0
T12	0	10	0	0
T13	0	1406	0	0
T14	0	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	227097	0	0
T1	441806	508	0	0
T2	92191	0	0	0
T3	308205	437	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	8	0	0
T9	332109	226	0	0
T10	68260	0	0	0
T11	12318	242	0	0
T12	0	10	0	0
T13	0	588	0	0
T14	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	213264	0	0
GntImpliesValid_A	427056681	213264	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	213264	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	5427913	0	0
ReadyAndValidImplyGrant_A	427056681	213264	0	0
ReqAndReadyImplyGrant_A	427056681	213264	0	0
ReqImpliesValid_A	427056681	1201955	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	213264	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	213264	0	0
T1	441806	1024	0	0
T2	92191	0	0	0
T3	308205	574	0	0
T4	7056	25	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	5	0	0
T9	332109	197	0	0
T10	68260	0	0	0
T11	12318	223	0	0
T12	0	18	0	0
T13	0	1024	0	0
T14	0	108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	213264	0	0
T1	441806	1024	0	0
T2	92191	0	0	0
T3	308205	574	0	0
T4	7056	25	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	5	0	0
T9	332109	197	0	0
T10	68260	0	0	0
T11	12318	223	0	0
T12	0	18	0	0
T13	0	1024	0	0
T14	0	108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	213264	0	0
T1	441806	1024	0	0
T2	92191	0	0	0
T3	308205	574	0	0
T4	7056	25	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	5	0	0
T9	332109	197	0	0
T10	68260	0	0	0
T11	12318	223	0	0
T12	0	18	0	0
T13	0	1024	0	0
T14	0	108	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	5427913	0	0
T1	441806	24769	0	0
T2	92191	0	0	0
T3	308205	4193	0	0
T4	7056	234	0	0
T5	689312	0	0	0
T7	2367	107	0	0
T8	4833	63	0	0
T9	332109	56253	0	0
T10	68260	0	0	0
T11	12318	673	0	0
T12	0	72	0	0
T13	0	5358	0	0
T14	0	1263	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	213264	0	0
T1	441806	1024	0	0
T2	92191	0	0	0
T3	308205	574	0	0
T4	7056	25	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	5	0	0
T9	332109	197	0	0
T10	68260	0	0	0
T11	12318	223	0	0
T12	0	18	0	0
T13	0	1024	0	0
T14	0	108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	213264	0	0
T1	441806	1024	0	0
T2	92191	0	0	0
T3	308205	574	0	0
T4	7056	25	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	5	0	0
T9	332109	197	0	0
T10	68260	0	0	0
T11	12318	223	0	0
T12	0	18	0	0
T13	0	1024	0	0
T14	0	108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	1201955	0	0
T1	441806	10028	0	0
T2	92191	0	0	0
T3	308205	1695	0	0
T4	7056	64	0	0
T5	689312	0	0	0
T7	2367	39	0	0
T8	4833	5	0	0
T9	332109	2238	0	0
T10	68260	0	0	0
T11	12318	325	0	0
T12	0	29	0	0
T13	0	4409	0	0
T14	0	134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	213264	0	0
T1	441806	1024	0	0
T2	92191	0	0	0
T3	308205	574	0	0
T4	7056	25	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	5	0	0
T9	332109	197	0	0
T10	68260	0	0	0
T11	12318	223	0	0
T12	0	18	0	0
T13	0	1024	0	0
T14	0	108	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Not Covered
1	1	Covered	T1,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	217186	0	0
GntImpliesValid_A	427056681	217186	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	217186	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	5150076	0	0
ReadyAndValidImplyGrant_A	427056681	217186	0	0
ReqAndReadyImplyGrant_A	427056681	217186	0	0
ReqImpliesValid_A	427056681	1243052	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	217186	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217186	0	0
T1	441806	1027	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	26	0	0
T5	689312	465	0	0
T7	2367	38	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	0	0	0
T11	12318	184	0	0
T12	0	6	0	0
T13	0	614	0	0
T14	0	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217186	0	0
T1	441806	1027	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	26	0	0
T5	689312	465	0	0
T7	2367	38	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	0	0	0
T11	12318	184	0	0
T12	0	6	0	0
T13	0	614	0	0
T14	0	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217186	0	0
T1	441806	1027	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	26	0	0
T5	689312	465	0	0
T7	2367	38	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	0	0	0
T11	12318	184	0	0
T12	0	6	0	0
T13	0	614	0	0
T14	0	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	5150076	0	0
T1	441806	28525	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	374	0	0
T5	689312	3348	0	0
T7	2367	135	0	0
T8	4833	35	0	0
T9	332109	311916	0	0
T10	68260	0	0	0
T11	12318	600	0	0
T12	0	20	0	0
T13	0	5362	0	0
T14	0	1025	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217186	0	0
T1	441806	1027	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	26	0	0
T5	689312	465	0	0
T7	2367	38	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	0	0	0
T11	12318	184	0	0
T12	0	6	0	0
T13	0	614	0	0
T14	0	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217186	0	0
T1	441806	1027	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	26	0	0
T5	689312	465	0	0
T7	2367	38	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	0	0	0
T11	12318	184	0	0
T12	0	6	0	0
T13	0	614	0	0
T14	0	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	1243052	0	0
T1	441806	21645	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	108	0	0
T5	689312	1774	0	0
T7	2367	72	0	0
T8	4833	7	0	0
T9	332109	51641	0	0
T10	68260	0	0	0
T11	12318	226	0	0
T12	0	6	0	0
T13	0	754	0	0
T14	0	143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217186	0	0
T1	441806	1027	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	26	0	0
T5	689312	465	0	0
T7	2367	38	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	0	0	0
T11	12318	184	0	0
T12	0	6	0	0
T13	0	614	0	0
T14	0	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Not Covered
1	1	Covered	T1,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	216334	0	0
GntImpliesValid_A	427056681	216334	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	216334	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	5902250	0	0
ReadyAndValidImplyGrant_A	427056681	216334	0	0
ReqAndReadyImplyGrant_A	427056681	216334	0	0
ReqImpliesValid_A	427056681	1115731	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	216334	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216334	0	0
T1	441806	2550	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	21	0	0
T5	689312	550	0	0
T7	2367	24	0	0
T8	4833	6	0	0
T9	332109	184	0	0
T10	68260	544	0	0
T11	12318	225	0	0
T12	0	21	0	0
T13	0	642	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216334	0	0
T1	441806	2550	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	21	0	0
T5	689312	550	0	0
T7	2367	24	0	0
T8	4833	6	0	0
T9	332109	184	0	0
T10	68260	544	0	0
T11	12318	225	0	0
T12	0	21	0	0
T13	0	642	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216334	0	0
T1	441806	2550	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	21	0	0
T5	689312	550	0	0
T7	2367	24	0	0
T8	4833	6	0	0
T9	332109	184	0	0
T10	68260	544	0	0
T11	12318	225	0	0
T12	0	21	0	0
T13	0	642	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	5902250	0	0
T1	441806	20026	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	185	0	0
T5	689312	4228	0	0
T7	2367	125	0	0
T8	4833	37	0	0
T9	332109	150134	0	0
T10	68260	358	0	0
T11	12318	808	0	0
T12	0	75	0	0
T13	0	4857	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216334	0	0
T1	441806	2550	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	21	0	0
T5	689312	550	0	0
T7	2367	24	0	0
T8	4833	6	0	0
T9	332109	184	0	0
T10	68260	544	0	0
T11	12318	225	0	0
T12	0	21	0	0
T13	0	642	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216334	0	0
T1	441806	2550	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	21	0	0
T5	689312	550	0	0
T7	2367	24	0	0
T8	4833	6	0	0
T9	332109	184	0	0
T10	68260	544	0	0
T11	12318	225	0	0
T12	0	21	0	0
T13	0	642	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	1115731	0	0
T1	441806	19003	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	33	0	0
T5	689312	1958	0	0
T7	2367	30	0	0
T8	4833	6	0	0
T9	332109	11157	0	0
T10	68260	6346	0	0
T11	12318	351	0	0
T12	0	24	0	0
T13	0	836	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216334	0	0
T1	441806	2550	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	21	0	0
T5	689312	550	0	0
T7	2367	24	0	0
T8	4833	6	0	0
T9	332109	184	0	0
T10	68260	544	0	0
T11	12318	225	0	0
T12	0	21	0	0
T13	0	642	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T9
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	224746	0	0
GntImpliesValid_A	427056681	224746	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	224746	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3366029	0	0
ReadyAndValidImplyGrant_A	427056681	224746	0	0
ReqAndReadyImplyGrant_A	427056681	224746	0	0
ReqImpliesValid_A	427056681	639433	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	224746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	224746	0	0
T1	441806	1375	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	235	0	0
T10	68260	419	0	0
T11	12318	221	0	0
T12	0	14	0	0
T13	0	1117	0	0
T14	0	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	224746	0	0
T1	441806	1375	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	235	0	0
T10	68260	419	0	0
T11	12318	221	0	0
T12	0	14	0	0
T13	0	1117	0	0
T14	0	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	224746	0	0
T1	441806	1375	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	235	0	0
T10	68260	419	0	0
T11	12318	221	0	0
T12	0	14	0	0
T13	0	1117	0	0
T14	0	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3366029	0	0
T1	441806	8390	0	0
T2	92191	1	0	0
T3	308205	1	0	0
T4	7056	190	0	0
T5	689312	1	0	0
T7	2367	23	0	0
T8	4833	79	0	0
T9	332109	75844	0	0
T10	68260	400	0	0
T11	12318	214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	224746	0	0
T1	441806	1375	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	235	0	0
T10	68260	419	0	0
T11	12318	221	0	0
T12	0	14	0	0
T13	0	1117	0	0
T14	0	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	224746	0	0
T1	441806	1375	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	235	0	0
T10	68260	419	0	0
T11	12318	221	0	0
T12	0	14	0	0
T13	0	1117	0	0
T14	0	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	639433	0	0
T1	441806	4971	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	42	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	6220	0	0
T10	68260	4435	0	0
T11	12318	229	0	0
T12	0	16	0	0
T13	0	2037	0	0
T14	0	116	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	224746	0	0
T1	441806	1375	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	0	0	0
T7	2367	22	0	0
T8	4833	8	0	0
T9	332109	235	0	0
T10	68260	419	0	0
T11	12318	221	0	0
T12	0	14	0	0
T13	0	1117	0	0
T14	0	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	216792	0	0
GntImpliesValid_A	427056681	216792	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	216792	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3322959	0	0
ReadyAndValidImplyGrant_A	427056681	216792	0	0
ReqAndReadyImplyGrant_A	427056681	216792	0	0
ReqImpliesValid_A	427056681	620718	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	216792	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216792	0	0
T1	441806	1043	0	0
T2	92191	0	0	0
T3	308205	523	0	0
T4	7056	30	0	0
T5	689312	0	0	0
T7	2367	24	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	550	0	0
T11	12318	223	0	0
T12	0	19	0	0
T13	0	616	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216792	0	0
T1	441806	1043	0	0
T2	92191	0	0	0
T3	308205	523	0	0
T4	7056	30	0	0
T5	689312	0	0	0
T7	2367	24	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	550	0	0
T11	12318	223	0	0
T12	0	19	0	0
T13	0	616	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216792	0	0
T1	441806	1043	0	0
T2	92191	0	0	0
T3	308205	523	0	0
T4	7056	30	0	0
T5	689312	0	0	0
T7	2367	24	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	550	0	0
T11	12318	223	0	0
T12	0	19	0	0
T13	0	616	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3322959	0	0
T1	441806	4271	0	0
T2	92191	1	0	0
T3	308205	1773	0	0
T4	7056	199	0	0
T5	689312	1	0	0
T7	2367	22	0	0
T8	4833	60	0	0
T9	332109	72012	0	0
T10	68260	464	0	0
T11	12318	206	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216792	0	0
T1	441806	1043	0	0
T2	92191	0	0	0
T3	308205	523	0	0
T4	7056	30	0	0
T5	689312	0	0	0
T7	2367	24	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	550	0	0
T11	12318	223	0	0
T12	0	19	0	0
T13	0	616	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216792	0	0
T1	441806	1043	0	0
T2	92191	0	0	0
T3	308205	523	0	0
T4	7056	30	0	0
T5	689312	0	0	0
T7	2367	24	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	550	0	0
T11	12318	223	0	0
T12	0	19	0	0
T13	0	616	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	620718	0	0
T1	441806	6470	0	0
T2	92191	0	0	0
T3	308205	1125	0	0
T4	7056	34	0	0
T5	689312	0	0	0
T7	2367	27	0	0
T8	4833	7	0	0
T9	332109	4860	0	0
T10	68260	5855	0	0
T11	12318	241	0	0
T12	0	20	0	0
T13	0	830	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216792	0	0
T1	441806	1043	0	0
T2	92191	0	0	0
T3	308205	523	0	0
T4	7056	30	0	0
T5	689312	0	0	0
T7	2367	24	0	0
T8	4833	7	0	0
T9	332109	223	0	0
T10	68260	550	0	0
T11	12318	223	0	0
T12	0	19	0	0
T13	0	616	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	215945	0	0
GntImpliesValid_A	427056681	215945	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	215945	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3337771	0	0
ReadyAndValidImplyGrant_A	427056681	215945	0	0
ReqAndReadyImplyGrant_A	427056681	215945	0	0
ReqImpliesValid_A	427056681	586337	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	215945	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	215945	0	0
T1	441806	1872	0	0
T2	92191	0	0	0
T3	308205	510	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	12	0	0
T9	332109	206	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	14	0	0
T13	0	652	0	0
T14	0	124	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	215945	0	0
T1	441806	1872	0	0
T2	92191	0	0	0
T3	308205	510	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	12	0	0
T9	332109	206	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	14	0	0
T13	0	652	0	0
T14	0	124	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	215945	0	0
T1	441806	1872	0	0
T2	92191	0	0	0
T3	308205	510	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	12	0	0
T9	332109	206	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	14	0	0
T13	0	652	0	0
T14	0	124	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3337771	0	0
T1	441806	12450	0	0
T2	92191	1	0	0
T3	308205	1670	0	0
T4	7056	233	0	0
T5	689312	1	0	0
T7	2367	22	0	0
T8	4833	96	0	0
T9	332109	67432	0	0
T10	68260	1	0	0
T11	12318	218	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	215945	0	0
T1	441806	1872	0	0
T2	92191	0	0	0
T3	308205	510	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	12	0	0
T9	332109	206	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	14	0	0
T13	0	652	0	0
T14	0	124	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	215945	0	0
T1	441806	1872	0	0
T2	92191	0	0	0
T3	308205	510	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	12	0	0
T9	332109	206	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	14	0	0
T13	0	652	0	0
T14	0	124	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	586337	0	0
T1	441806	5419	0	0
T2	92191	0	0	0
T3	308205	1178	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	13	0	0
T9	332109	3329	0	0
T10	68260	0	0	0
T11	12318	245	0	0
T12	0	15	0	0
T13	0	837	0	0
T14	0	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	215945	0	0
T1	441806	1872	0	0
T2	92191	0	0	0
T3	308205	510	0	0
T4	7056	29	0	0
T5	689312	0	0	0
T7	2367	21	0	0
T8	4833	12	0	0
T9	332109	206	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	14	0	0
T13	0	652	0	0
T14	0	124	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	216365	0	0
GntImpliesValid_A	427056681	216365	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	216365	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3253248	0	0
ReadyAndValidImplyGrant_A	427056681	216365	0	0
ReqAndReadyImplyGrant_A	427056681	216365	0	0
ReqImpliesValid_A	427056681	573432	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	216365	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216365	0	0
T1	441806	535	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	477	0	0
T7	2367	19	0	0
T8	4833	39	0	0
T9	332109	229	0	0
T10	68260	0	0	0
T11	12318	220	0	0
T12	0	14	0	0
T13	0	1692	0	0
T14	0	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216365	0	0
T1	441806	535	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	477	0	0
T7	2367	19	0	0
T8	4833	39	0	0
T9	332109	229	0	0
T10	68260	0	0	0
T11	12318	220	0	0
T12	0	14	0	0
T13	0	1692	0	0
T14	0	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216365	0	0
T1	441806	535	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	477	0	0
T7	2367	19	0	0
T8	4833	39	0	0
T9	332109	229	0	0
T10	68260	0	0	0
T11	12318	220	0	0
T12	0	14	0	0
T13	0	1692	0	0
T14	0	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3253248	0	0
T1	441806	4257	0	0
T2	92191	1	0	0
T3	308205	1	0	0
T4	7056	116	0	0
T5	689312	1424	0	0
T7	2367	19	0	0
T8	4833	238	0	0
T9	332109	75472	0	0
T10	68260	1	0	0
T11	12318	210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216365	0	0
T1	441806	535	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	477	0	0
T7	2367	19	0	0
T8	4833	39	0	0
T9	332109	229	0	0
T10	68260	0	0	0
T11	12318	220	0	0
T12	0	14	0	0
T13	0	1692	0	0
T14	0	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216365	0	0
T1	441806	535	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	477	0	0
T7	2367	19	0	0
T8	4833	39	0	0
T9	332109	229	0	0
T10	68260	0	0	0
T11	12318	220	0	0
T12	0	14	0	0
T13	0	1692	0	0
T14	0	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	573432	0	0
T1	441806	658	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	1136	0	0
T7	2367	20	0	0
T8	4833	75	0	0
T9	332109	4425	0	0
T10	68260	0	0	0
T11	12318	231	0	0
T12	0	15	0	0
T13	0	3370	0	0
T14	0	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	216365	0	0
T1	441806	535	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	477	0	0
T7	2367	19	0	0
T8	4833	39	0	0
T9	332109	229	0	0
T10	68260	0	0	0
T11	12318	220	0	0
T12	0	14	0	0
T13	0	1692	0	0
T14	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	219188	0	0
GntImpliesValid_A	427056681	219188	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	219188	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3232959	0	0
ReadyAndValidImplyGrant_A	427056681	219188	0	0
ReqAndReadyImplyGrant_A	427056681	219188	0	0
ReqImpliesValid_A	427056681	595348	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	219188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219188	0	0
T1	441806	513	0	0
T2	92191	1578	0	0
T3	308205	547	0	0
T4	7056	15	0	0
T5	689312	452	0	0
T7	2367	24	0	0
T8	4833	13	0	0
T9	332109	216	0	0
T10	68260	552	0	0
T11	12318	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219188	0	0
T1	441806	513	0	0
T2	92191	1578	0	0
T3	308205	547	0	0
T4	7056	15	0	0
T5	689312	452	0	0
T7	2367	24	0	0
T8	4833	13	0	0
T9	332109	216	0	0
T10	68260	552	0	0
T11	12318	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219188	0	0
T1	441806	513	0	0
T2	92191	1578	0	0
T3	308205	547	0	0
T4	7056	15	0	0
T5	689312	452	0	0
T7	2367	24	0	0
T8	4833	13	0	0
T9	332109	216	0	0
T10	68260	552	0	0
T11	12318	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3232959	0	0
T1	441806	3880	0	0
T2	92191	3536	0	0
T3	308205	2029	0	0
T4	7056	141	0	0
T5	689312	1479	0	0
T7	2367	24	0	0
T8	4833	80	0	0
T9	332109	72407	0	0
T10	68260	699	0	0
T11	12318	210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219188	0	0
T1	441806	513	0	0
T2	92191	1578	0	0
T3	308205	547	0	0
T4	7056	15	0	0
T5	689312	452	0	0
T7	2367	24	0	0
T8	4833	13	0	0
T9	332109	216	0	0
T10	68260	552	0	0
T11	12318	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219188	0	0
T1	441806	513	0	0
T2	92191	1578	0	0
T3	308205	547	0	0
T4	7056	15	0	0
T5	689312	452	0	0
T7	2367	24	0	0
T8	4833	13	0	0
T9	332109	216	0	0
T10	68260	552	0	0
T11	12318	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	595348	0	0
T1	441806	535	0	0
T2	92191	6049	0	0
T3	308205	994	0	0
T4	7056	18	0	0
T5	689312	1119	0	0
T7	2367	25	0	0
T8	4833	13	0	0
T9	332109	3857	0	0
T10	68260	5532	0	0
T11	12318	231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219188	0	0
T1	441806	513	0	0
T2	92191	1578	0	0
T3	308205	547	0	0
T4	7056	15	0	0
T5	689312	452	0	0
T7	2367	24	0	0
T8	4833	13	0	0
T9	332109	216	0	0
T10	68260	552	0	0
T11	12318	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	225268	0	0
GntImpliesValid_A	427056681	225268	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	225268	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3335726	0	0
ReadyAndValidImplyGrant_A	427056681	225268	0	0
ReqAndReadyImplyGrant_A	427056681	225268	0	0
ReqImpliesValid_A	427056681	617272	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	225268	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225268	0	0
T1	441806	999	0	0
T2	92191	475	0	0
T3	308205	0	0	0
T4	7056	28	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	11	0	0
T9	332109	212	0	0
T10	68260	0	0	0
T11	12318	241	0	0
T12	0	12	0	0
T13	0	1078	0	0
T14	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225268	0	0
T1	441806	999	0	0
T2	92191	475	0	0
T3	308205	0	0	0
T4	7056	28	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	11	0	0
T9	332109	212	0	0
T10	68260	0	0	0
T11	12318	241	0	0
T12	0	12	0	0
T13	0	1078	0	0
T14	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225268	0	0
T1	441806	999	0	0
T2	92191	475	0	0
T3	308205	0	0	0
T4	7056	28	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	11	0	0
T9	332109	212	0	0
T10	68260	0	0	0
T11	12318	241	0	0
T12	0	12	0	0
T13	0	1078	0	0
T14	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3335726	0	0
T1	441806	4312	0	0
T2	92191	547	0	0
T3	308205	1	0	0
T4	7056	180	0	0
T5	689312	1	0	0
T7	2367	27	0	0
T8	4833	94	0	0
T9	332109	66719	0	0
T10	68260	1	0	0
T11	12318	234	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225268	0	0
T1	441806	999	0	0
T2	92191	475	0	0
T3	308205	0	0	0
T4	7056	28	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	11	0	0
T9	332109	212	0	0
T10	68260	0	0	0
T11	12318	241	0	0
T12	0	12	0	0
T13	0	1078	0	0
T14	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225268	0	0
T1	441806	999	0	0
T2	92191	475	0	0
T3	308205	0	0	0
T4	7056	28	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	11	0	0
T9	332109	212	0	0
T10	68260	0	0	0
T11	12318	241	0	0
T12	0	12	0	0
T13	0	1078	0	0
T14	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	617272	0	0
T1	441806	5950	0	0
T2	92191	4782	0	0
T3	308205	0	0	0
T4	7056	48	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	23	0	0
T9	332109	1568	0	0
T10	68260	0	0	0
T11	12318	249	0	0
T12	0	13	0	0
T13	0	2450	0	0
T14	0	154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225268	0	0
T1	441806	999	0	0
T2	92191	475	0	0
T3	308205	0	0	0
T4	7056	28	0	0
T5	689312	0	0	0
T7	2367	26	0	0
T8	4833	11	0	0
T9	332109	212	0	0
T10	68260	0	0	0
T11	12318	241	0	0
T12	0	12	0	0
T13	0	1078	0	0
T14	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	217520	0	0
GntImpliesValid_A	427056681	217520	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	217520	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3308580	0	0
ReadyAndValidImplyGrant_A	427056681	217520	0	0
ReqAndReadyImplyGrant_A	427056681	217520	0	0
ReqImpliesValid_A	427056681	591110	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	217520	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217520	0	0
T1	441806	1005	0	0
T2	92191	0	0	0
T3	308205	452	0	0
T4	7056	27	0	0
T5	689312	0	0	0
T7	2367	34	0	0
T8	4833	11	0	0
T9	332109	215	0	0
T10	68260	0	0	0
T11	12318	202	0	0
T12	0	15	0	0
T13	0	609	0	0
T14	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217520	0	0
T1	441806	1005	0	0
T2	92191	0	0	0
T3	308205	452	0	0
T4	7056	27	0	0
T5	689312	0	0	0
T7	2367	34	0	0
T8	4833	11	0	0
T9	332109	215	0	0
T10	68260	0	0	0
T11	12318	202	0	0
T12	0	15	0	0
T13	0	609	0	0
T14	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217520	0	0
T1	441806	1005	0	0
T2	92191	0	0	0
T3	308205	452	0	0
T4	7056	27	0	0
T5	689312	0	0	0
T7	2367	34	0	0
T8	4833	11	0	0
T9	332109	215	0	0
T10	68260	0	0	0
T11	12318	202	0	0
T12	0	15	0	0
T13	0	609	0	0
T14	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3308580	0	0
T1	441806	4881	0	0
T2	92191	1	0	0
T3	308205	1434	0	0
T4	7056	163	0	0
T5	689312	1	0	0
T7	2367	34	0	0
T8	4833	69	0	0
T9	332109	70901	0	0
T10	68260	1	0	0
T11	12318	193	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217520	0	0
T1	441806	1005	0	0
T2	92191	0	0	0
T3	308205	452	0	0
T4	7056	27	0	0
T5	689312	0	0	0
T7	2367	34	0	0
T8	4833	11	0	0
T9	332109	215	0	0
T10	68260	0	0	0
T11	12318	202	0	0
T12	0	15	0	0
T13	0	609	0	0
T14	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217520	0	0
T1	441806	1005	0	0
T2	92191	0	0	0
T3	308205	452	0	0
T4	7056	27	0	0
T5	689312	0	0	0
T7	2367	34	0	0
T8	4833	11	0	0
T9	332109	215	0	0
T10	68260	0	0	0
T11	12318	202	0	0
T12	0	15	0	0
T13	0	609	0	0
T14	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	591110	0	0
T1	441806	5271	0	0
T2	92191	0	0	0
T3	308205	1073	0	0
T4	7056	45	0	0
T5	689312	0	0	0
T7	2367	35	0	0
T8	4833	21	0	0
T9	332109	4000	0	0
T10	68260	0	0	0
T11	12318	212	0	0
T12	0	16	0	0
T13	0	750	0	0
T14	0	98	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	217520	0	0
T1	441806	1005	0	0
T2	92191	0	0	0
T3	308205	452	0	0
T4	7056	27	0	0
T5	689312	0	0	0
T7	2367	34	0	0
T8	4833	11	0	0
T9	332109	215	0	0
T10	68260	0	0	0
T11	12318	202	0	0
T12	0	15	0	0
T13	0	609	0	0
T14	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	230628	0	0
GntImpliesValid_A	427056681	230628	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	230628	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3323626	0	0
ReadyAndValidImplyGrant_A	427056681	230628	0	0
ReqAndReadyImplyGrant_A	427056681	230628	0	0
ReqImpliesValid_A	427056681	663535	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	230628	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	230628	0	0
T1	441806	520	0	0
T2	92191	896	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	1090	0	0
T7	2367	35	0	0
T8	4833	5	0	0
T9	332109	211	0	0
T10	68260	424	0	0
T11	12318	204	0	0
T12	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	230628	0	0
T1	441806	520	0	0
T2	92191	896	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	1090	0	0
T7	2367	35	0	0
T8	4833	5	0	0
T9	332109	211	0	0
T10	68260	424	0	0
T11	12318	204	0	0
T12	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	230628	0	0
T1	441806	520	0	0
T2	92191	896	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	1090	0	0
T7	2367	35	0	0
T8	4833	5	0	0
T9	332109	211	0	0
T10	68260	424	0	0
T11	12318	204	0	0
T12	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3323626	0	0
T1	441806	3891	0	0
T2	92191	1438	0	0
T3	308205	1	0	0
T4	7056	208	0	0
T5	689312	3705	0	0
T7	2367	33	0	0
T8	4833	39	0	0
T9	332109	67515	0	0
T10	68260	398	0	0
T11	12318	190	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	230628	0	0
T1	441806	520	0	0
T2	92191	896	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	1090	0	0
T7	2367	35	0	0
T8	4833	5	0	0
T9	332109	211	0	0
T10	68260	424	0	0
T11	12318	204	0	0
T12	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	230628	0	0
T1	441806	520	0	0
T2	92191	896	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	1090	0	0
T7	2367	35	0	0
T8	4833	5	0	0
T9	332109	211	0	0
T10	68260	424	0	0
T11	12318	204	0	0
T12	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	663535	0	0
T1	441806	585	0	0
T2	92191	8501	0	0
T3	308205	0	0	0
T4	7056	32	0	0
T5	689312	2412	0	0
T7	2367	38	0	0
T8	4833	5	0	0
T9	332109	6019	0	0
T10	68260	4316	0	0
T11	12318	219	0	0
T12	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	230628	0	0
T1	441806	520	0	0
T2	92191	896	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	1090	0	0
T7	2367	35	0	0
T8	4833	5	0	0
T9	332109	211	0	0
T10	68260	424	0	0
T11	12318	204	0	0
T12	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	241330	0	0
GntImpliesValid_A	427056681	241330	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	241330	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3375346	0	0
ReadyAndValidImplyGrant_A	427056681	241330	0	0
ReqAndReadyImplyGrant_A	427056681	241330	0	0
ReqImpliesValid_A	427056681	619349	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	241330	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	241330	0	0
T1	441806	2704	0	0
T2	92191	484	0	0
T3	308205	539	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	44	0	0
T8	4833	11	0	0
T9	332109	206	0	0
T10	68260	454	0	0
T11	12318	212	0	0
T12	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	241330	0	0
T1	441806	2704	0	0
T2	92191	484	0	0
T3	308205	539	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	44	0	0
T8	4833	11	0	0
T9	332109	206	0	0
T10	68260	454	0	0
T11	12318	212	0	0
T12	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	241330	0	0
T1	441806	2704	0	0
T2	92191	484	0	0
T3	308205	539	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	44	0	0
T8	4833	11	0	0
T9	332109	206	0	0
T10	68260	454	0	0
T11	12318	212	0	0
T12	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3375346	0	0
T1	441806	14744	0	0
T2	92191	345	0	0
T3	308205	1792	0	0
T4	7056	189	0	0
T5	689312	1	0	0
T7	2367	43	0	0
T8	4833	74	0	0
T9	332109	59879	0	0
T10	68260	642	0	0
T11	12318	208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	241330	0	0
T1	441806	2704	0	0
T2	92191	484	0	0
T3	308205	539	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	44	0	0
T8	4833	11	0	0
T9	332109	206	0	0
T10	68260	454	0	0
T11	12318	212	0	0
T12	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	241330	0	0
T1	441806	2704	0	0
T2	92191	484	0	0
T3	308205	539	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	44	0	0
T8	4833	11	0	0
T9	332109	206	0	0
T10	68260	454	0	0
T11	12318	212	0	0
T12	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	619349	0	0
T1	441806	12024	0	0
T2	92191	5164	0	0
T3	308205	1193	0	0
T4	7056	50	0	0
T5	689312	0	0	0
T7	2367	46	0	0
T8	4833	11	0	0
T9	332109	3132	0	0
T10	68260	4347	0	0
T11	12318	217	0	0
T12	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	241330	0	0
T1	441806	2704	0	0
T2	92191	484	0	0
T3	308205	539	0	0
T4	7056	31	0	0
T5	689312	0	0	0
T7	2367	44	0	0
T8	4833	11	0	0
T9	332109	206	0	0
T10	68260	454	0	0
T11	12318	212	0	0
T12	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	219190	0	0
GntImpliesValid_A	427056681	219190	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	219190	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3308989	0	0
ReadyAndValidImplyGrant_A	427056681	219190	0	0
ReqAndReadyImplyGrant_A	427056681	219190	0	0
ReqImpliesValid_A	427056681	592527	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	219190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219190	0	0
T1	441806	495	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	12	0	0
T9	332109	233	0	0
T10	68260	0	0	0
T11	12318	227	0	0
T12	0	17	0	0
T13	0	1145	0	0
T14	0	115	0	0
T15	0	482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219190	0	0
T1	441806	495	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	12	0	0
T9	332109	233	0	0
T10	68260	0	0	0
T11	12318	227	0	0
T12	0	17	0	0
T13	0	1145	0	0
T14	0	115	0	0
T15	0	482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219190	0	0
T1	441806	495	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	12	0	0
T9	332109	233	0	0
T10	68260	0	0	0
T11	12318	227	0	0
T12	0	17	0	0
T13	0	1145	0	0
T14	0	115	0	0
T15	0	482	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3308989	0	0
T1	441806	3774	0	0
T2	92191	1	0	0
T3	308205	1	0	0
T4	7056	151	0	0
T5	689312	1	0	0
T7	2367	26	0	0
T8	4833	67	0	0
T9	332109	78167	0	0
T10	68260	1	0	0
T11	12318	212	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219190	0	0
T1	441806	495	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	12	0	0
T9	332109	233	0	0
T10	68260	0	0	0
T11	12318	227	0	0
T12	0	17	0	0
T13	0	1145	0	0
T14	0	115	0	0
T15	0	482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219190	0	0
T1	441806	495	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	12	0	0
T9	332109	233	0	0
T10	68260	0	0	0
T11	12318	227	0	0
T12	0	17	0	0
T13	0	1145	0	0
T14	0	115	0	0
T15	0	482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	592527	0	0
T1	441806	563	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	26	0	0
T9	332109	5210	0	0
T10	68260	0	0	0
T11	12318	243	0	0
T12	0	17	0	0
T13	0	2792	0	0
T14	0	143	0	0
T15	0	1144	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219190	0	0
T1	441806	495	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	22	0	0
T5	689312	0	0	0
T7	2367	25	0	0
T8	4833	12	0	0
T9	332109	233	0	0
T10	68260	0	0	0
T11	12318	227	0	0
T12	0	17	0	0
T13	0	1145	0	0
T14	0	115	0	0
T15	0	482	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	225715	0	0
GntImpliesValid_A	427056681	225715	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	225715	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3364936	0	0
ReadyAndValidImplyGrant_A	427056681	225715	0	0
ReqAndReadyImplyGrant_A	427056681	225715	0	0
ReqImpliesValid_A	427056681	605745	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	225715	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225715	0	0
T1	441806	921	0	0
T2	92191	511	0	0
T3	308205	0	0	0
T4	7056	14	0	0
T5	689312	997	0	0
T7	2367	23	0	0
T8	4833	74	0	0
T9	332109	202	0	0
T10	68260	0	0	0
T11	12318	208	0	0
T12	0	12	0	0
T13	0	1162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225715	0	0
T1	441806	921	0	0
T2	92191	511	0	0
T3	308205	0	0	0
T4	7056	14	0	0
T5	689312	997	0	0
T7	2367	23	0	0
T8	4833	74	0	0
T9	332109	202	0	0
T10	68260	0	0	0
T11	12318	208	0	0
T12	0	12	0	0
T13	0	1162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225715	0	0
T1	441806	921	0	0
T2	92191	511	0	0
T3	308205	0	0	0
T4	7056	14	0	0
T5	689312	997	0	0
T7	2367	23	0	0
T8	4833	74	0	0
T9	332109	202	0	0
T10	68260	0	0	0
T11	12318	208	0	0
T12	0	12	0	0
T13	0	1162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3364936	0	0
T1	441806	6305	0	0
T2	92191	1027	0	0
T3	308205	1	0	0
T4	7056	71	0	0
T5	689312	3284	0	0
T7	2367	24	0	0
T8	4833	537	0	0
T9	332109	62180	0	0
T10	68260	1	0	0
T11	12318	192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225715	0	0
T1	441806	921	0	0
T2	92191	511	0	0
T3	308205	0	0	0
T4	7056	14	0	0
T5	689312	997	0	0
T7	2367	23	0	0
T8	4833	74	0	0
T9	332109	202	0	0
T10	68260	0	0	0
T11	12318	208	0	0
T12	0	12	0	0
T13	0	1162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225715	0	0
T1	441806	921	0	0
T2	92191	511	0	0
T3	308205	0	0	0
T4	7056	14	0	0
T5	689312	997	0	0
T7	2367	23	0	0
T8	4833	74	0	0
T9	332109	202	0	0
T10	68260	0	0	0
T11	12318	208	0	0
T12	0	12	0	0
T13	0	1162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	605745	0	0
T1	441806	2082	0	0
T2	92191	2263	0	0
T3	308205	0	0	0
T4	7056	15	0	0
T5	689312	2194	0	0
T7	2367	23	0	0
T8	4833	164	0	0
T9	332109	4345	0	0
T10	68260	0	0	0
T11	12318	225	0	0
T12	0	13	0	0
T13	0	2473	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	225715	0	0
T1	441806	921	0	0
T2	92191	511	0	0
T3	308205	0	0	0
T4	7056	14	0	0
T5	689312	997	0	0
T7	2367	23	0	0
T8	4833	74	0	0
T9	332109	202	0	0
T10	68260	0	0	0
T11	12318	208	0	0
T12	0	12	0	0
T13	0	1162	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	219902	0	0
GntImpliesValid_A	427056681	219902	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	219902	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3303555	0	0
ReadyAndValidImplyGrant_A	427056681	219902	0	0
ReqAndReadyImplyGrant_A	427056681	219902	0	0
ReqImpliesValid_A	427056681	580635	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	219902	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219902	0	0
T1	441806	486	0	0
T2	92191	0	0	0
T3	308205	577	0	0
T4	7056	24	0	0
T5	689312	431	0	0
T7	2367	22	0	0
T8	4833	10	0	0
T9	332109	188	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	19	0	0
T13	0	660	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219902	0	0
T1	441806	486	0	0
T2	92191	0	0	0
T3	308205	577	0	0
T4	7056	24	0	0
T5	689312	431	0	0
T7	2367	22	0	0
T8	4833	10	0	0
T9	332109	188	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	19	0	0
T13	0	660	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219902	0	0
T1	441806	486	0	0
T2	92191	0	0	0
T3	308205	577	0	0
T4	7056	24	0	0
T5	689312	431	0	0
T7	2367	22	0	0
T8	4833	10	0	0
T9	332109	188	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	19	0	0
T13	0	660	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3303555	0	0
T1	441806	3733	0	0
T2	92191	1	0	0
T3	308205	2019	0	0
T4	7056	202	0	0
T5	689312	1282	0	0
T7	2367	21	0	0
T8	4833	77	0	0
T9	332109	62338	0	0
T10	68260	1	0	0
T11	12318	205	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219902	0	0
T1	441806	486	0	0
T2	92191	0	0	0
T3	308205	577	0	0
T4	7056	24	0	0
T5	689312	431	0	0
T7	2367	22	0	0
T8	4833	10	0	0
T9	332109	188	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	19	0	0
T13	0	660	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219902	0	0
T1	441806	486	0	0
T2	92191	0	0	0
T3	308205	577	0	0
T4	7056	24	0	0
T5	689312	431	0	0
T7	2367	22	0	0
T8	4833	10	0	0
T9	332109	188	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	19	0	0
T13	0	660	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	580635	0	0
T1	441806	596	0	0
T2	92191	0	0	0
T3	308205	1217	0	0
T4	7056	48	0	0
T5	689312	1162	0	0
T7	2367	24	0	0
T8	4833	10	0	0
T9	332109	5324	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	19	0	0
T13	0	905	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	219902	0	0
T1	441806	486	0	0
T2	92191	0	0	0
T3	308205	577	0	0
T4	7056	24	0	0
T5	689312	431	0	0
T7	2367	22	0	0
T8	4833	10	0	0
T9	332109	188	0	0
T10	68260	0	0	0
T11	12318	218	0	0
T12	0	19	0	0
T13	0	660	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	222339	0	0
GntImpliesValid_A	427056681	222339	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	222339	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3263396	0	0
ReadyAndValidImplyGrant_A	427056681	222339	0	0
ReqAndReadyImplyGrant_A	427056681	222339	0	0
ReqImpliesValid_A	427056681	606752	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	222339	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	222339	0	0
T1	441806	1112	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	18	0	0
T5	689312	504	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	181	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	9	0	0
T13	0	1109	0	0
T14	0	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	222339	0	0
T1	441806	1112	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	18	0	0
T5	689312	504	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	181	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	9	0	0
T13	0	1109	0	0
T14	0	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	222339	0	0
T1	441806	1112	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	18	0	0
T5	689312	504	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	181	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	9	0	0
T13	0	1109	0	0
T14	0	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3263396	0	0
T1	441806	7259	0	0
T2	92191	1	0	0
T3	308205	1	0	0
T4	7056	144	0	0
T5	689312	1659	0	0
T7	2367	25	0	0
T8	4833	32	0	0
T9	332109	56976	0	0
T10	68260	1	0	0
T11	12318	217	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	222339	0	0
T1	441806	1112	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	18	0	0
T5	689312	504	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	181	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	9	0	0
T13	0	1109	0	0
T14	0	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	222339	0	0
T1	441806	1112	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	18	0	0
T5	689312	504	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	181	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	9	0	0
T13	0	1109	0	0
T14	0	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	606752	0	0
T1	441806	2901	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	31	0	0
T5	689312	1054	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	2791	0	0
T10	68260	0	0	0
T11	12318	248	0	0
T12	0	9	0	0
T13	0	4938	0	0
T14	0	143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	222339	0	0
T1	441806	1112	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	18	0	0
T5	689312	504	0	0
T7	2367	24	0	0
T8	4833	8	0	0
T9	332109	181	0	0
T10	68260	0	0	0
T11	12318	232	0	0
T12	0	9	0	0
T13	0	1109	0	0
T14	0	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T5
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Covered	T1,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	235315	0	0
GntImpliesValid_A	427056681	235315	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	235315	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	3320831	0	0
ReadyAndValidImplyGrant_A	427056681	235315	0	0
ReqAndReadyImplyGrant_A	427056681	235315	0	0
ReqImpliesValid_A	427056681	643235	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	0	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	235315	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	235315	0	0
T1	441806	499	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	996	0	0
T7	2367	18	0	0
T8	4833	9	0	0
T9	332109	214	0	0
T10	68260	480	0	0
T11	12318	215	0	0
T12	0	16	0	0
T13	0	1095	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	235315	0	0
T1	441806	499	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	996	0	0
T7	2367	18	0	0
T8	4833	9	0	0
T9	332109	214	0	0
T10	68260	480	0	0
T11	12318	215	0	0
T12	0	16	0	0
T13	0	1095	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	235315	0	0
T1	441806	499	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	996	0	0
T7	2367	18	0	0
T8	4833	9	0	0
T9	332109	214	0	0
T10	68260	480	0	0
T11	12318	215	0	0
T12	0	16	0	0
T13	0	1095	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	3320831	0	0
T1	441806	3944	0	0
T2	92191	1	0	0
T3	308205	1	0	0
T4	7056	291	0	0
T5	689312	3238	0	0
T7	2367	19	0	0
T8	4833	81	0	0
T9	332109	69349	0	0
T10	68260	1009	0	0
T11	12318	198	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	235315	0	0
T1	441806	499	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	996	0	0
T7	2367	18	0	0
T8	4833	9	0	0
T9	332109	214	0	0
T10	68260	480	0	0
T11	12318	215	0	0
T12	0	16	0	0
T13	0	1095	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	235315	0	0
T1	441806	499	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	996	0	0
T7	2367	18	0	0
T8	4833	9	0	0
T9	332109	214	0	0
T10	68260	480	0	0
T11	12318	215	0	0
T12	0	16	0	0
T13	0	1095	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	643235	0	0
T1	441806	586	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	2474	0	0
T7	2367	18	0	0
T8	4833	14	0	0
T9	332109	5315	0	0
T10	68260	4441	0	0
T11	12318	233	0	0
T12	0	16	0	0
T13	0	3650	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	235315	0	0
T1	441806	499	0	0
T2	92191	0	0	0
T3	308205	0	0	0
T4	7056	27	0	0
T5	689312	996	0	0
T7	2367	18	0	0
T8	4833	9	0	0
T9	332109	214	0	0
T10	68260	480	0	0
T11	12318	215	0	0
T12	0	16	0	0
T13	0	1095	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	881646	0	0
GntImpliesValid_A	427056681	881646	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	881646	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	12570460	0	0
ReadyAndValidImplyGrant_A	427056681	881646	0	0
ReqAndReadyImplyGrant_A	427056681	881646	0	0
ReqImpliesValid_A	427056681	2347090	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	16320	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	881646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	881646	0	0
T1	441806	3559	0	0
T2	92191	743	0	0
T3	308205	576	0	0
T4	7056	77	0	0
T5	689312	1548	0	0
T7	2367	111	0	0
T8	4833	53	0	0
T9	332109	830	0	0
T10	68260	406	0	0
T11	12318	923	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	881646	0	0
T1	441806	3559	0	0
T2	92191	743	0	0
T3	308205	576	0	0
T4	7056	77	0	0
T5	689312	1548	0	0
T7	2367	111	0	0
T8	4833	53	0	0
T9	332109	830	0	0
T10	68260	406	0	0
T11	12318	923	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	881646	0	0
T1	441806	3559	0	0
T2	92191	743	0	0
T3	308205	576	0	0
T4	7056	77	0	0
T5	689312	1548	0	0
T7	2367	111	0	0
T8	4833	53	0	0
T9	332109	830	0	0
T10	68260	406	0	0
T11	12318	923	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	12570460	0	0
T1	441806	23517	0	0
T2	92191	4602	0	0
T3	308205	1974	0	0
T4	7056	501	0	0
T5	689312	4453	0	0
T7	2367	1	0	0
T8	4833	418	0	0
T9	332109	265733	0	0
T10	68260	2717	0	0
T11	12318	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	881646	0	0
T1	441806	3559	0	0
T2	92191	743	0	0
T3	308205	576	0	0
T4	7056	77	0	0
T5	689312	1548	0	0
T7	2367	111	0	0
T8	4833	53	0	0
T9	332109	830	0	0
T10	68260	406	0	0
T11	12318	923	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	881646	0	0
T1	441806	3559	0	0
T2	92191	743	0	0
T3	308205	576	0	0
T4	7056	77	0	0
T5	689312	1548	0	0
T7	2367	111	0	0
T8	4833	53	0	0
T9	332109	830	0	0
T10	68260	406	0	0
T11	12318	923	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	2347090	0	0
T1	441806	5345	0	0
T2	92191	1183	0	0
T3	308205	745	0	0
T4	7056	117	0	0
T5	689312	2755	0	0
T7	2367	111	0	0
T8	4833	65	0	0
T9	332109	19355	0	0
T10	68260	632	0	0
T11	12318	923	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	16320	0	900
T5	689312	13	0	1
T7	2367	1	0	1
T8	4833	0	0	1
T9	332109	0	0	1
T10	68260	0	0	1
T11	12318	12	0	1
T12	2068	0	0	1
T13	327785	1	0	1
T14	58439	0	0	1
T15	339042	0	0	1
T16	0	6	0	0
T17	0	2	0	0
T18	0	1151	0	0
T19	0	4	0	0
T20	0	684	0	0
T21	0	17	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	881646	0	0
T1	441806	3559	0	0
T2	92191	743	0	0
T3	308205	576	0	0
T4	7056	77	0	0
T5	689312	1548	0	0
T7	2367	111	0	0
T8	4833	53	0	0
T9	332109	830	0	0
T10	68260	406	0	0
T11	12318	923	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427056681	426924165	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427056681	883251	0	0
GntImpliesValid_A	427056681	883251	0	0
GrantKnown_A	427056681	426924165	0	0
IdxKnown_A	427056681	426924165	0	0
IndexIsCorrect_A	427056681	883251	0	0
LockArbDecision_A	427056681	0	0	0
NoReadyValidNoGrant_A	427056681	359132011	0	0
ReadyAndValidImplyGrant_A	427056681	883251	0	0
ReqAndReadyImplyGrant_A	427056681	883251	0	0
ReqImpliesValid_A	427056681	14557824	0	0
ReqStaysHighUntilGranted0_M	427056681	0	0	0
RoundRobin_A	427056681	22764	0	900
ValidKnown_A	427056681	426924165	0	0
gen_data_port_assertion.DataFlow_A	427056681	883251	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	883251	0	0
T1	441806	3486	0	0
T2	92191	1561	0	0
T3	308205	1283	0	0
T4	7056	93	0	0
T5	689312	3185	0	0
T7	2367	122	0	0
T8	4833	61	0	0
T9	332109	808	0	0
T10	68260	1954	0	0
T11	12318	923	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	883251	0	0
T1	441806	3486	0	0
T2	92191	1561	0	0
T3	308205	1283	0	0
T4	7056	93	0	0
T5	689312	3185	0	0
T7	2367	122	0	0
T8	4833	61	0	0
T9	332109	808	0	0
T10	68260	1954	0	0
T11	12318	923	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	883251	0	0
T1	441806	3486	0	0
T2	92191	1561	0	0
T3	308205	1283	0	0
T4	7056	93	0	0
T5	689312	3185	0	0
T7	2367	122	0	0
T8	4833	61	0	0
T9	332109	808	0	0
T10	68260	1954	0	0
T11	12318	923	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	359132011	0	0
T1	441806	377356	0	0
T2	92191	70641	0	0
T3	308205	256246	0	0
T4	7056	5689	0	0
T5	689312	572968	0	0
T7	2367	1	0	0
T8	4833	3792	0	0
T9	332109	303518	0	0
T10	68260	46832	0	0
T11	12318	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	883251	0	0
T1	441806	3486	0	0
T2	92191	1561	0	0
T3	308205	1283	0	0
T4	7056	93	0	0
T5	689312	3185	0	0
T7	2367	122	0	0
T8	4833	61	0	0
T9	332109	808	0	0
T10	68260	1954	0	0
T11	12318	923	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	883251	0	0
T1	441806	3486	0	0
T2	92191	1561	0	0
T3	308205	1283	0	0
T4	7056	93	0	0
T5	689312	3185	0	0
T7	2367	122	0	0
T8	4833	61	0	0
T9	332109	808	0	0
T10	68260	1954	0	0
T11	12318	923	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	14557824	0	0
T1	441806	27756	0	0
T2	92191	14673	0	0
T3	308205	5647	0	0
T4	7056	775	0	0
T5	689312	14214	0	0
T7	2367	122	0	0
T8	4833	513	0	0
T9	332109	280033	0	0
T10	68260	11757	0	0
T11	12318	923	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	22764	0	900
T1	441806	1	0	1
T2	92191	21	0	1
T3	308205	12	0	1
T4	7056	0	0	1
T5	689312	36	0	1
T7	2367	3	0	1
T8	4833	0	0	1
T9	332109	0	0	1
T10	68260	145	0	1
T11	12318	26	0	1
T13	0	4	0	0
T16	0	6	0	0
T17	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	426924165	0	0
T1	441806	441711	0	0
T2	92191	92174	0	0
T3	308205	308202	0	0
T4	7056	7004	0	0
T5	689312	689306	0	0
T7	2367	2345	0	0
T8	4833	4660	0	0
T9	332109	332105	0	0
T10	68260	68237	0	0
T11	12318	12309	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427056681	883251	0	0
T1	441806	3486	0	0
T2	92191	1561	0	0
T3	308205	1283	0	0
T4	7056	93	0	0
T5	689312	3185	0	0
T7	2367	122	0	0
T8	4833	61	0	0
T9	332109	808	0	0
T10	68260	1954	0	0
T11	12318	923	0	0