Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sm1_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.51 98.68 85.92 92.73 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 92.21 97.50 82.14 89.19 100.00



Module Instance : tb.dut.u_sm1_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_40

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_42

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_43

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_44

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_45

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_46

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_47

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_48

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_49

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_50

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_51

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_52

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_53

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_54

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_55

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_56

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.78 100.00 98.39 100.00 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
SCORELINE
95.96 100.00
tb.dut.u_sm1_28

SCORELINE
95.96 100.00
tb.dut.u_sm1_29

SCORELINE
100.00 100.00
tb.dut.u_sm1_30

SCORELINE
95.96 100.00
tb.dut.u_sm1_31

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
SCORELINE
96.97 100.00
tb.dut.u_sm1_33

SCORELINE
96.97 100.00
tb.dut.u_sm1_34

SCORELINE
96.97 100.00
tb.dut.u_sm1_36

SCORELINE
96.97 100.00
tb.dut.u_sm1_38

SCORELINE
96.97 100.00
tb.dut.u_sm1_40

SCORELINE
96.97 100.00
tb.dut.u_sm1_42

SCORELINE
96.97 100.00
tb.dut.u_sm1_43

SCORELINE
96.97 100.00
tb.dut.u_sm1_44

SCORELINE
96.97 100.00
tb.dut.u_sm1_45

SCORELINE
96.97 100.00
tb.dut.u_sm1_46

SCORELINE
96.97 100.00
tb.dut.u_sm1_47

SCORELINE
96.97 100.00
tb.dut.u_sm1_48

SCORELINE
96.97 100.00
tb.dut.u_sm1_49

SCORELINE
96.97 100.00
tb.dut.u_sm1_50

SCORELINE
96.97 100.00
tb.dut.u_sm1_51

SCORELINE
96.97 100.00
tb.dut.u_sm1_52

SCORELINE
96.97 100.00
tb.dut.u_sm1_53

SCORELINE
96.97 100.00
tb.dut.u_sm1_54

SCORELINE
96.97 100.00
tb.dut.u_sm1_55

SCORELINE
96.97 100.00
tb.dut.u_sm1_56

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
SCORECOND
95.96 87.88
tb.dut.u_sm1_28

SCORECOND
95.96 87.88
tb.dut.u_sm1_29

SCORECOND
95.96 87.88
tb.dut.u_sm1_31

SCORECOND
100.00 100.00
tb.dut.u_sm1_30

TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT13,T15,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT13,T15,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT13,T15,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT13,T15,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
SCORECOND
96.97 90.91
tb.dut.u_sm1_33

SCORECOND
96.97 90.91
tb.dut.u_sm1_34

SCORECOND
96.97 90.91
tb.dut.u_sm1_43

SCORECOND
96.97 90.91
tb.dut.u_sm1_44

SCORECOND
96.97 90.91
tb.dut.u_sm1_45

SCORECOND
96.97 90.91
tb.dut.u_sm1_46

SCORECOND
96.97 90.91
tb.dut.u_sm1_47

SCORECOND
96.97 90.91
tb.dut.u_sm1_48

SCORECOND
96.97 90.91
tb.dut.u_sm1_49

SCORECOND
96.97 90.91
tb.dut.u_sm1_50

SCORECOND
96.97 90.91
tb.dut.u_sm1_51

SCORECOND
96.97 90.91
tb.dut.u_sm1_52

SCORECOND
96.97 90.91
tb.dut.u_sm1_53

SCORECOND
96.97 90.91
tb.dut.u_sm1_54

SCORECOND
96.97 90.91
tb.dut.u_sm1_55

SCORECOND
96.97 90.91
tb.dut.u_sm1_56

SCORECOND
96.97 90.91
tb.dut.u_sm1_36

SCORECOND
96.97 90.91
tb.dut.u_sm1_38

SCORECOND
96.97 90.91
tb.dut.u_sm1_40

SCORECOND
96.97 90.91
tb.dut.u_sm1_42

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Module : tlul_socket_m1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 2147483647 23891659 0 0
gen_host_fifo[1].idInRange 2147483647 13499388 0 0
gen_host_fifo[2].idInRange 1742976816 3894948 0 0
maxM 21600 21600 0 0
rspIdInRange 2147483647 184041218 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 23891659 0 0
T1 3701952 15641 0 0
T2 780360 14164 0 0
T3 3369576 124803 0 0
T4 2622024 47345 0 0
T7 8743728 78143 0 0
T8 5871408 8949 0 0
T9 199008 1947 0 0
T10 239520 2728 0 0
T11 51360 302 0 0
T12 5815680 254601 0 0
T13 0 711 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 13499388 0 0
T1 3701952 9488 0 0
T2 780360 7434 0 0
T3 3369576 46480 0 0
T4 2622024 44469 0 0
T7 8743728 64082 0 0
T8 5871408 4328 0 0
T9 199008 1059 0 0
T10 239520 1414 0 0
T11 51360 137 0 0
T12 5815680 79098 0 0
T13 0 692 0 0
T15 0 292 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 1742976816 3894948 0 0
T1 616992 1148 0 0
T2 130060 788 0 0
T3 561596 23746 0 0
T4 437004 16230 0 0
T7 1457288 13084 0 0
T8 978568 1084 0 0
T9 33168 167 0 0
T10 39920 236 0 0
T11 8560 29 0 0
T12 969280 44077 0 0
T13 0 48 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 21600 21600 0 0
T1 24 24 0 0
T2 24 24 0 0
T3 24 24 0 0
T4 24 24 0 0
T7 24 24 0 0
T8 24 24 0 0
T9 24 24 0 0
T10 24 24 0 0
T11 24 24 0 0
T12 24 24 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 184041218 0 0
T1 3701952 48779 0 0
T2 780360 18321 0 0
T3 3369576 649144 0 0
T4 2622024 47956 0 0
T7 8743728 104532 0 0
T8 5871408 1486464 0 0
T9 199008 3067 0 0
T10 239520 3946 0 0
T11 51360 421 0 0
T12 5815680 790559 0 0
T13 0 1249 0 0

Line Coverage for Instance : tb.dut.u_sm1_28
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_28
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 1728607 0 0
gen_host_fifo[1].idInRange 435744204 440146 0 0
gen_host_fifo[2].idInRange 435744204 570172 0 0
maxM 900 900 0 0
rspIdInRange 435744204 22914974 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 1728607 0 0
T1 154248 931 0 0
T2 32515 1679 0 0
T3 140399 11027 0 0
T4 109251 1006 0 0
T7 364322 5163 0 0
T8 244642 954 0 0
T9 8292 274 0 0
T10 9980 330 0 0
T11 2140 46 0 0
T12 242320 17417 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 440146 0 0
T1 154248 180 0 0
T2 32515 209 0 0
T3 140399 1070 0 0
T4 109251 0 0 0
T7 364322 2622 0 0
T8 244642 112 0 0
T9 8292 52 0 0
T10 9980 42 0 0
T11 2140 4 0 0
T12 242320 3047 0 0
T13 0 57 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 570172 0 0
T1 154248 153 0 0
T2 32515 187 0 0
T3 140399 2496 0 0
T4 109251 0 0 0
T7 364322 1785 0 0
T8 244642 148 0 0
T9 8292 43 0 0
T10 9980 63 0 0
T11 2140 9 0 0
T12 242320 2307 0 0
T13 0 48 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 22914974 0 0
T1 154248 6974 0 0
T2 32515 2034 0 0
T3 140399 104295 0 0
T4 109251 5047 0 0
T7 364322 15176 0 0
T8 244642 293384 0 0
T9 8292 365 0 0
T10 9980 425 0 0
T11 2140 59 0 0
T12 242320 165907 0 0

Line Coverage for Instance : tb.dut.u_sm1_29
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_29
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 1921675 0 0
gen_host_fifo[1].idInRange 435744204 524185 0 0
gen_host_fifo[2].idInRange 435744204 668061 0 0
maxM 900 900 0 0
rspIdInRange 435744204 24636111 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 1921675 0 0
T1 154248 915 0 0
T2 32515 1987 0 0
T3 140399 7306 0 0
T4 109251 2331 0 0
T7 364322 2824 0 0
T8 244642 995 0 0
T9 8292 282 0 0
T10 9980 421 0 0
T11 2140 47 0 0
T12 242320 19515 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 524185 0 0
T1 154248 165 0 0
T2 32515 245 0 0
T3 140399 1663 0 0
T4 109251 1284 0 0
T7 364322 297 0 0
T8 244642 132 0 0
T9 8292 47 0 0
T10 9980 47 0 0
T11 2140 8 0 0
T12 242320 836 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 668061 0 0
T1 154248 145 0 0
T2 32515 192 0 0
T3 140399 2472 0 0
T4 109251 1572 0 0
T7 364322 235 0 0
T8 244642 150 0 0
T9 8292 55 0 0
T10 9980 52 0 0
T11 2140 3 0 0
T12 242320 5945 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 24636111 0 0
T1 154248 6637 0 0
T2 32515 1981 0 0
T3 140399 94035 0 0
T4 109251 8276 0 0
T7 364322 12549 0 0
T8 244642 277657 0 0
T9 8292 368 0 0
T10 9980 440 0 0
T11 2140 50 0 0
T12 242320 149598 0 0

Line Coverage for Instance : tb.dut.u_sm1_31
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_31
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 1895601 0 0
gen_host_fifo[1].idInRange 435744204 522832 0 0
gen_host_fifo[2].idInRange 435744204 638929 0 0
maxM 900 900 0 0
rspIdInRange 435744204 24914874 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 1895601 0 0
T1 154248 885 0 0
T2 32515 2041 0 0
T3 140399 4019 0 0
T4 109251 6146 0 0
T7 364322 6938 0 0
T8 244642 985 0 0
T9 8292 300 0 0
T10 9980 427 0 0
T11 2140 39 0 0
T12 242320 18906 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 522832 0 0
T1 154248 123 0 0
T2 32515 263 0 0
T3 140399 43 0 0
T4 109251 5200 0 0
T7 364322 4571 0 0
T8 244642 133 0 0
T9 8292 48 0 0
T10 9980 64 0 0
T11 2140 2 0 0
T12 242320 3446 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 638929 0 0
T1 154248 139 0 0
T2 32515 217 0 0
T3 140399 2179 0 0
T4 109251 5083 0 0
T7 364322 4564 0 0
T8 244642 144 0 0
T9 8292 34 0 0
T10 9980 61 0 0
T11 2140 11 0 0
T12 242320 4271 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 24914874 0 0
T1 154248 6623 0 0
T2 32515 2026 0 0
T3 140399 95717 0 0
T4 109251 8900 0 0
T7 364322 14444 0 0
T8 244642 281742 0 0
T9 8292 362 0 0
T10 9980 469 0 0
T11 2140 47 0 0
T12 242320 162442 0 0

Line Coverage for Instance : tb.dut.u_sm1_33
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_33
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 303116 0 0
gen_host_fifo[1].idInRange 435744204 425986 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4168466 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 303116 0 0
T1 154248 119 0 0
T2 32515 205 0 0
T3 140399 29 0 0
T4 109251 2658 0 0
T7 364322 2672 0 0
T8 244642 163 0 0
T9 8292 45 0 0
T10 9980 65 0 0
T11 2140 3 0 0
T12 242320 871 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 425986 0 0
T1 154248 120 0 0
T2 32515 222 0 0
T3 140399 713 0 0
T4 109251 3384 0 0
T7 364322 3230 0 0
T8 244642 194 0 0
T9 8292 44 0 0
T10 9980 57 0 0
T11 2140 5 0 0
T12 242320 2265 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4168466 0 0
T1 154248 977 0 0
T2 32515 406 0 0
T3 140399 9579 0 0
T4 109251 1097 0 0
T7 364322 5164 0 0
T8 244642 21450 0 0
T9 8292 89 0 0
T10 9980 116 0 0
T11 2140 8 0 0
T12 242320 3155 0 0

Line Coverage for Instance : tb.dut.u_sm1_34
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_34
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 314644 0 0
gen_host_fifo[1].idInRange 435744204 417399 0 0
maxM 900 900 0 0
rspIdInRange 435744204 3518315 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 314644 0 0
T1 154248 120 0 0
T2 32515 392 0 0
T3 140399 965 0 0
T4 109251 0 0 0
T7 364322 236 0 0
T8 244642 142 0 0
T9 8292 42 0 0
T10 9980 50 0 0
T11 2140 6 0 0
T12 242320 878 0 0
T13 0 55 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 417399 0 0
T1 154248 135 0 0
T2 32515 427 0 0
T3 140399 388 0 0
T4 109251 0 0 0
T7 364322 211 0 0
T8 244642 196 0 0
T9 8292 37 0 0
T10 9980 57 0 0
T11 2140 7 0 0
T12 242320 1115 0 0
T13 0 51 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 3518315 0 0
T1 154248 988 0 0
T2 32515 738 0 0
T3 140399 10045 0 0
T4 109251 0 0 0
T7 364322 1508 0 0
T8 244642 18846 0 0
T9 8292 79 0 0
T10 9980 102 0 0
T11 2140 13 0 0
T12 242320 5403 0 0
T13 0 106 0 0

Line Coverage for Instance : tb.dut.u_sm1_36
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_36
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 749604 0 0
gen_host_fifo[1].idInRange 435744204 871085 0 0
maxM 900 900 0 0
rspIdInRange 435744204 5316030 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 749604 0 0
T1 154248 109 0 0
T2 32515 1336 0 0
T3 140399 34 0 0
T4 109251 0 0 0
T7 364322 18000 0 0
T8 244642 198 0 0
T9 8292 45 0 0
T10 9980 75 0 0
T11 2140 5 0 0
T12 242320 121 0 0
T13 0 76 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 871085 0 0
T1 154248 118 0 0
T2 32515 1297 0 0
T3 140399 359 0 0
T4 109251 0 0 0
T7 364322 19589 0 0
T8 244642 197 0 0
T9 8292 76 0 0
T10 9980 51 0 0
T11 2140 4 0 0
T12 242320 772 0 0
T13 0 76 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 5316030 0 0
T1 154248 891 0 0
T2 32515 1112 0 0
T3 140399 12314 0 0
T4 109251 0 0 0
T7 364322 6130 0 0
T8 244642 15310 0 0
T9 8292 94 0 0
T10 9980 92 0 0
T11 2140 9 0 0
T12 242320 20489 0 0
T13 0 101 0 0

Line Coverage for Instance : tb.dut.u_sm1_38
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_38
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T8,T12
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 636509 0 0
gen_host_fifo[1].idInRange 435744204 787425 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4935795 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 636509 0 0
T1 154248 149 0 0
T2 32515 307 0 0
T3 140399 6411 0 0
T4 109251 0 0 0
T7 364322 259 0 0
T8 244642 142 0 0
T9 8292 53 0 0
T10 9980 106 0 0
T11 2140 6 0 0
T12 242320 307 0 0
T13 0 65 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 787425 0 0
T1 154248 115 0 0
T2 32515 259 0 0
T3 140399 5453 0 0
T4 109251 0 0 0
T7 364322 204 0 0
T8 244642 191 0 0
T9 8292 52 0 0
T10 9980 50 0 0
T11 2140 13 0 0
T12 242320 990 0 0
T13 0 68 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4935795 0 0
T1 154248 892 0 0
T2 32515 395 0 0
T3 140399 11119 0 0
T4 109251 0 0 0
T7 364322 1472 0 0
T8 244642 32974 0 0
T9 8292 93 0 0
T10 9980 100 0 0
T11 2140 13 0 0
T12 242320 29803 0 0
T13 0 116 0 0

Line Coverage for Instance : tb.dut.u_sm1_40
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_40
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 686277 0 0
gen_host_fifo[1].idInRange 435744204 798868 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4800782 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 686277 0 0
T1 154248 125 0 0
T2 32515 283 0 0
T3 140399 5150 0 0
T4 109251 0 0 0
T7 364322 219 0 0
T8 244642 172 0 0
T9 8292 33 0 0
T10 9980 76 0 0
T11 2140 32 0 0
T12 242320 296 0 0
T13 0 72 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 798868 0 0
T1 154248 115 0 0
T2 32515 335 0 0
T3 140399 3070 0 0
T4 109251 0 0 0
T7 364322 232 0 0
T8 244642 327 0 0
T9 8292 22 0 0
T10 9980 62 0 0
T11 2140 3 0 0
T12 242320 509 0 0
T13 0 46 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4800782 0 0
T1 154248 892 0 0
T2 32515 407 0 0
T3 140399 17657 0 0
T4 109251 0 0 0
T7 364322 1677 0 0
T8 244642 12534 0 0
T9 8292 55 0 0
T10 9980 112 0 0
T11 2140 12 0 0
T12 242320 26029 0 0
T13 0 99 0 0

Line Coverage for Instance : tb.dut.u_sm1_42
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_42
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 907840 0 0
gen_host_fifo[1].idInRange 435744204 1032354 0 0
maxM 900 900 0 0
rspIdInRange 435744204 5172232 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 907840 0 0
T1 154248 1729 0 0
T2 32515 309 0 0
T3 140399 653 0 0
T4 109251 2793 0 0
T7 364322 346 0 0
T8 244642 164 0 0
T9 8292 42 0 0
T10 9980 51 0 0
T11 2140 4 0 0
T12 242320 1335 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 1032354 0 0
T1 154248 2918 0 0
T2 32515 188 0 0
T3 140399 1239 0 0
T4 109251 3280 0 0
T7 364322 382 0 0
T8 244642 268 0 0
T9 8292 44 0 0
T10 9980 111 0 0
T11 2140 2 0 0
T12 242320 2768 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 5172232 0 0
T1 154248 2214 0 0
T2 32515 400 0 0
T3 140399 15263 0 0
T4 109251 1361 0 0
T7 364322 1627 0 0
T8 244642 13668 0 0
T9 8292 78 0 0
T10 9980 121 0 0
T11 2140 6 0 0
T12 242320 4778 0 0

Line Coverage for Instance : tb.dut.u_sm1_43
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_43
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 270431 0 0
gen_host_fifo[1].idInRange 435744204 369642 0 0
maxM 900 900 0 0
rspIdInRange 435744204 3894132 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 270431 0 0
T1 154248 130 0 0
T2 32515 216 0 0
T3 140399 35 0 0
T4 109251 3115 0 0
T7 364322 182 0 0
T8 244642 105 0 0
T9 8292 37 0 0
T10 9980 44 0 0
T11 2140 5 0 0
T12 242320 76 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 369642 0 0
T1 154248 138 0 0
T2 32515 201 0 0
T3 140399 43 0 0
T4 109251 3820 0 0
T7 364322 255 0 0
T8 244642 168 0 0
T9 8292 46 0 0
T10 9980 60 0 0
T11 2140 8 0 0
T12 242320 2692 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 3894132 0 0
T1 154248 1060 0 0
T2 32515 397 0 0
T3 140399 11379 0 0
T4 109251 1199 0 0
T7 364322 1167 0 0
T8 244642 13165 0 0
T9 8292 83 0 0
T10 9980 100 0 0
T11 2140 13 0 0
T12 242320 4731 0 0

Line Coverage for Instance : tb.dut.u_sm1_44
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_44
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 275863 0 0
gen_host_fifo[1].idInRange 435744204 355290 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4127819 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 275863 0 0
T1 154248 107 0 0
T2 32515 239 0 0
T3 140399 37 0 0
T4 109251 2482 0 0
T7 364322 3300 0 0
T8 244642 129 0 0
T9 8292 28 0 0
T10 9980 60 0 0
T11 2140 3 0 0
T12 242320 1192 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 355290 0 0
T1 154248 119 0 0
T2 32515 172 0 0
T3 140399 997 0 0
T4 109251 2703 0 0
T7 364322 3925 0 0
T8 244642 165 0 0
T9 8292 48 0 0
T10 9980 60 0 0
T11 2140 7 0 0
T12 242320 2356 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4127819 0 0
T1 154248 827 0 0
T2 32515 391 0 0
T3 140399 11399 0 0
T4 109251 3686 0 0
T7 364322 3215 0 0
T8 244642 14173 0 0
T9 8292 75 0 0
T10 9980 114 0 0
T11 2140 10 0 0
T12 242320 5518 0 0

Line Coverage for Instance : tb.dut.u_sm1_45
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_45
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 310345 0 0
gen_host_fifo[1].idInRange 435744204 407769 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4720136 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 310345 0 0
T1 154248 146 0 0
T2 32515 219 0 0
T3 140399 337 0 0
T4 109251 0 0 0
T7 364322 238 0 0
T8 244642 129 0 0
T9 8292 40 0 0
T10 9980 57 0 0
T11 2140 2 0 0
T12 242320 667 0 0
T13 0 55 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 407769 0 0
T1 154248 107 0 0
T2 32515 211 0 0
T3 140399 269 0 0
T4 109251 0 0 0
T7 364322 241 0 0
T8 244642 195 0 0
T9 8292 39 0 0
T10 9980 49 0 0
T11 2140 4 0 0
T12 242320 1087 0 0
T13 0 62 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4720136 0 0
T1 154248 1079 0 0
T2 32515 399 0 0
T3 140399 10509 0 0
T4 109251 0 0 0
T7 364322 1500 0 0
T8 244642 19574 0 0
T9 8292 78 0 0
T10 9980 93 0 0
T11 2140 6 0 0
T12 242320 7663 0 0
T13 0 115 0 0

Line Coverage for Instance : tb.dut.u_sm1_46
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_46
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 296788 0 0
gen_host_fifo[1].idInRange 435744204 386734 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4446448 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 296788 0 0
T1 154248 119 0 0
T2 32515 197 0 0
T3 140399 700 0 0
T4 109251 1289 0 0
T7 364322 198 0 0
T8 244642 138 0 0
T9 8292 34 0 0
T10 9980 57 0 0
T11 2140 5 0 0
T12 242320 1227 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 386734 0 0
T1 154248 112 0 0
T2 32515 228 0 0
T3 140399 3596 0 0
T4 109251 1270 0 0
T7 364322 263 0 0
T8 244642 179 0 0
T9 8292 41 0 0
T10 9980 56 0 0
T11 2140 8 0 0
T12 242320 1932 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4446448 0 0
T1 154248 1012 0 0
T2 32515 413 0 0
T3 140399 12522 0 0
T4 109251 2035 0 0
T7 364322 1512 0 0
T8 244642 19611 0 0
T9 8292 75 0 0
T10 9980 111 0 0
T11 2140 13 0 0
T12 242320 4972 0 0

Line Coverage for Instance : tb.dut.u_sm1_47
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_47
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 326414 0 0
gen_host_fifo[1].idInRange 435744204 420673 0 0
maxM 900 900 0 0
rspIdInRange 435744204 3606762 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 326414 0 0
T1 154248 104 0 0
T2 32515 212 0 0
T3 140399 907 0 0
T4 109251 0 0 0
T7 364322 192 0 0
T8 244642 124 0 0
T9 8292 39 0 0
T10 9980 49 0 0
T11 2140 3 0 0
T12 242320 1579 0 0
T13 0 49 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 420673 0 0
T1 154248 119 0 0
T2 32515 201 0 0
T3 140399 835 0 0
T4 109251 0 0 0
T7 364322 237 0 0
T8 244642 108 0 0
T9 8292 43 0 0
T10 9980 50 0 0
T11 2140 4 0 0
T12 242320 2356 0 0
T13 0 54 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 3606762 0 0
T1 154248 831 0 0
T2 32515 394 0 0
T3 140399 10772 0 0
T4 109251 0 0 0
T7 364322 1504 0 0
T8 244642 16709 0 0
T9 8292 81 0 0
T10 9980 96 0 0
T11 2140 7 0 0
T12 242320 5925 0 0
T13 0 102 0 0

Line Coverage for Instance : tb.dut.u_sm1_48
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_48
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 360514 0 0
gen_host_fifo[1].idInRange 435744204 473726 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4233234 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 360514 0 0
T1 154248 112 0 0
T2 32515 189 0 0
T3 140399 818 0 0
T4 109251 3359 0 0
T7 364322 2682 0 0
T8 244642 129 0 0
T9 8292 37 0 0
T10 9980 58 0 0
T11 2140 6 0 0
T12 242320 239 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 473726 0 0
T1 154248 97 0 0
T2 32515 212 0 0
T3 140399 2007 0 0
T4 109251 4135 0 0
T7 364322 3188 0 0
T8 244642 163 0 0
T9 8292 55 0 0
T10 9980 58 0 0
T11 2140 6 0 0
T12 242320 294 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4233234 0 0
T1 154248 944 0 0
T2 32515 388 0 0
T3 140399 15283 0 0
T4 109251 1503 0 0
T7 364322 2754 0 0
T8 244642 20496 0 0
T9 8292 91 0 0
T10 9980 111 0 0
T11 2140 11 0 0
T12 242320 3828 0 0

Line Coverage for Instance : tb.dut.u_sm1_49
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_49
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 352211 0 0
gen_host_fifo[1].idInRange 435744204 457995 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4323366 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 352211 0 0
T1 154248 103 0 0
T2 32515 573 0 0
T3 140399 420 0 0
T4 109251 0 0 0
T7 364322 198 0 0
T8 244642 122 0 0
T9 8292 40 0 0
T10 9980 56 0 0
T11 2140 9 0 0
T12 242320 1250 0 0
T13 0 52 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 457995 0 0
T1 154248 107 0 0
T2 32515 629 0 0
T3 140399 319 0 0
T4 109251 0 0 0
T7 364322 253 0 0
T8 244642 180 0 0
T9 8292 37 0 0
T10 9980 50 0 0
T11 2140 0 0 0
T12 242320 776 0 0
T13 0 52 0 0
T15 0 292 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4323366 0 0
T1 154248 902 0 0
T2 32515 933 0 0
T3 140399 17160 0 0
T4 109251 0 0 0
T7 364322 1493 0 0
T8 244642 17811 0 0
T9 8292 75 0 0
T10 9980 104 0 0
T11 2140 8 0 0
T12 242320 4502 0 0
T13 0 104 0 0

Line Coverage for Instance : tb.dut.u_sm1_50
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_50
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 293605 0 0
gen_host_fifo[1].idInRange 435744204 401442 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4428721 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 293605 0 0
T1 154248 114 0 0
T2 32515 195 0 0
T3 140399 28 0 0
T4 109251 0 0 0
T7 364322 232 0 0
T8 244642 137 0 0
T9 8292 29 0 0
T10 9980 53 0 0
T11 2140 4 0 0
T12 242320 210 0 0
T13 0 54 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 401442 0 0
T1 154248 96 0 0
T2 32515 218 0 0
T3 140399 2501 0 0
T4 109251 0 0 0
T7 364322 203 0 0
T8 244642 145 0 0
T9 8292 48 0 0
T10 9980 52 0 0
T11 2140 6 0 0
T12 242320 2817 0 0
T13 0 46 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4428721 0 0
T1 154248 820 0 0
T2 32515 397 0 0
T3 140399 8907 0 0
T4 109251 0 0 0
T7 364322 1416 0 0
T8 244642 15482 0 0
T9 8292 77 0 0
T10 9980 101 0 0
T11 2140 10 0 0
T12 242320 5527 0 0
T13 0 98 0 0

Line Coverage for Instance : tb.dut.u_sm1_51
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_51
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 335600 0 0
gen_host_fifo[1].idInRange 435744204 436051 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4625471 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 335600 0 0
T1 154248 137 0 0
T2 32515 273 0 0
T3 140399 883 0 0
T4 109251 0 0 0
T7 364322 6034 0 0
T8 244642 140 0 0
T9 8292 45 0 0
T10 9980 100 0 0
T11 2140 7 0 0
T12 242320 1772 0 0
T13 0 61 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 436051 0 0
T1 154248 124 0 0
T2 32515 241 0 0
T3 140399 776 0 0
T4 109251 0 0 0
T7 364322 7635 0 0
T8 244642 141 0 0
T9 8292 35 0 0
T10 9980 81 0 0
T11 2140 9 0 0
T12 242320 3271 0 0
T13 0 57 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4625471 0 0
T1 154248 1073 0 0
T2 32515 481 0 0
T3 140399 15914 0 0
T4 109251 0 0 0
T7 364322 3958 0 0
T8 244642 19417 0 0
T9 8292 78 0 0
T10 9980 166 0 0
T11 2140 16 0 0
T12 242320 4944 0 0
T13 0 117 0 0

Line Coverage for Instance : tb.dut.u_sm1_52
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_52
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 314556 0 0
gen_host_fifo[1].idInRange 435744204 422779 0 0
maxM 900 900 0 0
rspIdInRange 435744204 3903900 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 314556 0 0
T1 154248 133 0 0
T2 32515 212 0 0
T3 140399 636 0 0
T4 109251 0 0 0
T7 364322 1478 0 0
T8 244642 140 0 0
T9 8292 33 0 0
T10 9980 65 0 0
T11 2140 4 0 0
T12 242320 669 0 0
T13 0 53 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 422779 0 0
T1 154248 161 0 0
T2 32515 213 0 0
T3 140399 1893 0 0
T4 109251 0 0 0
T7 364322 2567 0 0
T8 244642 126 0 0
T9 8292 36 0 0
T10 9980 63 0 0
T11 2140 3 0 0
T12 242320 3024 0 0
T13 0 48 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 3903900 0 0
T1 154248 1077 0 0
T2 32515 403 0 0
T3 140399 13619 0 0
T4 109251 0 0 0
T7 364322 2882 0 0
T8 244642 19198 0 0
T9 8292 69 0 0
T10 9980 122 0 0
T11 2140 7 0 0
T12 242320 4086 0 0
T13 0 100 0 0

Line Coverage for Instance : tb.dut.u_sm1_53
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_53
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 295813 0 0
gen_host_fifo[1].idInRange 435744204 389688 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4820098 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 295813 0 0
T1 154248 2650 0 0
T2 32515 244 0 0
T3 140399 486 0 0
T4 109251 0 0 0
T7 364322 188 0 0
T8 244642 125 0 0
T9 8292 45 0 0
T10 9980 56 0 0
T11 2140 4 0 0
T12 242320 1250 0 0
T13 0 53 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 389688 0 0
T1 154248 2999 0 0
T2 32515 212 0 0
T3 140399 2537 0 0
T4 109251 0 0 0
T7 364322 266 0 0
T8 244642 125 0 0
T9 8292 46 0 0
T10 9980 50 0 0
T11 2140 7 0 0
T12 242320 2279 0 0
T13 0 35 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4820098 0 0
T1 154248 2258 0 0
T2 32515 434 0 0
T3 140399 15492 0 0
T4 109251 0 0 0
T7 364322 1387 0 0
T8 244642 15593 0 0
T9 8292 91 0 0
T10 9980 101 0 0
T11 2140 11 0 0
T12 242320 5587 0 0
T13 0 88 0 0

Line Coverage for Instance : tb.dut.u_sm1_54
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_54
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 381999 0 0
gen_host_fifo[1].idInRange 435744204 479374 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4812298 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 381999 0 0
T1 154248 113 0 0
T2 32515 219 0 0
T3 140399 39 0 0
T4 109251 2317 0 0
T7 364322 2719 0 0
T8 244642 135 0 0
T9 8292 59 0 0
T10 9980 75 0 0
T11 2140 8 0 0
T12 242320 565 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 479374 0 0
T1 154248 112 0 0
T2 32515 170 0 0
T3 140399 898 0 0
T4 109251 2952 0 0
T7 364322 3502 0 0
T8 244642 138 0 0
T9 8292 41 0 0
T10 9980 59 0 0
T11 2140 9 0 0
T12 242320 5640 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4812298 0 0
T1 154248 972 0 0
T2 32515 372 0 0
T3 140399 16502 0 0
T4 109251 1114 0 0
T7 364322 2491 0 0
T8 244642 19527 0 0
T9 8292 95 0 0
T10 9980 124 0 0
T11 2140 16 0 0
T12 242320 3874 0 0

Line Coverage for Instance : tb.dut.u_sm1_55
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_55
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T7,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 322160 0 0
gen_host_fifo[1].idInRange 435744204 422186 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4080408 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 322160 0 0
T1 154248 117 0 0
T2 32515 716 0 0
T3 140399 36 0 0
T4 109251 0 0 0
T7 364322 208 0 0
T8 244642 106 0 0
T9 8292 47 0 0
T10 9980 54 0 0
T11 2140 4 0 0
T12 242320 659 0 0
T13 0 66 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 422186 0 0
T1 154248 103 0 0
T2 32515 653 0 0
T3 140399 2211 0 0
T4 109251 0 0 0
T7 364322 222 0 0
T8 244642 164 0 0
T9 8292 51 0 0
T10 9980 65 0 0
T11 2140 3 0 0
T12 242320 2879 0 0
T13 0 40 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4080408 0 0
T1 154248 900 0 0
T2 32515 934 0 0
T3 140399 12760 0 0
T4 109251 0 0 0
T7 364322 1579 0 0
T8 244642 16776 0 0
T9 8292 98 0 0
T10 9980 112 0 0
T11 2140 6 0 0
T12 242320 4932 0 0
T13 0 103 0 0

Line Coverage for Instance : tb.dut.u_sm1_56
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_56
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 288820 0 0
gen_host_fifo[1].idInRange 435744204 389690 0 0
maxM 900 900 0 0
rspIdInRange 435744204 4585250 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 288820 0 0
T1 154248 115 0 0
T2 32515 229 0 0
T3 140399 673 0 0
T4 109251 5613 0 0
T7 364322 2831 0 0
T8 244642 117 0 0
T9 8292 44 0 0
T10 9980 44 0 0
T11 2140 9 0 0
T12 242320 2024 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 389690 0 0
T1 154248 118 0 0
T2 32515 225 0 0
T3 140399 2273 0 0
T4 109251 6994 0 0
T7 364322 3484 0 0
T8 244642 173 0 0
T9 8292 32 0 0
T10 9980 53 0 0
T11 2140 8 0 0
T12 242320 1511 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 4585250 0 0
T1 154248 963 0 0
T2 32515 428 0 0
T3 140399 13402 0 0
T4 109251 2417 0 0
T7 364322 2560 0 0
T8 244642 12096 0 0
T9 8292 76 0 0
T10 9980 94 0 0
T11 2140 16 0 0
T12 242320 5803 0 0

Line Coverage for Instance : tb.dut.u_sm1_30
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_30
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT13,T15,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT13,T15,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT13,T15,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT13,T15,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T3,T7
101CoveredT1,T2,T3
110CoveredT13,T15,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT13,T15,T18
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 435744204 10322667 0 0
gen_host_fifo[1].idInRange 435744204 1866069 0 0
gen_host_fifo[2].idInRange 435744204 2017786 0 0
maxM 900 900 0 0
rspIdInRange 435744204 23055596 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 10322667 0 0
T1 154248 6359 0 0
T2 32515 1692 0 0
T3 140399 83174 0 0
T4 109251 14236 0 0
T7 364322 20806 0 0
T8 244642 3258 0 0
T9 8292 274 0 0
T10 9980 299 0 0
T11 2140 41 0 0
T12 242320 181576 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 1866069 0 0
T1 154248 987 0 0
T2 32515 203 0 0
T3 140399 11327 0 0
T4 109251 9447 0 0
T7 364322 6503 0 0
T8 244642 408 0 0
T9 8292 39 0 0
T10 9980 67 0 0
T11 2140 7 0 0
T12 242320 30436 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 2017786 0 0
T1 154248 711 0 0
T2 32515 192 0 0
T3 140399 16599 0 0
T4 109251 9575 0 0
T7 364322 6500 0 0
T8 244642 642 0 0
T9 8292 35 0 0
T10 9980 60 0 0
T11 2140 6 0 0
T12 242320 31554 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 435744204 23055596 0 0
T1 154248 6973 0 0
T2 32515 2058 0 0
T3 140399 93500 0 0
T4 109251 11321 0 0
T7 364322 15367 0 0
T8 244642 279271 0 0
T9 8292 342 0 0
T10 9980 420 0 0
T11 2140 54 0 0
T12 242320 151063 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%