Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8017275	0	0
GntImpliesValid_A	2147483647	8017275	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8017275	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	469742661	0	0
ReadyAndValidImplyGrant_A	2147483647	8017275	0	0
ReqAndReadyImplyGrant_A	2147483647	8017275	0	0
ReqImpliesValid_A	2147483647	35448394	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46351	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8017275	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3701952	3697728	0	0
T2	780360	770064	0	0
T3	3369576	3369480	0	0
T4	2622024	2620296	0	0
T7	8743728	8741904	0	0
T8	5871408	5871336	0	0
T9	199008	198624	0	0
T10	239520	237816	0	0
T11	51360	49632	0	0
T12	5815680	5815680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8017275	0	0
T1	3701952	9348	0	0
T2	780360	18333	0	0
T3	3369576	3052	0	0
T4	2622024	10206	0	0
T7	8743728	26308	0	0
T8	5871408	8626	0	0
T9	199008	3067	0	0
T10	239520	3946	0	0
T11	51360	421	0	0
T12	5815680	6203	0	0
T13	0	1249	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8017275	0	0
T1	3701952	9348	0	0
T2	780360	18333	0	0
T3	3369576	3052	0	0
T4	2622024	10206	0	0
T7	8743728	26308	0	0
T8	5871408	8626	0	0
T9	199008	3067	0	0
T10	239520	3946	0	0
T11	51360	421	0	0
T12	5815680	6203	0	0
T13	0	1249	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3701952	3697728	0	0
T2	780360	770064	0	0
T3	3369576	3369480	0	0
T4	2622024	2620296	0	0
T7	8743728	8741904	0	0
T8	5871408	5871336	0	0
T9	199008	198624	0	0
T10	239520	237816	0	0
T11	51360	49632	0	0
T12	5815680	5815680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3701952	3697728	0	0
T2	780360	770064	0	0
T3	3369576	3369480	0	0
T4	2622024	2620296	0	0
T7	8743728	8741904	0	0
T8	5871408	5871336	0	0
T9	199008	198624	0	0
T10	239520	237816	0	0
T11	51360	49632	0	0
T12	5815680	5815680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8017275	0	0
T1	3701952	9348	0	0
T2	780360	18333	0	0
T3	3369576	3052	0	0
T4	2622024	10206	0	0
T7	8743728	26308	0	0
T8	5871408	8626	0	0
T9	199008	3067	0	0
T10	239520	3946	0	0
T11	51360	421	0	0
T12	5815680	6203	0	0
T13	0	1249	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	469742661	0	0
T1	3701952	199535	0	0
T2	780360	20362	0	0
T3	3369576	1142574	0	0
T4	2622024	106842	0	0
T7	8743728	461599	0	0
T8	5871408	239577	0	0
T9	199008	3568	0	0
T10	239520	5028	0	0
T11	51360	556	0	0
T12	5815680	1910143	0	0
T13	0	3291	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8017275	0	0
T1	3701952	9348	0	0
T2	780360	18333	0	0
T3	3369576	3052	0	0
T4	2622024	10206	0	0
T7	8743728	26308	0	0
T8	5871408	8626	0	0
T9	199008	3067	0	0
T10	239520	3946	0	0
T11	51360	421	0	0
T12	5815680	6203	0	0
T13	0	1249	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8017275	0	0
T1	3701952	9348	0	0
T2	780360	18333	0	0
T3	3369576	3052	0	0
T4	2622024	10206	0	0
T7	8743728	26308	0	0
T8	5871408	8626	0	0
T9	199008	3067	0	0
T10	239520	3946	0	0
T11	51360	421	0	0
T12	5815680	6203	0	0
T13	0	1249	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35448394	0	0
T1	3701952	23963	0	0
T2	780360	21734	0	0
T3	3369576	190501	0	0
T4	2622024	70476	0	0
T7	8743728	115656	0	0
T8	5871408	14361	0	0
T9	199008	3149	0	0
T10	239520	4335	0	0
T11	51360	468	0	0
T12	5815680	368484	0	0
T13	0	1342	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46351	0	21600
T1	154248	1	0	1
T2	65030	71	0	2
T3	280798	0	0	2
T4	218502	27	0	2
T5	0	100	0	0
T7	728644	19	0	2
T8	489284	0	0	2
T9	16584	13	0	2
T10	19960	19	0	2
T11	4280	0	0	2
T12	484640	0	0	2
T13	12025	14	0	1
T14	0	66	0	0
T15	0	365	0	0
T16	0	2449	0	0
T17	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3701952	3697728	0	0
T2	780360	770064	0	0
T3	3369576	3369480	0	0
T4	2622024	2620296	0	0
T7	8743728	8741904	0	0
T8	5871408	5871336	0	0
T9	199008	198624	0	0
T10	239520	237816	0	0
T11	51360	49632	0	0
T12	5815680	5815680	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8017275	0	0
T1	3701952	9348	0	0
T2	780360	18333	0	0
T3	3369576	3052	0	0
T4	2622024	10206	0	0
T7	8743728	26308	0	0
T8	5871408	8626	0	0
T9	199008	3067	0	0
T10	239520	3946	0	0
T11	51360	421	0	0
T12	5815680	6203	0	0
T13	0	1249	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	907553	0	0
GntImpliesValid_A	435744204	907553	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	907553	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	12078625	0	0
ReadyAndValidImplyGrant_A	435744204	907553	0	0
ReqAndReadyImplyGrant_A	435744204	907553	0	0
ReqImpliesValid_A	435744204	2558382	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	907553	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	907553	0	0
T1	154248	959	0	0
T2	32515	1982	0	0
T3	140399	307	0	0
T4	109251	1304	0	0
T7	364322	2520	0	0
T8	244642	931	0	0
T9	8292	368	0	0
T10	9980	440	0	0
T11	2140	50	0	0
T12	242320	646	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	907553	0	0
T1	154248	959	0	0
T2	32515	1982	0	0
T3	140399	307	0	0
T4	109251	1304	0	0
T7	364322	2520	0	0
T8	244642	931	0	0
T9	8292	368	0	0
T10	9980	440	0	0
T11	2140	50	0	0
T12	242320	646	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	907553	0	0
T1	154248	959	0	0
T2	32515	1982	0	0
T3	140399	307	0	0
T4	109251	1304	0	0
T7	364322	2520	0	0
T8	244642	931	0	0
T9	8292	368	0	0
T10	9980	440	0	0
T11	2140	50	0	0
T12	242320	646	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	12078625	0	0
T1	154248	7195	0	0
T2	32515	1587	0	0
T3	140399	98218	0	0
T4	109251	5377	0	0
T7	364322	17776	0	0
T8	244642	3991	0	0
T9	8292	355	0	0
T10	9980	366	0	0
T11	2140	43	0	0
T12	242320	211824	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	907553	0	0
T1	154248	959	0	0
T2	32515	1982	0	0
T3	140399	307	0	0
T4	109251	1304	0	0
T7	364322	2520	0	0
T8	244642	931	0	0
T9	8292	368	0	0
T10	9980	440	0	0
T11	2140	50	0	0
T12	242320	646	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	907553	0	0
T1	154248	959	0	0
T2	32515	1982	0	0
T3	140399	307	0	0
T4	109251	1304	0	0
T7	364322	2520	0	0
T8	244642	931	0	0
T9	8292	368	0	0
T10	9980	440	0	0
T11	2140	50	0	0
T12	242320	646	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	2558382	0	0
T1	154248	1222	0	0
T2	32515	2385	0	0
T3	140399	10885	0	0
T4	109251	3646	0	0
T7	364322	3347	0	0
T8	244642	1277	0	0
T9	8292	382	0	0
T10	9980	515	0	0
T11	2140	58	0	0
T12	242320	25807	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	907553	0	0
T1	154248	959	0	0
T2	32515	1982	0	0
T3	140399	307	0	0
T4	109251	1304	0	0
T7	364322	2520	0	0
T8	244642	931	0	0
T9	8292	368	0	0
T10	9980	440	0	0
T11	2140	50	0	0
T12	242320	646	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	893252	0	0
GntImpliesValid_A	435744204	893252	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	893252	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	12313759	0	0
ReadyAndValidImplyGrant_A	435744204	893252	0	0
ReqAndReadyImplyGrant_A	435744204	893252	0	0
ReqImpliesValid_A	435744204	2546504	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	893252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	893252	0	0
T1	154248	964	0	0
T2	32515	2027	0	0
T3	140399	307	0	0
T4	109251	1433	0	0
T7	364322	3232	0	0
T8	244642	939	0	0
T9	8292	362	0	0
T10	9980	469	0	0
T11	2140	47	0	0
T12	242320	696	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	893252	0	0
T1	154248	964	0	0
T2	32515	2027	0	0
T3	140399	307	0	0
T4	109251	1433	0	0
T7	364322	3232	0	0
T8	244642	939	0	0
T9	8292	362	0	0
T10	9980	469	0	0
T11	2140	47	0	0
T12	242320	696	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	893252	0	0
T1	154248	964	0	0
T2	32515	2027	0	0
T3	140399	307	0	0
T4	109251	1433	0	0
T7	364322	3232	0	0
T8	244642	939	0	0
T9	8292	362	0	0
T10	9980	469	0	0
T11	2140	47	0	0
T12	242320	696	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	12313759	0	0
T1	154248	7460	0	0
T2	32515	1578	0	0
T3	140399	89993	0	0
T4	109251	5687	0	0
T7	364322	20071	0	0
T8	244642	3812	0	0
T9	8292	349	0	0
T10	9980	394	0	0
T11	2140	43	0	0
T12	242320	228339	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	893252	0	0
T1	154248	964	0	0
T2	32515	2027	0	0
T3	140399	307	0	0
T4	109251	1433	0	0
T7	364322	3232	0	0
T8	244642	939	0	0
T9	8292	362	0	0
T10	9980	469	0	0
T11	2140	47	0	0
T12	242320	696	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	893252	0	0
T1	154248	964	0	0
T2	32515	2027	0	0
T3	140399	307	0	0
T4	109251	1433	0	0
T7	364322	3232	0	0
T8	244642	939	0	0
T9	8292	362	0	0
T10	9980	469	0	0
T11	2140	47	0	0
T12	242320	696	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	2546504	0	0
T1	154248	1146	0	0
T2	32515	2484	0	0
T3	140399	5932	0	0
T4	109251	9148	0	0
T7	364322	10240	0	0
T8	244642	1262	0	0
T9	8292	376	0	0
T10	9980	545	0	0
T11	2140	52	0	0
T12	242320	25917	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	893252	0	0
T1	154248	964	0	0
T2	32515	2027	0	0
T3	140399	307	0	0
T4	109251	1433	0	0
T7	364322	3232	0	0
T8	244642	939	0	0
T9	8292	362	0	0
T10	9980	469	0	0
T11	2140	47	0	0
T12	242320	696	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	215431	0	0
GntImpliesValid_A	435744204	215431	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	215431	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3010427	0	0
ReadyAndValidImplyGrant_A	435744204	215431	0	0
ReqAndReadyImplyGrant_A	435744204	215431	0	0
ReqImpliesValid_A	435744204	610656	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	215431	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	215431	0	0
T1	154248	212	0	0
T2	32515	406	0	0
T3	140399	87	0	0
T4	109251	454	0	0
T7	364322	1361	0	0
T8	244642	279	0	0
T9	8292	89	0	0
T10	9980	116	0	0
T11	2140	8	0	0
T12	242320	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	215431	0	0
T1	154248	212	0	0
T2	32515	406	0	0
T3	140399	87	0	0
T4	109251	454	0	0
T7	364322	1361	0	0
T8	244642	279	0	0
T9	8292	89	0	0
T10	9980	116	0	0
T11	2140	8	0	0
T12	242320	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	215431	0	0
T1	154248	212	0	0
T2	32515	406	0	0
T3	140399	87	0	0
T4	109251	454	0	0
T7	364322	1361	0	0
T8	244642	279	0	0
T9	8292	89	0	0
T10	9980	116	0	0
T11	2140	8	0	0
T12	242320	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3010427	0	0
T1	154248	1614	0	0
T2	32515	395	0	0
T3	140399	28157	0	0
T4	109251	885	0	0
T7	364322	4977	0	0
T8	244642	1279	0	0
T9	8292	90	0	0
T10	9980	111	0	0
T11	2140	9	0	0
T12	242320	55420	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	215431	0	0
T1	154248	212	0	0
T2	32515	406	0	0
T3	140399	87	0	0
T4	109251	454	0	0
T7	364322	1361	0	0
T8	244642	279	0	0
T9	8292	89	0	0
T10	9980	116	0	0
T11	2140	8	0	0
T12	242320	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	215431	0	0
T1	154248	212	0	0
T2	32515	406	0	0
T3	140399	87	0	0
T4	109251	454	0	0
T7	364322	1361	0	0
T8	244642	279	0	0
T9	8292	89	0	0
T10	9980	116	0	0
T11	2140	8	0	0
T12	242320	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	610656	0	0
T1	154248	238	0	0
T2	32515	425	0	0
T3	140399	742	0	0
T4	109251	4108	0	0
T7	364322	4616	0	0
T8	244642	357	0	0
T9	8292	89	0	0
T10	9980	122	0	0
T11	2140	8	0	0
T12	242320	3136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	215431	0	0
T1	154248	212	0	0
T2	32515	406	0	0
T3	140399	87	0	0
T4	109251	454	0	0
T7	364322	1361	0	0
T8	244642	279	0	0
T9	8292	89	0	0
T10	9980	116	0	0
T11	2140	8	0	0
T12	242320	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	218656	0	0
GntImpliesValid_A	435744204	218656	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	218656	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3055253	0	0
ReadyAndValidImplyGrant_A	435744204	218656	0	0
ReqAndReadyImplyGrant_A	435744204	218656	0	0
ReqImpliesValid_A	435744204	598606	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	218656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	218656	0	0
T1	154248	251	0	0
T2	32515	738	0	0
T3	140399	79	0	0
T4	109251	0	0	0
T7	364322	412	0	0
T8	244642	256	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	13	0	0
T12	242320	178	0	0
T13	0	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	218656	0	0
T1	154248	251	0	0
T2	32515	738	0	0
T3	140399	79	0	0
T4	109251	0	0	0
T7	364322	412	0	0
T8	244642	256	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	13	0	0
T12	242320	178	0	0
T13	0	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	218656	0	0
T1	154248	251	0	0
T2	32515	738	0	0
T3	140399	79	0	0
T4	109251	0	0	0
T7	364322	412	0	0
T8	244642	256	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	13	0	0
T12	242320	178	0	0
T13	0	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3055253	0	0
T1	154248	1890	0	0
T2	32515	678	0	0
T3	140399	27996	0	0
T4	109251	1	0	0
T7	364322	2950	0	0
T8	244642	1092	0	0
T9	8292	80	0	0
T10	9980	99	0	0
T11	2140	14	0	0
T12	242320	61199	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	218656	0	0
T1	154248	251	0	0
T2	32515	738	0	0
T3	140399	79	0	0
T4	109251	0	0	0
T7	364322	412	0	0
T8	244642	256	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	13	0	0
T12	242320	178	0	0
T13	0	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	218656	0	0
T1	154248	251	0	0
T2	32515	738	0	0
T3	140399	79	0	0
T4	109251	0	0	0
T7	364322	412	0	0
T8	244642	256	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	13	0	0
T12	242320	178	0	0
T13	0	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	598606	0	0
T1	154248	254	0	0
T2	32515	806	0	0
T3	140399	1353	0	0
T4	109251	0	0	0
T7	364322	447	0	0
T8	244642	338	0	0
T9	8292	79	0	0
T10	9980	106	0	0
T11	2140	13	0	0
T12	242320	1993	0	0
T13	0	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	218656	0	0
T1	154248	251	0	0
T2	32515	738	0	0
T3	140399	79	0	0
T4	109251	0	0	0
T7	364322	412	0	0
T8	244642	256	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	13	0	0
T12	242320	178	0	0
T13	0	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	217112	0	0
GntImpliesValid_A	435744204	217112	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	217112	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	4987481	0	0
ReadyAndValidImplyGrant_A	435744204	217112	0	0
ReqAndReadyImplyGrant_A	435744204	217112	0	0
ReqImpliesValid_A	435744204	1198765	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	217112	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	217112	0	0
T1	154248	225	0	0
T2	32515	1115	0	0
T3	140399	83	0	0
T4	109251	0	0	0
T7	364322	1960	0	0
T8	244642	257	0	0
T9	8292	94	0	0
T10	9980	92	0	0
T11	2140	9	0	0
T12	242320	175	0	0
T13	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	217112	0	0
T1	154248	225	0	0
T2	32515	1115	0	0
T3	140399	83	0	0
T4	109251	0	0	0
T7	364322	1960	0	0
T8	244642	257	0	0
T9	8292	94	0	0
T10	9980	92	0	0
T11	2140	9	0	0
T12	242320	175	0	0
T13	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	217112	0	0
T1	154248	225	0	0
T2	32515	1115	0	0
T3	140399	83	0	0
T4	109251	0	0	0
T7	364322	1960	0	0
T8	244642	257	0	0
T9	8292	94	0	0
T10	9980	92	0	0
T11	2140	9	0	0
T12	242320	175	0	0
T13	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	4987481	0	0
T1	154248	4128	0	0
T2	32515	3801	0	0
T3	140399	12813	0	0
T4	109251	0	0	0
T7	364322	16497	0	0
T8	244642	2179	0	0
T9	8292	495	0	0
T10	9980	535	0	0
T11	2140	52	0	0
T12	242320	13941	0	0
T13	0	1389	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	217112	0	0
T1	154248	225	0	0
T2	32515	1115	0	0
T3	140399	83	0	0
T4	109251	0	0	0
T7	364322	1960	0	0
T8	244642	257	0	0
T9	8292	94	0	0
T10	9980	92	0	0
T11	2140	9	0	0
T12	242320	175	0	0
T13	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	217112	0	0
T1	154248	225	0	0
T2	32515	1115	0	0
T3	140399	83	0	0
T4	109251	0	0	0
T7	364322	1960	0	0
T8	244642	257	0	0
T9	8292	94	0	0
T10	9980	92	0	0
T11	2140	9	0	0
T12	242320	175	0	0
T13	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	1198765	0	0
T1	154248	227	0	0
T2	32515	2475	0	0
T3	140399	393	0	0
T4	109251	0	0	0
T7	364322	25132	0	0
T8	244642	395	0	0
T9	8292	120	0	0
T10	9980	126	0	0
T11	2140	9	0	0
T12	242320	893	0	0
T13	0	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	217112	0	0
T1	154248	225	0	0
T2	32515	1115	0	0
T3	140399	83	0	0
T4	109251	0	0	0
T7	364322	1960	0	0
T8	244642	257	0	0
T9	8292	94	0	0
T10	9980	92	0	0
T11	2140	9	0	0
T12	242320	175	0	0
T13	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	220937	0	0
GntImpliesValid_A	435744204	220937	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	220937	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	4946008	0	0
ReadyAndValidImplyGrant_A	435744204	220937	0	0
ReqAndReadyImplyGrant_A	435744204	220937	0	0
ReqImpliesValid_A	435744204	1112625	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	220937	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	220937	0	0
T1	154248	215	0	0
T2	32515	396	0	0
T3	140399	85	0	0
T4	109251	0	0	0
T7	364322	397	0	0
T8	244642	249	0	0
T9	8292	93	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	200	0	0
T13	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	220937	0	0
T1	154248	215	0	0
T2	32515	396	0	0
T3	140399	85	0	0
T4	109251	0	0	0
T7	364322	397	0	0
T8	244642	249	0	0
T9	8292	93	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	200	0	0
T13	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	220937	0	0
T1	154248	215	0	0
T2	32515	396	0	0
T3	140399	85	0	0
T4	109251	0	0	0
T7	364322	397	0	0
T8	244642	249	0	0
T9	8292	93	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	200	0	0
T13	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	4946008	0	0
T1	154248	4445	0	0
T2	32515	1809	0	0
T3	140399	131139	0	0
T4	109251	0	0	0
T7	364322	7283	0	0
T8	244642	1452	0	0
T9	8292	350	0	0
T10	9980	650	0	0
T11	2140	118	0	0
T12	242320	11612	0	0
T13	0	951	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	220937	0	0
T1	154248	215	0	0
T2	32515	396	0	0
T3	140399	85	0	0
T4	109251	0	0	0
T7	364322	397	0	0
T8	244642	249	0	0
T9	8292	93	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	200	0	0
T13	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	220937	0	0
T1	154248	215	0	0
T2	32515	396	0	0
T3	140399	85	0	0
T4	109251	0	0	0
T7	364322	397	0	0
T8	244642	249	0	0
T9	8292	93	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	200	0	0
T13	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	1112625	0	0
T1	154248	264	0	0
T2	32515	557	0	0
T3	140399	11629	0	0
T4	109251	0	0	0
T7	364322	463	0	0
T8	244642	333	0	0
T9	8292	103	0	0
T10	9980	154	0	0
T11	2140	19	0	0
T12	242320	1297	0	0
T13	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	220937	0	0
T1	154248	215	0	0
T2	32515	396	0	0
T3	140399	85	0	0
T4	109251	0	0	0
T7	364322	397	0	0
T8	244642	249	0	0
T9	8292	93	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	200	0	0
T13	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	219338	0	0
GntImpliesValid_A	435744204	219338	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	219338	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	4643036	0	0
ReadyAndValidImplyGrant_A	435744204	219338	0	0
ReqAndReadyImplyGrant_A	435744204	219338	0	0
ReqImpliesValid_A	435744204	1130488	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	219338	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219338	0	0
T1	154248	214	0	0
T2	32515	409	0	0
T3	140399	96	0	0
T4	109251	0	0	0
T7	364322	432	0	0
T8	244642	241	0	0
T9	8292	55	0	0
T10	9980	112	0	0
T11	2140	12	0	0
T12	242320	162	0	0
T13	0	99	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219338	0	0
T1	154248	214	0	0
T2	32515	409	0	0
T3	140399	96	0	0
T4	109251	0	0	0
T7	364322	432	0	0
T8	244642	241	0	0
T9	8292	55	0	0
T10	9980	112	0	0
T11	2140	12	0	0
T12	242320	162	0	0
T13	0	99	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219338	0	0
T1	154248	214	0	0
T2	32515	409	0	0
T3	140399	96	0	0
T4	109251	0	0	0
T7	364322	432	0	0
T8	244642	241	0	0
T9	8292	55	0	0
T10	9980	112	0	0
T11	2140	12	0	0
T12	242320	162	0	0
T13	0	99	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	4643036	0	0
T1	154248	2488	0	0
T2	32515	2417	0	0
T3	140399	90218	0	0
T4	109251	0	0	0
T7	364322	2748	0	0
T8	244642	2801	0	0
T9	8292	208	0	0
T10	9980	617	0	0
T11	2140	69	0	0
T12	242320	12223	0	0
T13	0	951	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219338	0	0
T1	154248	214	0	0
T2	32515	409	0	0
T3	140399	96	0	0
T4	109251	0	0	0
T7	364322	432	0	0
T8	244642	241	0	0
T9	8292	55	0	0
T10	9980	112	0	0
T11	2140	12	0	0
T12	242320	162	0	0
T13	0	99	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219338	0	0
T1	154248	214	0	0
T2	32515	409	0	0
T3	140399	96	0	0
T4	109251	0	0	0
T7	364322	432	0	0
T8	244642	241	0	0
T9	8292	55	0	0
T10	9980	112	0	0
T11	2140	12	0	0
T12	242320	162	0	0
T13	0	99	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	1130488	0	0
T1	154248	240	0	0
T2	32515	614	0	0
T3	140399	8220	0	0
T4	109251	0	0	0
T7	364322	451	0	0
T8	244642	499	0	0
T9	8292	55	0	0
T10	9980	138	0	0
T11	2140	35	0	0
T12	242320	805	0	0
T13	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219338	0	0
T1	154248	214	0	0
T2	32515	409	0	0
T3	140399	96	0	0
T4	109251	0	0	0
T7	364322	432	0	0
T8	244642	241	0	0
T9	8292	55	0	0
T10	9980	112	0	0
T11	2140	12	0	0
T12	242320	162	0	0
T13	0	99	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	231944	0	0
GntImpliesValid_A	435744204	231944	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	231944	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	4912868	0	0
ReadyAndValidImplyGrant_A	435744204	231944	0	0
ReqAndReadyImplyGrant_A	435744204	231944	0	0
ReqImpliesValid_A	435744204	1408703	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	231944	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	231944	0	0
T1	154248	742	0	0
T2	32515	401	0	0
T3	140399	97	0	0
T4	109251	502	0	0
T7	364322	433	0	0
T8	244642	227	0	0
T9	8292	78	0	0
T10	9980	121	0	0
T11	2140	6	0	0
T12	242320	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	231944	0	0
T1	154248	742	0	0
T2	32515	401	0	0
T3	140399	97	0	0
T4	109251	502	0	0
T7	364322	433	0	0
T8	244642	227	0	0
T9	8292	78	0	0
T10	9980	121	0	0
T11	2140	6	0	0
T12	242320	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	231944	0	0
T1	154248	742	0	0
T2	32515	401	0	0
T3	140399	97	0	0
T4	109251	502	0	0
T7	364322	433	0	0
T8	244642	227	0	0
T9	8292	78	0	0
T10	9980	121	0	0
T11	2140	6	0	0
T12	242320	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	4912868	0	0
T1	154248	5159	0	0
T2	32515	1844	0	0
T3	140399	31379	0	0
T4	109251	1256	0	0
T7	364322	9603	0	0
T8	244642	2296	0	0
T9	8292	493	0	0
T10	9980	764	0	0
T11	2140	47	0	0
T12	242320	54495	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	231944	0	0
T1	154248	742	0	0
T2	32515	401	0	0
T3	140399	97	0	0
T4	109251	502	0	0
T7	364322	433	0	0
T8	244642	227	0	0
T9	8292	78	0	0
T10	9980	121	0	0
T11	2140	6	0	0
T12	242320	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	231944	0	0
T1	154248	742	0	0
T2	32515	401	0	0
T3	140399	97	0	0
T4	109251	502	0	0
T7	364322	433	0	0
T8	244642	227	0	0
T9	8292	78	0	0
T10	9980	121	0	0
T11	2140	6	0	0
T12	242320	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	1408703	0	0
T1	154248	4006	0	0
T2	32515	496	0	0
T3	140399	1892	0	0
T4	109251	4285	0	0
T7	364322	727	0	0
T8	244642	432	0	0
T9	8292	86	0	0
T10	9980	162	0	0
T11	2140	6	0	0
T12	242320	3931	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	231944	0	0
T1	154248	742	0	0
T2	32515	401	0	0
T3	140399	97	0	0
T4	109251	502	0	0
T7	364322	433	0	0
T8	244642	227	0	0
T9	8292	78	0	0
T10	9980	121	0	0
T11	2140	6	0	0
T12	242320	159	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	210101	0	0
GntImpliesValid_A	435744204	210101	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	210101	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	2940528	0	0
ReadyAndValidImplyGrant_A	435744204	210101	0	0
ReqAndReadyImplyGrant_A	435744204	210101	0	0
ReqImpliesValid_A	435744204	543566	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	210101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	210101	0	0
T1	154248	254	0	0
T2	32515	397	0	0
T3	140399	78	0	0
T4	109251	508	0	0
T7	364322	386	0	0
T8	244642	223	0	0
T9	8292	83	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	210101	0	0
T1	154248	254	0	0
T2	32515	397	0	0
T3	140399	78	0	0
T4	109251	508	0	0
T7	364322	386	0	0
T8	244642	223	0	0
T9	8292	83	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	210101	0	0
T1	154248	254	0	0
T2	32515	397	0	0
T3	140399	78	0	0
T4	109251	508	0	0
T7	364322	386	0	0
T8	244642	223	0	0
T9	8292	83	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	2940528	0	0
T1	154248	1979	0	0
T2	32515	386	0	0
T3	140399	23450	0	0
T4	109251	1007	0	0
T7	364322	2901	0	0
T8	244642	966	0	0
T9	8292	84	0	0
T10	9980	97	0	0
T11	2140	14	0	0
T12	242320	54852	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	210101	0	0
T1	154248	254	0	0
T2	32515	397	0	0
T3	140399	78	0	0
T4	109251	508	0	0
T7	364322	386	0	0
T8	244642	223	0	0
T9	8292	83	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	210101	0	0
T1	154248	254	0	0
T2	32515	397	0	0
T3	140399	78	0	0
T4	109251	508	0	0
T7	364322	386	0	0
T8	244642	223	0	0
T9	8292	83	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	543566	0	0
T1	154248	268	0	0
T2	32515	416	0	0
T3	140399	78	0	0
T4	109251	4725	0	0
T7	364322	437	0	0
T8	244642	273	0	0
T9	8292	83	0	0
T10	9980	104	0	0
T11	2140	13	0	0
T12	242320	2768	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	210101	0	0
T1	154248	254	0	0
T2	32515	397	0	0
T3	140399	78	0	0
T4	109251	508	0	0
T7	364322	386	0	0
T8	244642	223	0	0
T9	8292	83	0	0
T10	9980	100	0	0
T11	2140	13	0	0
T12	242320	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	207883	0	0
GntImpliesValid_A	435744204	207883	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	207883	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	2983302	0	0
ReadyAndValidImplyGrant_A	435744204	207883	0	0
ReqAndReadyImplyGrant_A	435744204	207883	0	0
ReqImpliesValid_A	435744204	531317	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	207883	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	207883	0	0
T1	154248	197	0	0
T2	32515	391	0	0
T3	140399	84	0	0
T4	109251	913	0	0
T7	364322	969	0	0
T8	244642	231	0	0
T9	8292	75	0	0
T10	9980	114	0	0
T11	2140	10	0	0
T12	242320	185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	207883	0	0
T1	154248	197	0	0
T2	32515	391	0	0
T3	140399	84	0	0
T4	109251	913	0	0
T7	364322	969	0	0
T8	244642	231	0	0
T9	8292	75	0	0
T10	9980	114	0	0
T11	2140	10	0	0
T12	242320	185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	207883	0	0
T1	154248	197	0	0
T2	32515	391	0	0
T3	140399	84	0	0
T4	109251	913	0	0
T7	364322	969	0	0
T8	244642	231	0	0
T9	8292	75	0	0
T10	9980	114	0	0
T11	2140	10	0	0
T12	242320	185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	2983302	0	0
T1	154248	1495	0	0
T2	32515	379	0	0
T3	140399	27373	0	0
T4	109251	1934	0	0
T7	364322	4668	0	0
T8	244642	949	0	0
T9	8292	75	0	0
T10	9980	109	0	0
T11	2140	11	0	0
T12	242320	62659	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	207883	0	0
T1	154248	197	0	0
T2	32515	391	0	0
T3	140399	84	0	0
T4	109251	913	0	0
T7	364322	969	0	0
T8	244642	231	0	0
T9	8292	75	0	0
T10	9980	114	0	0
T11	2140	10	0	0
T12	242320	185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	207883	0	0
T1	154248	197	0	0
T2	32515	391	0	0
T3	140399	84	0	0
T4	109251	913	0	0
T7	364322	969	0	0
T8	244642	231	0	0
T9	8292	75	0	0
T10	9980	114	0	0
T11	2140	10	0	0
T12	242320	185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	531317	0	0
T1	154248	226	0	0
T2	32515	411	0	0
T3	140399	1034	0	0
T4	109251	4007	0	0
T7	364322	5158	0	0
T8	244642	294	0	0
T9	8292	76	0	0
T10	9980	120	0	0
T11	2140	10	0	0
T12	242320	3311	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	207883	0	0
T1	154248	197	0	0
T2	32515	391	0	0
T3	140399	84	0	0
T4	109251	913	0	0
T7	364322	969	0	0
T8	244642	231	0	0
T9	8292	75	0	0
T10	9980	114	0	0
T11	2140	10	0	0
T12	242320	185	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	219933	0	0
GntImpliesValid_A	435744204	219933	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	219933	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3048583	0	0
ReadyAndValidImplyGrant_A	435744204	219933	0	0
ReqAndReadyImplyGrant_A	435744204	219933	0	0
ReqImpliesValid_A	435744204	589617	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	219933	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219933	0	0
T1	154248	231	0	0
T2	32515	399	0	0
T3	140399	88	0	0
T4	109251	0	0	0
T7	364322	441	0	0
T8	244642	244	0	0
T9	8292	78	0	0
T10	9980	93	0	0
T11	2140	6	0	0
T12	242320	163	0	0
T13	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219933	0	0
T1	154248	231	0	0
T2	32515	399	0	0
T3	140399	88	0	0
T4	109251	0	0	0
T7	364322	441	0	0
T8	244642	244	0	0
T9	8292	78	0	0
T10	9980	93	0	0
T11	2140	6	0	0
T12	242320	163	0	0
T13	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219933	0	0
T1	154248	231	0	0
T2	32515	399	0	0
T3	140399	88	0	0
T4	109251	0	0	0
T7	364322	441	0	0
T8	244642	244	0	0
T9	8292	78	0	0
T10	9980	93	0	0
T11	2140	6	0	0
T12	242320	163	0	0
T13	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3048583	0	0
T1	154248	1667	0	0
T2	32515	381	0	0
T3	140399	29936	0	0
T4	109251	1	0	0
T7	364322	3206	0	0
T8	244642	1047	0	0
T9	8292	78	0	0
T10	9980	85	0	0
T11	2140	7	0	0
T12	242320	50375	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219933	0	0
T1	154248	231	0	0
T2	32515	399	0	0
T3	140399	88	0	0
T4	109251	0	0	0
T7	364322	441	0	0
T8	244642	244	0	0
T9	8292	78	0	0
T10	9980	93	0	0
T11	2140	6	0	0
T12	242320	163	0	0
T13	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219933	0	0
T1	154248	231	0	0
T2	32515	399	0	0
T3	140399	88	0	0
T4	109251	0	0	0
T7	364322	441	0	0
T8	244642	244	0	0
T9	8292	78	0	0
T10	9980	93	0	0
T11	2140	6	0	0
T12	242320	163	0	0
T13	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	589617	0	0
T1	154248	253	0	0
T2	32515	425	0	0
T3	140399	530	0	0
T4	109251	0	0	0
T7	364322	479	0	0
T8	244642	324	0	0
T9	8292	79	0	0
T10	9980	102	0	0
T11	2140	6	0	0
T12	242320	1754	0	0
T13	0	116	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219933	0	0
T1	154248	231	0	0
T2	32515	399	0	0
T3	140399	88	0	0
T4	109251	0	0	0
T7	364322	441	0	0
T8	244642	244	0	0
T9	8292	78	0	0
T10	9980	93	0	0
T11	2140	6	0	0
T12	242320	163	0	0
T13	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	222070	0	0
GntImpliesValid_A	435744204	222070	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	222070	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3018779	0	0
ReadyAndValidImplyGrant_A	435744204	222070	0	0
ReqAndReadyImplyGrant_A	435744204	222070	0	0
ReqImpliesValid_A	435744204	577228	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	222070	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222070	0	0
T1	154248	224	0	0
T2	32515	413	0	0
T3	140399	88	0	0
T4	109251	524	0	0
T7	364322	413	0	0
T8	244642	263	0	0
T9	8292	75	0	0
T10	9980	111	0	0
T11	2140	13	0	0
T12	242320	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222070	0	0
T1	154248	224	0	0
T2	32515	413	0	0
T3	140399	88	0	0
T4	109251	524	0	0
T7	364322	413	0	0
T8	244642	263	0	0
T9	8292	75	0	0
T10	9980	111	0	0
T11	2140	13	0	0
T12	242320	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222070	0	0
T1	154248	224	0	0
T2	32515	413	0	0
T3	140399	88	0	0
T4	109251	524	0	0
T7	364322	413	0	0
T8	244642	263	0	0
T9	8292	75	0	0
T10	9980	111	0	0
T11	2140	13	0	0
T12	242320	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3018779	0	0
T1	154248	1680	0	0
T2	32515	410	0	0
T3	140399	25043	0	0
T4	109251	1153	0	0
T7	364322	3112	0	0
T8	244642	1103	0	0
T9	8292	76	0	0
T10	9980	111	0	0
T11	2140	14	0	0
T12	242320	56631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222070	0	0
T1	154248	224	0	0
T2	32515	413	0	0
T3	140399	88	0	0
T4	109251	524	0	0
T7	364322	413	0	0
T8	244642	263	0	0
T9	8292	75	0	0
T10	9980	111	0	0
T11	2140	13	0	0
T12	242320	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222070	0	0
T1	154248	224	0	0
T2	32515	413	0	0
T3	140399	88	0	0
T4	109251	524	0	0
T7	364322	413	0	0
T8	244642	263	0	0
T9	8292	75	0	0
T10	9980	111	0	0
T11	2140	13	0	0
T12	242320	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	577228	0	0
T1	154248	231	0	0
T2	32515	424	0	0
T3	140399	4296	0	0
T4	109251	2014	0	0
T7	364322	461	0	0
T8	244642	317	0	0
T9	8292	75	0	0
T10	9980	112	0	0
T11	2140	13	0	0
T12	242320	3159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222070	0	0
T1	154248	224	0	0
T2	32515	413	0	0
T3	140399	88	0	0
T4	109251	524	0	0
T7	364322	413	0	0
T8	244642	263	0	0
T9	8292	75	0	0
T10	9980	111	0	0
T11	2140	13	0	0
T12	242320	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	224646	0	0
GntImpliesValid_A	435744204	224646	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	224646	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3071639	0	0
ReadyAndValidImplyGrant_A	435744204	224646	0	0
ReqAndReadyImplyGrant_A	435744204	224646	0	0
ReqImpliesValid_A	435744204	616798	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	224646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	224646	0	0
T1	154248	220	0	0
T2	32515	394	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	392	0	0
T8	244642	223	0	0
T9	8292	81	0	0
T10	9980	96	0	0
T11	2140	7	0	0
T12	242320	211	0	0
T13	0	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	224646	0	0
T1	154248	220	0	0
T2	32515	394	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	392	0	0
T8	244642	223	0	0
T9	8292	81	0	0
T10	9980	96	0	0
T11	2140	7	0	0
T12	242320	211	0	0
T13	0	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	224646	0	0
T1	154248	220	0	0
T2	32515	394	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	392	0	0
T8	244642	223	0	0
T9	8292	81	0	0
T10	9980	96	0	0
T11	2140	7	0	0
T12	242320	211	0	0
T13	0	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3071639	0	0
T1	154248	1755	0	0
T2	32515	385	0	0
T3	140399	32924	0	0
T4	109251	1	0	0
T7	364322	3040	0	0
T8	244642	940	0	0
T9	8292	81	0	0
T10	9980	94	0	0
T11	2140	8	0	0
T12	242320	72760	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	224646	0	0
T1	154248	220	0	0
T2	32515	394	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	392	0	0
T8	244642	223	0	0
T9	8292	81	0	0
T10	9980	96	0	0
T11	2140	7	0	0
T12	242320	211	0	0
T13	0	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	224646	0	0
T1	154248	220	0	0
T2	32515	394	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	392	0	0
T8	244642	223	0	0
T9	8292	81	0	0
T10	9980	96	0	0
T11	2140	7	0	0
T12	242320	211	0	0
T13	0	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	616798	0	0
T1	154248	223	0	0
T2	32515	411	0	0
T3	140399	1742	0	0
T4	109251	0	0	0
T7	364322	429	0	0
T8	244642	232	0	0
T9	8292	82	0	0
T10	9980	99	0	0
T11	2140	7	0	0
T12	242320	3935	0	0
T13	0	103	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	224646	0	0
T1	154248	220	0	0
T2	32515	394	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	392	0	0
T8	244642	223	0	0
T9	8292	81	0	0
T10	9980	96	0	0
T11	2140	7	0	0
T12	242320	211	0	0
T13	0	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	238232	0	0
GntImpliesValid_A	435744204	238232	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	238232	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3084543	0	0
ReadyAndValidImplyGrant_A	435744204	238232	0	0
ReqAndReadyImplyGrant_A	435744204	238232	0	0
ReqImpliesValid_A	435744204	682488	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	238232	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	238232	0	0
T1	154248	207	0	0
T2	32515	388	0	0
T3	140399	92	0	0
T4	109251	585	0	0
T7	364322	859	0	0
T8	244642	256	0	0
T9	8292	91	0	0
T10	9980	111	0	0
T11	2140	11	0	0
T12	242320	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	238232	0	0
T1	154248	207	0	0
T2	32515	388	0	0
T3	140399	92	0	0
T4	109251	585	0	0
T7	364322	859	0	0
T8	244642	256	0	0
T9	8292	91	0	0
T10	9980	111	0	0
T11	2140	11	0	0
T12	242320	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	238232	0	0
T1	154248	207	0	0
T2	32515	388	0	0
T3	140399	92	0	0
T4	109251	585	0	0
T7	364322	859	0	0
T8	244642	256	0	0
T9	8292	91	0	0
T10	9980	111	0	0
T11	2140	11	0	0
T12	242320	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3084543	0	0
T1	154248	1690	0	0
T2	32515	383	0	0
T3	140399	25586	0	0
T4	109251	1481	0	0
T7	364322	4377	0	0
T8	244642	1098	0	0
T9	8292	91	0	0
T10	9980	108	0	0
T11	2140	11	0	0
T12	242320	56044	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	238232	0	0
T1	154248	207	0	0
T2	32515	388	0	0
T3	140399	92	0	0
T4	109251	585	0	0
T7	364322	859	0	0
T8	244642	256	0	0
T9	8292	91	0	0
T10	9980	111	0	0
T11	2140	11	0	0
T12	242320	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	238232	0	0
T1	154248	207	0	0
T2	32515	388	0	0
T3	140399	92	0	0
T4	109251	585	0	0
T7	364322	859	0	0
T8	244642	256	0	0
T9	8292	91	0	0
T10	9980	111	0	0
T11	2140	11	0	0
T12	242320	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	682488	0	0
T1	154248	209	0	0
T2	32515	401	0	0
T3	140399	2825	0	0
T4	109251	5139	0	0
T7	364322	4321	0	0
T8	244642	292	0	0
T9	8292	92	0	0
T10	9980	115	0	0
T11	2140	12	0	0
T12	242320	533	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	238232	0	0
T1	154248	207	0	0
T2	32515	388	0	0
T3	140399	92	0	0
T4	109251	585	0	0
T7	364322	859	0	0
T8	244642	256	0	0
T9	8292	91	0	0
T10	9980	111	0	0
T11	2140	11	0	0
T12	242320	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	223901	0	0
GntImpliesValid_A	435744204	223901	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	223901	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3093163	0	0
ReadyAndValidImplyGrant_A	435744204	223901	0	0
ReqAndReadyImplyGrant_A	435744204	223901	0	0
ReqImpliesValid_A	435744204	657427	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	223901	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	223901	0	0
T1	154248	210	0	0
T2	32515	933	0	0
T3	140399	90	0	0
T4	109251	0	0	0
T7	364322	407	0	0
T8	244642	248	0	0
T9	8292	75	0	0
T10	9980	104	0	0
T11	2140	8	0	0
T12	242320	169	0	0
T13	0	104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	223901	0	0
T1	154248	210	0	0
T2	32515	933	0	0
T3	140399	90	0	0
T4	109251	0	0	0
T7	364322	407	0	0
T8	244642	248	0	0
T9	8292	75	0	0
T10	9980	104	0	0
T11	2140	8	0	0
T12	242320	169	0	0
T13	0	104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	223901	0	0
T1	154248	210	0	0
T2	32515	933	0	0
T3	140399	90	0	0
T4	109251	0	0	0
T7	364322	407	0	0
T8	244642	248	0	0
T9	8292	75	0	0
T10	9980	104	0	0
T11	2140	8	0	0
T12	242320	169	0	0
T13	0	104	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3093163	0	0
T1	154248	1505	0	0
T2	32515	793	0	0
T3	140399	33242	0	0
T4	109251	1	0	0
T7	364322	3101	0	0
T8	244642	951	0	0
T9	8292	75	0	0
T10	9980	103	0	0
T11	2140	8	0	0
T12	242320	58449	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	223901	0	0
T1	154248	210	0	0
T2	32515	933	0	0
T3	140399	90	0	0
T4	109251	0	0	0
T7	364322	407	0	0
T8	244642	248	0	0
T9	8292	75	0	0
T10	9980	104	0	0
T11	2140	8	0	0
T12	242320	169	0	0
T13	0	104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	223901	0	0
T1	154248	210	0	0
T2	32515	933	0	0
T3	140399	90	0	0
T4	109251	0	0	0
T7	364322	407	0	0
T8	244642	248	0	0
T9	8292	75	0	0
T10	9980	104	0	0
T11	2140	8	0	0
T12	242320	169	0	0
T13	0	104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	657427	0	0
T1	154248	210	0	0
T2	32515	1081	0	0
T3	140399	739	0	0
T4	109251	0	0	0
T7	364322	451	0	0
T8	244642	302	0	0
T9	8292	76	0	0
T10	9980	106	0	0
T11	2140	9	0	0
T12	242320	2026	0	0
T13	0	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	223901	0	0
T1	154248	210	0	0
T2	32515	933	0	0
T3	140399	90	0	0
T4	109251	0	0	0
T7	364322	407	0	0
T8	244642	248	0	0
T9	8292	75	0	0
T10	9980	104	0	0
T11	2140	8	0	0
T12	242320	169	0	0
T13	0	104	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	219037	0	0
GntImpliesValid_A	435744204	219037	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	219037	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	2953264	0	0
ReadyAndValidImplyGrant_A	435744204	219037	0	0
ReqAndReadyImplyGrant_A	435744204	219037	0	0
ReqImpliesValid_A	435744204	583213	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	219037	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219037	0	0
T1	154248	201	0	0
T2	32515	397	0	0
T3	140399	87	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	250	0	0
T9	8292	77	0	0
T10	9980	101	0	0
T11	2140	10	0	0
T12	242320	178	0	0
T13	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219037	0	0
T1	154248	201	0	0
T2	32515	397	0	0
T3	140399	87	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	250	0	0
T9	8292	77	0	0
T10	9980	101	0	0
T11	2140	10	0	0
T12	242320	178	0	0
T13	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219037	0	0
T1	154248	201	0	0
T2	32515	397	0	0
T3	140399	87	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	250	0	0
T9	8292	77	0	0
T10	9980	101	0	0
T11	2140	10	0	0
T12	242320	178	0	0
T13	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	2953264	0	0
T1	154248	1478	0	0
T2	32515	389	0	0
T3	140399	25008	0	0
T4	109251	1	0	0
T7	364322	3003	0	0
T8	244642	1054	0	0
T9	8292	78	0	0
T10	9980	98	0	0
T11	2140	11	0	0
T12	242320	55281	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219037	0	0
T1	154248	201	0	0
T2	32515	397	0	0
T3	140399	87	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	250	0	0
T9	8292	77	0	0
T10	9980	101	0	0
T11	2140	10	0	0
T12	242320	178	0	0
T13	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219037	0	0
T1	154248	201	0	0
T2	32515	397	0	0
T3	140399	87	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	250	0	0
T9	8292	77	0	0
T10	9980	101	0	0
T11	2140	10	0	0
T12	242320	178	0	0
T13	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	583213	0	0
T1	154248	210	0	0
T2	32515	413	0	0
T3	140399	2529	0	0
T4	109251	0	0	0
T7	364322	435	0	0
T8	244642	282	0	0
T9	8292	77	0	0
T10	9980	105	0	0
T11	2140	10	0	0
T12	242320	3027	0	0
T13	0	99	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219037	0	0
T1	154248	201	0	0
T2	32515	397	0	0
T3	140399	87	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	250	0	0
T9	8292	77	0	0
T10	9980	101	0	0
T11	2140	10	0	0
T12	242320	178	0	0
T13	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	241942	0	0
GntImpliesValid_A	435744204	241942	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	241942	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3148801	0	0
ReadyAndValidImplyGrant_A	435744204	241942	0	0
ReqAndReadyImplyGrant_A	435744204	241942	0	0
ReqImpliesValid_A	435744204	640125	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	241942	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	241942	0	0
T1	154248	244	0	0
T2	32515	483	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	1412	0	0
T8	244642	247	0	0
T9	8292	78	0	0
T10	9980	166	0	0
T11	2140	16	0	0
T12	242320	195	0	0
T13	0	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	241942	0	0
T1	154248	244	0	0
T2	32515	483	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	1412	0	0
T8	244642	247	0	0
T9	8292	78	0	0
T10	9980	166	0	0
T11	2140	16	0	0
T12	242320	195	0	0
T13	0	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	241942	0	0
T1	154248	244	0	0
T2	32515	483	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	1412	0	0
T8	244642	247	0	0
T9	8292	78	0	0
T10	9980	166	0	0
T11	2140	16	0	0
T12	242320	195	0	0
T13	0	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3148801	0	0
T1	154248	1905	0	0
T2	32515	464	0	0
T3	140399	33455	0	0
T4	109251	1	0	0
T7	364322	5229	0	0
T8	244642	1083	0	0
T9	8292	78	0	0
T10	9980	155	0	0
T11	2140	17	0	0
T12	242320	62729	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	241942	0	0
T1	154248	244	0	0
T2	32515	483	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	1412	0	0
T8	244642	247	0	0
T9	8292	78	0	0
T10	9980	166	0	0
T11	2140	16	0	0
T12	242320	195	0	0
T13	0	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	241942	0	0
T1	154248	244	0	0
T2	32515	483	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	1412	0	0
T8	244642	247	0	0
T9	8292	78	0	0
T10	9980	166	0	0
T11	2140	16	0	0
T12	242320	195	0	0
T13	0	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	640125	0	0
T1	154248	261	0	0
T2	32515	509	0	0
T3	140399	1659	0	0
T4	109251	0	0	0
T7	364322	9592	0	0
T8	244642	281	0	0
T9	8292	79	0	0
T10	9980	178	0	0
T11	2140	16	0	0
T12	242320	4680	0	0
T13	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	241942	0	0
T1	154248	244	0	0
T2	32515	483	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	1412	0	0
T8	244642	247	0	0
T9	8292	78	0	0
T10	9980	166	0	0
T11	2140	16	0	0
T12	242320	195	0	0
T13	0	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	222563	0	0
GntImpliesValid_A	435744204	222563	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	222563	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3050761	0	0
ReadyAndValidImplyGrant_A	435744204	222563	0	0
ReqAndReadyImplyGrant_A	435744204	222563	0	0
ReqImpliesValid_A	435744204	607813	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	222563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222563	0	0
T1	154248	260	0	0
T2	32515	403	0	0
T3	140399	91	0	0
T4	109251	0	0	0
T7	364322	932	0	0
T8	244642	203	0	0
T9	8292	69	0	0
T10	9980	122	0	0
T11	2140	7	0	0
T12	242320	166	0	0
T13	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222563	0	0
T1	154248	260	0	0
T2	32515	403	0	0
T3	140399	91	0	0
T4	109251	0	0	0
T7	364322	932	0	0
T8	244642	203	0	0
T9	8292	69	0	0
T10	9980	122	0	0
T11	2140	7	0	0
T12	242320	166	0	0
T13	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222563	0	0
T1	154248	260	0	0
T2	32515	403	0	0
T3	140399	91	0	0
T4	109251	0	0	0
T7	364322	932	0	0
T8	244642	203	0	0
T9	8292	69	0	0
T10	9980	122	0	0
T11	2140	7	0	0
T12	242320	166	0	0
T13	0	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3050761	0	0
T1	154248	2078	0	0
T2	32515	390	0	0
T3	140399	25974	0	0
T4	109251	1	0	0
T7	364322	5623	0	0
T8	244642	775	0	0
T9	8292	70	0	0
T10	9980	117	0	0
T11	2140	8	0	0
T12	242320	60566	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222563	0	0
T1	154248	260	0	0
T2	32515	403	0	0
T3	140399	91	0	0
T4	109251	0	0	0
T7	364322	932	0	0
T8	244642	203	0	0
T9	8292	69	0	0
T10	9980	122	0	0
T11	2140	7	0	0
T12	242320	166	0	0
T13	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222563	0	0
T1	154248	260	0	0
T2	32515	403	0	0
T3	140399	91	0	0
T4	109251	0	0	0
T7	364322	932	0	0
T8	244642	203	0	0
T9	8292	69	0	0
T10	9980	122	0	0
T11	2140	7	0	0
T12	242320	166	0	0
T13	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	607813	0	0
T1	154248	294	0	0
T2	32515	424	0	0
T3	140399	2529	0	0
T4	109251	0	0	0
T7	364322	3613	0	0
T8	244642	266	0	0
T9	8292	69	0	0
T10	9980	128	0	0
T11	2140	7	0	0
T12	242320	3693	0	0
T13	0	101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	222563	0	0
T1	154248	260	0	0
T2	32515	403	0	0
T3	140399	91	0	0
T4	109251	0	0	0
T7	364322	932	0	0
T8	244642	203	0	0
T9	8292	69	0	0
T10	9980	122	0	0
T11	2140	7	0	0
T12	242320	166	0	0
T13	0	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	219643	0	0
GntImpliesValid_A	435744204	219643	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	219643	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3048316	0	0
ReadyAndValidImplyGrant_A	435744204	219643	0	0
ReqAndReadyImplyGrant_A	435744204	219643	0	0
ReqImpliesValid_A	435744204	579076	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	219643	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219643	0	0
T1	154248	689	0	0
T2	32515	434	0	0
T3	140399	97	0	0
T4	109251	0	0	0
T7	364322	416	0	0
T8	244642	213	0	0
T9	8292	91	0	0
T10	9980	101	0	0
T11	2140	11	0	0
T12	242320	193	0	0
T13	0	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219643	0	0
T1	154248	689	0	0
T2	32515	434	0	0
T3	140399	97	0	0
T4	109251	0	0	0
T7	364322	416	0	0
T8	244642	213	0	0
T9	8292	91	0	0
T10	9980	101	0	0
T11	2140	11	0	0
T12	242320	193	0	0
T13	0	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219643	0	0
T1	154248	689	0	0
T2	32515	434	0	0
T3	140399	97	0	0
T4	109251	0	0	0
T7	364322	416	0	0
T8	244642	213	0	0
T9	8292	91	0	0
T10	9980	101	0	0
T11	2140	11	0	0
T12	242320	193	0	0
T13	0	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3048316	0	0
T1	154248	2985	0	0
T2	32515	423	0	0
T3	140399	29211	0	0
T4	109251	1	0	0
T7	364322	3261	0	0
T8	244642	901	0	0
T9	8292	92	0	0
T10	9980	97	0	0
T11	2140	12	0	0
T12	242320	55549	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219643	0	0
T1	154248	689	0	0
T2	32515	434	0	0
T3	140399	97	0	0
T4	109251	0	0	0
T7	364322	416	0	0
T8	244642	213	0	0
T9	8292	91	0	0
T10	9980	101	0	0
T11	2140	11	0	0
T12	242320	193	0	0
T13	0	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219643	0	0
T1	154248	689	0	0
T2	32515	434	0	0
T3	140399	97	0	0
T4	109251	0	0	0
T7	364322	416	0	0
T8	244642	213	0	0
T9	8292	91	0	0
T10	9980	101	0	0
T11	2140	11	0	0
T12	242320	193	0	0
T13	0	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	579076	0	0
T1	154248	4122	0	0
T2	32515	453	0	0
T3	140399	3023	0	0
T4	109251	0	0	0
T7	364322	454	0	0
T8	244642	250	0	0
T9	8292	91	0	0
T10	9980	106	0	0
T11	2140	11	0	0
T12	242320	3333	0	0
T13	0	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219643	0	0
T1	154248	689	0	0
T2	32515	434	0	0
T3	140399	97	0	0
T4	109251	0	0	0
T7	364322	416	0	0
T8	244642	213	0	0
T9	8292	91	0	0
T10	9980	101	0	0
T11	2140	11	0	0
T12	242320	193	0	0
T13	0	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	235897	0	0
GntImpliesValid_A	435744204	235897	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	235897	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3035148	0	0
ReadyAndValidImplyGrant_A	435744204	235897	0	0
ReqAndReadyImplyGrant_A	435744204	235897	0	0
ReqImpliesValid_A	435744204	685872	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	235897	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	235897	0	0
T1	154248	225	0	0
T2	32515	372	0	0
T3	140399	75	0	0
T4	109251	418	0	0
T7	364322	874	0	0
T8	244642	246	0	0
T9	8292	95	0	0
T10	9980	124	0	0
T11	2140	16	0	0
T12	242320	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	235897	0	0
T1	154248	225	0	0
T2	32515	372	0	0
T3	140399	75	0	0
T4	109251	418	0	0
T7	364322	874	0	0
T8	244642	246	0	0
T9	8292	95	0	0
T10	9980	124	0	0
T11	2140	16	0	0
T12	242320	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	235897	0	0
T1	154248	225	0	0
T2	32515	372	0	0
T3	140399	75	0	0
T4	109251	418	0	0
T7	364322	874	0	0
T8	244642	246	0	0
T9	8292	95	0	0
T10	9980	124	0	0
T11	2140	16	0	0
T12	242320	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3035148	0	0
T1	154248	1743	0	0
T2	32515	363	0	0
T3	140399	25220	0	0
T4	109251	936	0	0
T7	364322	4121	0	0
T8	244642	1072	0	0
T9	8292	92	0	0
T10	9980	117	0	0
T11	2140	16	0	0
T12	242320	64059	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	235897	0	0
T1	154248	225	0	0
T2	32515	372	0	0
T3	140399	75	0	0
T4	109251	418	0	0
T7	364322	874	0	0
T8	244642	246	0	0
T9	8292	95	0	0
T10	9980	124	0	0
T11	2140	16	0	0
T12	242320	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	235897	0	0
T1	154248	225	0	0
T2	32515	372	0	0
T3	140399	75	0	0
T4	109251	418	0	0
T7	364322	874	0	0
T8	244642	246	0	0
T9	8292	95	0	0
T10	9980	124	0	0
T11	2140	16	0	0
T12	242320	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	685872	0	0
T1	154248	225	0	0
T2	32515	389	0	0
T3	140399	937	0	0
T4	109251	3680	0	0
T7	364322	4543	0	0
T8	244642	273	0	0
T9	8292	99	0	0
T10	9980	132	0	0
T11	2140	17	0	0
T12	242320	6205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	235897	0	0
T1	154248	225	0	0
T2	32515	372	0	0
T3	140399	75	0	0
T4	109251	418	0	0
T7	364322	874	0	0
T8	244642	246	0	0
T9	8292	95	0	0
T10	9980	124	0	0
T11	2140	16	0	0
T12	242320	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	219389	0	0
GntImpliesValid_A	435744204	219389	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	219389	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3105940	0	0
ReadyAndValidImplyGrant_A	435744204	219389	0	0
ReqAndReadyImplyGrant_A	435744204	219389	0	0
ReqImpliesValid_A	435744204	616499	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	219389	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219389	0	0
T1	154248	205	0	0
T2	32515	934	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	238	0	0
T9	8292	98	0	0
T10	9980	112	0	0
T11	2140	6	0	0
T12	242320	176	0	0
T13	0	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219389	0	0
T1	154248	205	0	0
T2	32515	934	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	238	0	0
T9	8292	98	0	0
T10	9980	112	0	0
T11	2140	6	0	0
T12	242320	176	0	0
T13	0	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219389	0	0
T1	154248	205	0	0
T2	32515	934	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	238	0	0
T9	8292	98	0	0
T10	9980	112	0	0
T11	2140	6	0	0
T12	242320	176	0	0
T13	0	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3105940	0	0
T1	154248	1546	0	0
T2	32515	687	0	0
T3	140399	31612	0	0
T4	109251	1	0	0
T7	364322	3130	0	0
T8	244642	1023	0	0
T9	8292	99	0	0
T10	9980	107	0	0
T11	2140	6	0	0
T12	242320	58372	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219389	0	0
T1	154248	205	0	0
T2	32515	934	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	238	0	0
T9	8292	98	0	0
T10	9980	112	0	0
T11	2140	6	0	0
T12	242320	176	0	0
T13	0	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219389	0	0
T1	154248	205	0	0
T2	32515	934	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	238	0	0
T9	8292	98	0	0
T10	9980	112	0	0
T11	2140	6	0	0
T12	242320	176	0	0
T13	0	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	616499	0	0
T1	154248	220	0	0
T2	32515	1189	0	0
T3	140399	2247	0	0
T4	109251	0	0	0
T7	364322	430	0	0
T8	244642	270	0	0
T9	8292	98	0	0
T10	9980	118	0	0
T11	2140	7	0	0
T12	242320	3538	0	0
T13	0	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	219389	0	0
T1	154248	205	0	0
T2	32515	934	0	0
T3	140399	93	0	0
T4	109251	0	0	0
T7	364322	405	0	0
T8	244642	238	0	0
T9	8292	98	0	0
T10	9980	112	0	0
T11	2140	6	0	0
T12	242320	176	0	0
T13	0	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	216767	0	0
GntImpliesValid_A	435744204	216767	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	216767	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	3074842	0	0
ReadyAndValidImplyGrant_A	435744204	216767	0	0
ReqAndReadyImplyGrant_A	435744204	216767	0	0
ReqImpliesValid_A	435744204	574319	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	0	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	216767	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	216767	0	0
T1	154248	215	0	0
T2	32515	428	0	0
T3	140399	99	0	0
T4	109251	918	0	0
T7	364322	839	0	0
T8	244642	228	0	0
T9	8292	76	0	0
T10	9980	94	0	0
T11	2140	16	0	0
T12	242320	176	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	216767	0	0
T1	154248	215	0	0
T2	32515	428	0	0
T3	140399	99	0	0
T4	109251	918	0	0
T7	364322	839	0	0
T8	244642	228	0	0
T9	8292	76	0	0
T10	9980	94	0	0
T11	2140	16	0	0
T12	242320	176	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	216767	0	0
T1	154248	215	0	0
T2	32515	428	0	0
T3	140399	99	0	0
T4	109251	918	0	0
T7	364322	839	0	0
T8	244642	228	0	0
T9	8292	76	0	0
T10	9980	94	0	0
T11	2140	16	0	0
T12	242320	176	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	3074842	0	0
T1	154248	1646	0	0
T2	32515	411	0	0
T3	140399	33504	0	0
T4	109251	1867	0	0
T7	364322	4225	0	0
T8	244642	956	0	0
T9	8292	77	0	0
T10	9980	92	0	0
T11	2140	16	0	0
T12	242320	56715	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	216767	0	0
T1	154248	215	0	0
T2	32515	428	0	0
T3	140399	99	0	0
T4	109251	918	0	0
T7	364322	839	0	0
T8	244642	228	0	0
T9	8292	76	0	0
T10	9980	94	0	0
T11	2140	16	0	0
T12	242320	176	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	216767	0	0
T1	154248	215	0	0
T2	32515	428	0	0
T3	140399	99	0	0
T4	109251	918	0	0
T7	364322	839	0	0
T8	244642	228	0	0
T9	8292	76	0	0
T10	9980	94	0	0
T11	2140	16	0	0
T12	242320	176	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	574319	0	0
T1	154248	233	0	0
T2	32515	453	0	0
T3	140399	2946	0	0
T4	109251	8687	0	0
T7	364322	4416	0	0
T8	244642	290	0	0
T9	8292	76	0	0
T10	9980	97	0	0
T11	2140	17	0	0
T12	242320	3535	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	216767	0	0
T1	154248	215	0	0
T2	32515	428	0	0
T3	140399	99	0	0
T4	109251	918	0	0
T7	364322	839	0	0
T8	244642	228	0	0
T9	8292	76	0	0
T10	9980	94	0	0
T11	2140	16	0	0
T12	242320	176	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	891567	0	0
GntImpliesValid_A	435744204	891567	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	891567	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	11544464	0	0
ReadyAndValidImplyGrant_A	435744204	891567	0	0
ReqAndReadyImplyGrant_A	435744204	891567	0	0
ReqImpliesValid_A	435744204	2362119	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	17934	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	891567	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	891567	0	0
T1	154248	1008	0	0
T2	32515	2035	0	0
T3	140399	324	0	0
T4	109251	626	0	0
T7	364322	3249	0	0
T8	244642	967	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	658	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	891567	0	0
T1	154248	1008	0	0
T2	32515	2035	0	0
T3	140399	324	0	0
T4	109251	626	0	0
T7	364322	3249	0	0
T8	244642	967	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	658	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	891567	0	0
T1	154248	1008	0	0
T2	32515	2035	0	0
T3	140399	324	0	0
T4	109251	626	0	0
T7	364322	3249	0	0
T8	244642	967	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	658	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	11544464	0	0
T1	154248	6811	0	0
T2	32515	8	0	0
T3	140399	101768	0	0
T4	109251	3961	0	0
T7	364322	19112	0	0
T8	244642	3234	0	0
T9	8292	1	0	0
T10	9980	1	0	0
T11	2140	1	0	0
T12	242320	217849	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	891567	0	0
T1	154248	1008	0	0
T2	32515	2035	0	0
T3	140399	324	0	0
T4	109251	626	0	0
T7	364322	3249	0	0
T8	244642	967	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	658	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	891567	0	0
T1	154248	1008	0	0
T2	32515	2035	0	0
T3	140399	324	0	0
T4	109251	626	0	0
T7	364322	3249	0	0
T8	244642	967	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	658	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	2362119	0	0
T1	154248	1261	0	0
T2	32515	2035	0	0
T3	140399	14417	0	0
T4	109251	1006	0	0
T7	364322	8202	0	0
T8	244642	1214	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	22161	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	17934	0	900
T2	32515	38	0	1
T3	140399	0	0	1
T4	109251	0	0	1
T5	0	14	0	0
T7	364322	6	0	1
T8	244642	0	0	1
T9	8292	9	0	1
T10	9980	10	0	1
T11	2140	0	0	1
T12	242320	0	0	1
T13	12025	7	0	1
T14	0	66	0	0
T15	0	335	0	0
T16	0	1208	0	0
T17	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	891567	0	0
T1	154248	1008	0	0
T2	32515	2035	0	0
T3	140399	324	0	0
T4	109251	626	0	0
T7	364322	3249	0	0
T8	244642	967	0	0
T9	8292	365	0	0
T10	9980	425	0	0
T11	2140	59	0	0
T12	242320	658	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435744204	435617864	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435744204	879481	0	0
GntImpliesValid_A	435744204	879481	0	0
GrantKnown_A	435744204	435617864	0	0
IdxKnown_A	435744204	435617864	0	0
IndexIsCorrect_A	435744204	879481	0	0
LockArbDecision_A	435744204	0	0	0
NoReadyValidNoGrant_A	435744204	365593131	0	0
ReadyAndValidImplyGrant_A	435744204	879481	0	0
ReqAndReadyImplyGrant_A	435744204	879481	0	0
ReqImpliesValid_A	435744204	13436188	0	0
ReqStaysHighUntilGranted0_M	435744204	0	0	0
RoundRobin_A	435744204	28417	0	900
ValidKnown_A	435744204	435617864	0	0
gen_data_port_assertion.DataFlow_A	435744204	879481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	879481	0	0
T1	154248	976	0	0
T2	32515	2058	0	0
T3	140399	339	0	0
T4	109251	2021	0	0
T7	364322	3162	0	0
T8	244642	967	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	671	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	879481	0	0
T1	154248	976	0	0
T2	32515	2058	0	0
T3	140399	339	0	0
T4	109251	2021	0	0
T7	364322	3162	0	0
T8	244642	967	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	671	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	879481	0	0
T1	154248	976	0	0
T2	32515	2058	0	0
T3	140399	339	0	0
T4	109251	2021	0	0
T7	364322	3162	0	0
T8	244642	967	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	671	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	365593131	0	0
T1	154248	133193	0	0
T2	32515	1	0	0
T3	140399	129355	0	0
T4	109251	81289	0	0
T7	364322	307585	0	0
T8	244642	203523	0	0
T9	8292	1	0	0
T10	9980	1	0	0
T11	2140	1	0	0
T12	242320	218200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	879481	0	0
T1	154248	976	0	0
T2	32515	2058	0	0
T3	140399	339	0	0
T4	109251	2021	0	0
T7	364322	3162	0	0
T8	244642	967	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	671	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	879481	0	0
T1	154248	976	0	0
T2	32515	2058	0	0
T3	140399	339	0	0
T4	109251	2021	0	0
T7	364322	3162	0	0
T8	244642	967	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	671	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	13436188	0	0
T1	154248	7920	0	0
T2	32515	2058	0	0
T3	140399	107924	0	0
T4	109251	20031	0	0
T7	364322	26812	0	0
T8	244642	4308	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	237047	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	28417	0	900
T1	154248	1	0	1
T2	32515	33	0	1
T3	140399	0	0	1
T4	109251	27	0	1
T5	0	86	0	0
T7	364322	13	0	1
T8	244642	0	0	1
T9	8292	4	0	1
T10	9980	9	0	1
T11	2140	0	0	1
T12	242320	0	0	1
T13	0	7	0	0
T15	0	30	0	0
T16	0	1241	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	435617864	0	0
T1	154248	154072	0	0
T2	32515	32086	0	0
T3	140399	140395	0	0
T4	109251	109179	0	0
T7	364322	364246	0	0
T8	244642	244639	0	0
T9	8292	8276	0	0
T10	9980	9909	0	0
T11	2140	2068	0	0
T12	242320	242320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435744204	879481	0	0
T1	154248	976	0	0
T2	32515	2058	0	0
T3	140399	339	0	0
T4	109251	2021	0	0
T7	364322	3162	0	0
T8	244642	967	0	0
T9	8292	342	0	0
T10	9980	420	0	0
T11	2140	54	0	0
T12	242320	671	0	0