Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sm1_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.51 98.68 85.92 92.73 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 92.21 97.50 82.14 89.19 100.00



Module Instance : tb.dut.u_sm1_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_40

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_42

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_43

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_44

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_45

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_46

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_47

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_48

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_49

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_50

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_51

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_52

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_53

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_54

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_55

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_56

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.78 100.00 98.39 100.00 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
SCORELINE
95.96 100.00
tb.dut.u_sm1_28

SCORELINE
95.96 100.00
tb.dut.u_sm1_29

SCORELINE
100.00 100.00
tb.dut.u_sm1_30

SCORELINE
95.96 100.00
tb.dut.u_sm1_31

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
SCORELINE
96.97 100.00
tb.dut.u_sm1_33

SCORELINE
96.97 100.00
tb.dut.u_sm1_34

SCORELINE
96.97 100.00
tb.dut.u_sm1_36

SCORELINE
96.97 100.00
tb.dut.u_sm1_38

SCORELINE
96.97 100.00
tb.dut.u_sm1_40

SCORELINE
96.97 100.00
tb.dut.u_sm1_42

SCORELINE
96.97 100.00
tb.dut.u_sm1_43

SCORELINE
96.97 100.00
tb.dut.u_sm1_44

SCORELINE
96.97 100.00
tb.dut.u_sm1_45

SCORELINE
96.97 100.00
tb.dut.u_sm1_46

SCORELINE
96.97 100.00
tb.dut.u_sm1_47

SCORELINE
96.97 100.00
tb.dut.u_sm1_48

SCORELINE
96.97 100.00
tb.dut.u_sm1_49

SCORELINE
96.97 100.00
tb.dut.u_sm1_50

SCORELINE
96.97 100.00
tb.dut.u_sm1_51

SCORELINE
96.97 100.00
tb.dut.u_sm1_52

SCORELINE
96.97 100.00
tb.dut.u_sm1_53

SCORELINE
96.97 100.00
tb.dut.u_sm1_54

SCORELINE
96.97 100.00
tb.dut.u_sm1_55

SCORELINE
96.97 100.00
tb.dut.u_sm1_56

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
SCORECOND
95.96 87.88
tb.dut.u_sm1_28

SCORECOND
95.96 87.88
tb.dut.u_sm1_29

SCORECOND
95.96 87.88
tb.dut.u_sm1_31

SCORECOND
100.00 100.00
tb.dut.u_sm1_30

TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT1,T2,T3
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT1,T2,T3
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110CoveredT2,T3,T8
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110CoveredT2,T3,T8
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
SCORECOND
96.97 90.91
tb.dut.u_sm1_33

SCORECOND
96.97 90.91
tb.dut.u_sm1_34

SCORECOND
96.97 90.91
tb.dut.u_sm1_43

SCORECOND
96.97 90.91
tb.dut.u_sm1_44

SCORECOND
96.97 90.91
tb.dut.u_sm1_45

SCORECOND
96.97 90.91
tb.dut.u_sm1_46

SCORECOND
96.97 90.91
tb.dut.u_sm1_47

SCORECOND
96.97 90.91
tb.dut.u_sm1_48

SCORECOND
96.97 90.91
tb.dut.u_sm1_49

SCORECOND
96.97 90.91
tb.dut.u_sm1_50

SCORECOND
96.97 90.91
tb.dut.u_sm1_51

SCORECOND
96.97 90.91
tb.dut.u_sm1_52

SCORECOND
96.97 90.91
tb.dut.u_sm1_53

SCORECOND
96.97 90.91
tb.dut.u_sm1_54

SCORECOND
96.97 90.91
tb.dut.u_sm1_55

SCORECOND
96.97 90.91
tb.dut.u_sm1_56

SCORECOND
96.97 90.91
tb.dut.u_sm1_36

SCORECOND
96.97 90.91
tb.dut.u_sm1_38

SCORECOND
96.97 90.91
tb.dut.u_sm1_40

SCORECOND
96.97 90.91
tb.dut.u_sm1_42

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Module : tlul_socket_m1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 2147483647 23015351 0 0
gen_host_fifo[1].idInRange 2147483647 12642213 0 0
gen_host_fifo[2].idInRange 1688261608 3751080 0 0
maxM 21600 21600 0 0
rspIdInRange 2147483647 159083884 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 23015351 0 0
T1 1456130 1190 0 0
T2 5506608 221133 0 0
T3 9769032 18012 0 0
T7 5612880 243833 0 0
T8 20938248 32732 0 0
T9 3313008 5072 0 0
T10 4650048 183012 0 0
T11 10427808 17157 0 0
T12 1010016 3099 0 0
T13 9671976 11028 0 0
T14 560006 21237 0 0
T15 0 104 0 0
T16 0 416 0 0
T17 0 509 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 12642213 0 0
T1 291226 788 0 0
T2 5506608 75321 0 0
T3 9769032 13271 0 0
T7 5612880 91878 0 0
T8 20938248 28420 0 0
T9 3313008 2433 0 0
T10 4650048 74782 0 0
T11 10427808 13757 0 0
T12 1010016 1317 0 0
T13 9671976 7963 0 0
T14 677902 22682 0 0
T15 0 221 0 0
T16 0 551 0 0
T17 0 638 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 1688261608 3751080 0 0
T2 917768 35020 0 0
T3 1628172 3034 0 0
T7 935480 39340 0 0
T8 3489708 4007 0 0
T9 552168 625 0 0
T10 775008 22920 0 0
T11 1737968 4528 0 0
T12 168336 323 0 0
T13 1611996 1379 0 0
T14 117896 4037 0 0
T15 0 59 0 0
T16 0 67 0 0
T17 0 155 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 21600 21600 0 0
T1 24 24 0 0
T2 24 24 0 0
T3 24 24 0 0
T7 24 24 0 0
T8 24 24 0 0
T9 24 24 0 0
T10 24 24 0 0
T11 24 24 0 0
T12 24 24 0 0
T13 24 24 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 159083884 0 0
T1 1456130 96083 0 0
T2 5506608 737272 0 0
T3 9769032 1426397 0 0
T7 5612880 999696 0 0
T8 20938248 3682792 0 0
T9 3313008 639706 0 0
T10 4650048 629540 0 0
T11 10427808 1756608 0 0
T12 1010016 13646 0 0
T13 9671976 64350 0 0
T14 560006 6857 0 0
T15 0 881 0 0
T16 0 1278 0 0
T17 0 925 0 0

Line Coverage for Instance : tb.dut.u_sm1_28
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_28
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T7,T9
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T7,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

Assert Coverage for Instance : tb.dut.u_sm1_28
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 1633733 0 0
gen_host_fifo[1].idInRange 422065402 401162 0 0
gen_host_fifo[2].idInRange 422065402 493026 0 0
maxM 900 900 0 0
rspIdInRange 422065402 17969307 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 1633733 0 0
T1 291226 48 0 0
T2 229442 18685 0 0
T3 407043 951 0 0
T7 233870 13796 0 0
T8 872427 1230 0 0
T9 138042 524 0 0
T10 193752 8144 0 0
T11 434492 903 0 0
T12 42084 297 0 0
T13 402999 73 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 401162 0 0
T2 229442 2434 0 0
T3 407043 0 0 0
T7 233870 3591 0 0
T8 872427 0 0 0
T9 138042 87 0 0
T10 193752 4163 0 0
T11 434492 0 0 0
T12 42084 90 0 0
T13 402999 9 0 0
T14 29474 6 0 0
T15 0 5 0 0
T16 0 47 0 0
T17 0 156 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 493026 0 0
T2 229442 5232 0 0
T3 407043 0 0 0
T7 233870 3394 0 0
T8 872427 0 0 0
T9 138042 70 0 0
T10 193752 560 0 0
T11 434492 0 0 0
T12 42084 52 0 0
T13 402999 73 0 0
T14 29474 6 0 0
T15 0 6 0 0
T16 0 67 0 0
T17 0 155 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 17969307 0 0
T1 291226 301 0 0
T2 229442 71510 0 0
T3 407043 2071 0 0
T7 233870 63093 0 0
T8 872427 346074 0 0
T9 138042 144620 0 0
T10 193752 57982 0 0
T11 434492 1756 0 0
T12 42084 2005 0 0
T13 402999 5630 0 0

Line Coverage for Instance : tb.dut.u_sm1_29
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_29
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_29
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 1836144 0 0
gen_host_fifo[1].idInRange 422065402 462321 0 0
gen_host_fifo[2].idInRange 422065402 625042 0 0
maxM 900 900 0 0
rspIdInRange 422065402 16939728 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 1836144 0 0
T1 291226 96 0 0
T2 229442 10944 0 0
T3 407043 2245 0 0
T7 233870 21497 0 0
T8 872427 2435 0 0
T9 138042 510 0 0
T10 193752 8215 0 0
T11 434492 954 0 0
T12 42084 215 0 0
T13 402999 2057 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 462321 0 0
T2 229442 677 0 0
T3 407043 1099 0 0
T7 233870 2429 0 0
T8 872427 1152 0 0
T9 138042 72 0 0
T10 193752 2861 0 0
T11 434492 0 0 0
T12 42084 42 0 0
T13 402999 4 0 0
T14 29474 1211 0 0
T15 0 14 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 625042 0 0
T2 229442 3140 0 0
T3 407043 1200 0 0
T7 233870 3772 0 0
T8 872427 1331 0 0
T9 138042 100 0 0
T10 193752 2406 0 0
T11 434492 0 0 0
T12 42084 27 0 0
T13 402999 6 0 0
T14 29474 1212 0 0
T15 0 3 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 16939728 0 0
T1 291226 51 0 0
T2 229442 56597 0 0
T3 407043 191095 0 0
T7 233870 78012 0 0
T8 872427 559260 0 0
T9 138042 140949 0 0
T10 193752 61583 0 0
T11 434492 2789 0 0
T12 42084 1510 0 0
T13 402999 4977 0 0

Line Coverage for Instance : tb.dut.u_sm1_31
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_31
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_31
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 1826844 0 0
gen_host_fifo[1].idInRange 422065402 463990 0 0
gen_host_fifo[2].idInRange 422065402 607320 0 0
maxM 900 900 0 0
rspIdInRange 422065402 17946803 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 1826844 0 0
T1 291226 59 0 0
T2 229442 18346 0 0
T3 407043 1012 0 0
T7 233870 19483 0 0
T8 872427 3483 0 0
T9 138042 575 0 0
T10 193752 13780 0 0
T11 434492 3127 0 0
T12 42084 271 0 0
T13 402999 767 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 463990 0 0
T2 229442 3316 0 0
T3 407043 0 0 0
T7 233870 2469 0 0
T8 872427 2261 0 0
T9 138042 101 0 0
T10 193752 1561 0 0
T11 434492 2203 0 0
T12 42084 51 0 0
T13 402999 148 0 0
T14 29474 2994 0 0
T15 0 13 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 607320 0 0
T2 229442 5489 0 0
T3 407043 0 0 0
T7 233870 3977 0 0
T8 872427 2676 0 0
T9 138042 59 0 0
T10 193752 3149 0 0
T11 434492 2749 0 0
T12 42084 32 0 0
T13 402999 9 0 0
T14 29474 2289 0 0
T15 0 5 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 17946803 0 0
T1 291226 47 0 0
T2 229442 56661 0 0
T3 407043 2535 0 0
T7 233870 69146 0 0
T8 872427 725911 0 0
T9 138042 153070 0 0
T10 193752 59080 0 0
T11 434492 375463 0 0
T12 42084 1980 0 0
T13 402999 3704 0 0

Line Coverage for Instance : tb.dut.u_sm1_33
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_33
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT2,T3,T7
110CoveredT1,T2,T3
111CoveredT2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT2,T3,T7
110Not Covered
111CoveredT2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

Assert Coverage for Instance : tb.dut.u_sm1_33
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 308382 0 0
gen_host_fifo[1].idInRange 422065402 404596 0 0
maxM 900 900 0 0
rspIdInRange 422065402 5069386 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 308382 0 0
T2 229442 1866 0 0
T3 407043 1550 0 0
T7 233870 869 0 0
T8 872427 0 0 0
T9 138042 83 0 0
T10 193752 1136 0 0
T11 434492 0 0 0
T12 42084 55 0 0
T13 402999 5 0 0
T14 29474 9 0 0
T15 0 9 0 0
T16 0 45 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 404596 0 0
T2 229442 4315 0 0
T3 407043 1871 0 0
T7 233870 681 0 0
T8 872427 0 0 0
T9 138042 57 0 0
T10 193752 831 0 0
T11 434492 0 0 0
T12 42084 47 0 0
T13 402999 10 0 0
T14 29474 2 0 0
T15 0 6 0 0
T16 0 57 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 5069386 0 0
T2 229442 23840 0 0
T3 407043 181070 0 0
T7 233870 32798 0 0
T8 872427 0 0 0
T9 138042 1618 0 0
T10 193752 18793 0 0
T11 434492 0 0 0
T12 42084 323 0 0
T13 402999 2183 0 0
T14 29474 11 0 0
T15 0 67 0 0
T16 0 164 0 0

Line Coverage for Instance : tb.dut.u_sm1_34
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_34
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT2,T3,T7
110CoveredT1,T2,T3
111CoveredT2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT2,T3,T7
110Not Covered
111CoveredT2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

Assert Coverage for Instance : tb.dut.u_sm1_34
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 287878 0 0
gen_host_fifo[1].idInRange 422065402 392766 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4042081 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 287878 0 0
T2 229442 1193 0 0
T3 407043 720 0 0
T7 233870 1264 0 0
T8 872427 0 0 0
T9 138042 96 0 0
T10 193752 63 0 0
T11 434492 0 0 0
T12 42084 36 0 0
T13 402999 5 0 0
T14 29474 6 0 0
T15 0 3 0 0
T16 0 39 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 392766 0 0
T2 229442 2223 0 0
T3 407043 755 0 0
T7 233870 2100 0 0
T8 872427 0 0 0
T9 138042 81 0 0
T10 193752 1991 0 0
T11 434492 0 0 0
T12 42084 28 0 0
T13 402999 6 0 0
T14 29474 6 0 0
T15 0 3 0 0
T16 0 73 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4042081 0 0
T2 229442 31551 0 0
T3 407043 89929 0 0
T7 233870 32963 0 0
T8 872427 0 0 0
T9 138042 3609 0 0
T10 193752 17641 0 0
T11 434492 0 0 0
T12 42084 242 0 0
T13 402999 2076 0 0
T14 29474 12 0 0
T15 0 21 0 0
T16 0 186 0 0

Line Coverage for Instance : tb.dut.u_sm1_36
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_36
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_36
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 636256 0 0
gen_host_fifo[1].idInRange 422065402 752949 0 0
maxM 900 900 0 0
rspIdInRange 422065402 5758667 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 636256 0 0
T2 229442 853 0 0
T3 407043 0 0 0
T7 233870 266 0 0
T8 872427 11637 0 0
T9 138042 71 0 0
T10 193752 177 0 0
T11 434492 793 0 0
T12 42084 31 0 0
T13 402999 10 0 0
T14 29474 2 0 0
T15 0 4 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 752949 0 0
T2 229442 1079 0 0
T3 407043 0 0 0
T7 233870 440 0 0
T8 872427 12747 0 0
T9 138042 123 0 0
T10 193752 3378 0 0
T11 434492 1145 0 0
T12 42084 26 0 0
T13 402999 220 0 0
T14 29474 4 0 0
T15 0 5 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 5758667 0 0
T2 229442 28870 0 0
T3 407043 0 0 0
T7 233870 52867 0 0
T8 872427 196276 0 0
T9 138042 6626 0 0
T10 193752 15796 0 0
T11 434492 128601 0 0
T12 42084 253 0 0
T13 402999 5007 0 0
T14 29474 6 0 0
T15 0 20 0 0

Line Coverage for Instance : tb.dut.u_sm1_38
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_38
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110CoveredT1,T2,T3
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110Not Covered
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

Assert Coverage for Instance : tb.dut.u_sm1_38
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 744141 0 0
gen_host_fifo[1].idInRange 422065402 871069 0 0
maxM 900 900 0 0
rspIdInRange 422065402 3441054 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 744141 0 0
T2 229442 10550 0 0
T3 407043 0 0 0
T7 233870 161 0 0
T8 872427 0 0 0
T9 138042 125 0 0
T10 193752 906 0 0
T11 434492 797 0 0
T12 42084 30 0 0
T13 402999 8 0 0
T14 29474 6 0 0
T15 0 7 0 0
T16 0 101 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 871069 0 0
T2 229442 9798 0 0
T3 407043 0 0 0
T7 233870 1304 0 0
T8 872427 0 0 0
T9 138042 186 0 0
T10 193752 41 0 0
T11 434492 1156 0 0
T12 42084 42 0 0
T13 402999 5 0 0
T14 29474 5 0 0
T15 0 3 0 0
T16 0 53 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 3441054 0 0
T2 229442 23530 0 0
T3 407043 0 0 0
T7 233870 49705 0 0
T8 872427 0 0 0
T9 138042 2020 0 0
T10 193752 29612 0 0
T11 434492 115203 0 0
T12 42084 222 0 0
T13 402999 3468 0 0
T14 29474 11 0 0
T15 0 53 0 0
T16 0 165 0 0

Line Coverage for Instance : tb.dut.u_sm1_40
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_40
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_40
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 651067 0 0
gen_host_fifo[1].idInRange 422065402 752627 0 0
maxM 900 900 0 0
rspIdInRange 422065402 3755249 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 651067 0 0
T2 229442 3218 0 0
T3 407043 1408 0 0
T7 233870 261 0 0
T8 872427 960 0 0
T9 138042 93 0 0
T10 193752 35 0 0
T11 434492 0 0 0
T12 42084 37 0 0
T13 402999 5 0 0
T14 29474 11761 0 0
T15 0 9 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 752627 0 0
T2 229442 1556 0 0
T3 407043 1656 0 0
T7 233870 251 0 0
T8 872427 1279 0 0
T9 138042 131 0 0
T10 193752 2705 0 0
T11 434492 0 0 0
T12 42084 42 0 0
T13 402999 545 0 0
T14 29474 10621 0 0
T15 0 17 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 3755249 0 0
T2 229442 23929 0 0
T3 407043 108957 0 0
T7 233870 58547 0 0
T8 872427 113014 0 0
T9 138042 4304 0 0
T10 193752 12447 0 0
T11 434492 0 0 0
T12 42084 308 0 0
T13 402999 2338 0 0
T14 29474 1474 0 0
T15 0 83 0 0

Line Coverage for Instance : tb.dut.u_sm1_42
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_42
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T10
101CoveredT2,T7,T9
110CoveredT1,T2,T3
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110Not Covered
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

Assert Coverage for Instance : tb.dut.u_sm1_42
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 691815 0 0
gen_host_fifo[1].idInRange 422065402 823450 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4542576 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 691815 0 0
T2 229442 2266 0 0
T3 407043 0 0 0
T7 233870 2619 0 0
T8 872427 0 0 0
T9 138042 81 0 0
T10 193752 19851 0 0
T11 434492 0 0 0
T12 42084 43 0 0
T13 402999 7 0 0
T14 29474 2 0 0
T15 0 9 0 0
T16 0 53 0 0
T17 0 181 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 823450 0 0
T2 229442 3540 0 0
T3 407043 0 0 0
T7 233870 1628 0 0
T8 872427 0 0 0
T9 138042 100 0 0
T10 193752 14086 0 0
T11 434492 0 0 0
T12 42084 41 0 0
T13 402999 4 0 0
T14 29474 4 0 0
T15 0 4 0 0
T16 0 73 0 0
T17 0 170 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4542576 0 0
T2 229442 26396 0 0
T3 407043 0 0 0
T7 233870 36127 0 0
T8 872427 0 0 0
T9 138042 3884 0 0
T10 193752 21009 0 0
T11 434492 0 0 0
T12 42084 305 0 0
T13 402999 2646 0 0
T14 29474 6 0 0
T15 0 99 0 0
T16 0 183 0 0
T17 0 297 0 0

Line Coverage for Instance : tb.dut.u_sm1_43
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_43
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_43
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 265578 0 0
gen_host_fifo[1].idInRange 422065402 353887 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4009174 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 265578 0 0
T2 229442 1616 0 0
T3 407043 0 0 0
T7 233870 2430 0 0
T8 872427 737 0 0
T9 138042 83 0 0
T10 193752 565 0 0
T11 434492 709 0 0
T12 42084 43 0 0
T13 402999 8 0 0
T14 29474 519 0 0
T15 0 5 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 353887 0 0
T2 229442 1193 0 0
T3 407043 0 0 0
T7 233870 2587 0 0
T8 872427 861 0 0
T9 138042 75 0 0
T10 193752 786 0 0
T11 434492 810 0 0
T12 42084 43 0 0
T13 402999 576 0 0
T14 29474 322 0 0
T15 0 25 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4009174 0 0
T2 229442 21501 0 0
T3 407043 0 0 0
T7 233870 27655 0 0
T8 872427 123111 0 0
T9 138042 1861 0 0
T10 193752 21699 0 0
T11 434492 96421 0 0
T12 42084 334 0 0
T13 402999 1126 0 0
T14 29474 425 0 0
T15 0 64 0 0

Line Coverage for Instance : tb.dut.u_sm1_44
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_44
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_44
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 302147 0 0
gen_host_fifo[1].idInRange 422065402 397557 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4546076 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 302147 0 0
T2 229442 1928 0 0
T3 407043 703 0 0
T7 233870 684 0 0
T8 872427 688 0 0
T9 138042 70 0 0
T10 193752 800 0 0
T11 434492 748 0 0
T12 42084 37 0 0
T13 402999 4 0 0
T14 29474 5 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 397557 0 0
T2 229442 1123 0 0
T3 407043 848 0 0
T7 233870 2628 0 0
T8 872427 966 0 0
T9 138042 71 0 0
T10 193752 1527 0 0
T11 434492 936 0 0
T12 42084 48 0 0
T13 402999 2 0 0
T14 29474 3 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4546076 0 0
T2 229442 32751 0 0
T3 407043 105648 0 0
T7 233870 25787 0 0
T8 872427 101545 0 0
T9 138042 2413 0 0
T10 193752 19647 0 0
T11 434492 112890 0 0
T12 42084 334 0 0
T13 402999 1462 0 0
T14 29474 8 0 0

Line Coverage for Instance : tb.dut.u_sm1_45
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_45
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_45
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 319011 0 0
gen_host_fifo[1].idInRange 422065402 421224 0 0
maxM 900 900 0 0
rspIdInRange 422065402 5485499 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 319011 0 0
T2 229442 1359 0 0
T3 407043 816 0 0
T7 233870 1380 0 0
T8 872427 776 0 0
T9 138042 80 0 0
T10 193752 114 0 0
T11 434492 717 0 0
T12 42084 43 0 0
T13 402999 5 0 0
T14 29474 512 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 421224 0 0
T2 229442 2756 0 0
T3 407043 872 0 0
T7 233870 2411 0 0
T8 872427 871 0 0
T9 138042 89 0 0
T10 193752 1117 0 0
T11 434492 897 0 0
T12 42084 59 0 0
T13 402999 341 0 0
T14 29474 554 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 5485499 0 0
T2 229442 24526 0 0
T3 407043 96564 0 0
T7 233870 30116 0 0
T8 872427 115806 0 0
T9 138042 2998 0 0
T10 193752 12677 0 0
T11 434492 86060 0 0
T12 42084 374 0 0
T13 402999 1200 0 0
T14 29474 536 0 0

Line Coverage for Instance : tb.dut.u_sm1_46
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_46
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_46
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 274599 0 0
gen_host_fifo[1].idInRange 422065402 377417 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4807076 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 274599 0 0
T2 229442 1543 0 0
T3 407043 0 0 0
T7 233870 1445 0 0
T8 872427 772 0 0
T9 138042 77 0 0
T10 193752 309 0 0
T11 434492 577 0 0
T12 42084 43 0 0
T13 402999 9 0 0
T14 29474 5 0 0
T15 0 6 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 377417 0 0
T2 229442 1819 0 0
T3 407043 0 0 0
T7 233870 3117 0 0
T8 872427 848 0 0
T9 138042 102 0 0
T10 193752 3277 0 0
T11 434492 767 0 0
T12 42084 50 0 0
T13 402999 1865 0 0
T14 29474 4 0 0
T15 0 16 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4807076 0 0
T2 229442 24148 0 0
T3 407043 0 0 0
T7 233870 34497 0 0
T8 872427 123587 0 0
T9 138042 2483 0 0
T10 193752 18994 0 0
T11 434492 111947 0 0
T12 42084 399 0 0
T13 402999 3776 0 0
T14 29474 9 0 0
T15 0 74 0 0

Line Coverage for Instance : tb.dut.u_sm1_47
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_47
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110CoveredT1,T2,T3
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110Not Covered
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

Assert Coverage for Instance : tb.dut.u_sm1_47
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 253520 0 0
gen_host_fifo[1].idInRange 422065402 349726 0 0
maxM 900 900 0 0
rspIdInRange 422065402 3636968 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 253520 0 0
T2 229442 1074 0 0
T3 407043 0 0 0
T7 233870 1543 0 0
T8 872427 0 0 0
T9 138042 65 0 0
T10 193752 491 0 0
T11 434492 0 0 0
T12 42084 61 0 0
T13 402999 3 0 0
T14 29474 1995 0 0
T15 0 8 0 0
T16 0 65 0 0
T17 0 174 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 349726 0 0
T2 229442 1870 0 0
T3 407043 0 0 0
T7 233870 1319 0 0
T8 872427 0 0 0
T9 138042 97 0 0
T10 193752 1591 0 0
T11 434492 0 0 0
T12 42084 41 0 0
T13 402999 652 0 0
T14 29474 1435 0 0
T15 0 3 0 0
T16 0 90 0 0
T17 0 157 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 3636968 0 0
T2 229442 18972 0 0
T3 407043 0 0 0
T7 233870 38961 0 0
T8 872427 0 0 0
T9 138042 1071 0 0
T10 193752 23077 0 0
T11 434492 0 0 0
T12 42084 398 0 0
T13 402999 814 0 0
T14 29474 1050 0 0
T15 0 46 0 0
T16 0 151 0 0
T17 0 325 0 0

Line Coverage for Instance : tb.dut.u_sm1_48
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_48
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_48
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 247373 0 0
gen_host_fifo[1].idInRange 422065402 348487 0 0
maxM 900 900 0 0
rspIdInRange 422065402 3448247 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 247373 0 0
T2 229442 257 0 0
T3 407043 708 0 0
T7 233870 1359 0 0
T8 872427 1051 0 0
T9 138042 56 0 0
T10 193752 1064 0 0
T11 434492 0 0 0
T12 42084 40 0 0
T13 402999 5 0 0
T14 29474 1149 0 0
T15 0 8 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 348487 0 0
T2 229442 1978 0 0
T3 407043 788 0 0
T7 233870 3771 0 0
T8 872427 1340 0 0
T9 138042 90 0 0
T10 193752 1583 0 0
T11 434492 0 0 0
T12 42084 37 0 0
T13 402999 521 0 0
T14 29474 872 0 0
T15 0 13 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 3448247 0 0
T2 229442 19206 0 0
T3 407043 82633 0 0
T7 233870 32971 0 0
T8 872427 205218 0 0
T9 138042 2628 0 0
T10 193752 17796 0 0
T11 434492 0 0 0
T12 42084 315 0 0
T13 402999 1559 0 0
T14 29474 590 0 0
T15 0 65 0 0

Line Coverage for Instance : tb.dut.u_sm1_49
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_49
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 279797 0 0
gen_host_fifo[1].idInRange 422065402 376349 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4091121 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 279797 0 0
T1 291226 740 0 0
T2 229442 344 0 0
T3 407043 709 0 0
T7 233870 1273 0 0
T8 872427 0 0 0
T9 138042 82 0 0
T10 193752 1161 0 0
T11 434492 0 0 0
T12 42084 43 0 0
T13 402999 2 0 0
T14 0 6 0 0
T15 0 5 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 376349 0 0
T1 291226 788 0 0
T2 229442 1284 0 0
T3 407043 853 0 0
T7 233870 3050 0 0
T8 872427 0 0 0
T9 138042 67 0 0
T10 193752 46 0 0
T11 434492 0 0 0
T12 42084 40 0 0
T13 402999 2 0 0
T14 0 5 0 0
T15 0 3 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4091121 0 0
T1 291226 95626 0 0
T2 229442 21399 0 0
T3 407043 81949 0 0
T7 233870 32813 0 0
T8 872427 0 0 0
T9 138042 1626 0 0
T10 193752 23575 0 0
T11 434492 0 0 0
T12 42084 324 0 0
T13 402999 239 0 0
T14 0 11 0 0
T15 0 33 0 0

Line Coverage for Instance : tb.dut.u_sm1_50
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_50
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T7,T9
11CoveredT2,T7,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110CoveredT1,T2,T3
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T9
101CoveredT2,T7,T9
110Not Covered
111CoveredT2,T7,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T9

Assert Coverage for Instance : tb.dut.u_sm1_50
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 291598 0 0
gen_host_fifo[1].idInRange 422065402 394514 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4514753 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 291598 0 0
T2 229442 259 0 0
T3 407043 0 0 0
T7 233870 1982 0 0
T8 872427 0 0 0
T9 138042 68 0 0
T10 193752 998 0 0
T11 434492 0 0 0
T12 42084 29 0 0
T13 402999 5 0 0
T14 29474 8 0 0
T15 0 9 0 0
T16 0 57 0 0
T17 0 154 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 394514 0 0
T2 229442 2024 0 0
T3 407043 0 0 0
T7 233870 2304 0 0
T8 872427 0 0 0
T9 138042 36 0 0
T10 193752 3952 0 0
T11 434492 0 0 0
T12 42084 35 0 0
T13 402999 9 0 0
T14 29474 6 0 0
T15 0 11 0 0
T16 0 78 0 0
T17 0 155 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4514753 0 0
T2 229442 20810 0 0
T3 407043 0 0 0
T7 233870 36121 0 0
T8 872427 0 0 0
T9 138042 1185 0 0
T10 193752 13462 0 0
T11 434492 0 0 0
T12 42084 295 0 0
T13 402999 1303 0 0
T14 29474 14 0 0
T15 0 75 0 0
T16 0 205 0 0
T17 0 303 0 0

Line Coverage for Instance : tb.dut.u_sm1_51
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_51
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_51
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 304227 0 0
gen_host_fifo[1].idInRange 422065402 412148 0 0
maxM 900 900 0 0
rspIdInRange 422065402 3421647 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 304227 0 0
T2 229442 333 0 0
T3 407043 0 0 0
T7 233870 206 0 0
T8 872427 724 0 0
T9 138042 63 0 0
T10 193752 605 0 0
T11 434492 660 0 0
T12 42084 39 0 0
T13 402999 11 0 0
T14 29474 1150 0 0
T15 0 6 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 412148 0 0
T2 229442 1901 0 0
T3 407043 0 0 0
T7 233870 3386 0 0
T8 872427 864 0 0
T9 138042 92 0 0
T10 193752 1592 0 0
T11 434492 837 0 0
T12 42084 60 0 0
T13 402999 4 0 0
T14 29474 835 0 0
T15 0 2 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 3421647 0 0
T2 229442 19550 0 0
T3 407043 0 0 0
T7 233870 24234 0 0
T8 872427 95907 0 0
T9 138042 4334 0 0
T10 193752 18372 0 0
T11 434492 97499 0 0
T12 42084 323 0 0
T13 402999 3202 0 0
T14 29474 582 0 0
T15 0 46 0 0

Line Coverage for Instance : tb.dut.u_sm1_52
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_52
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_52
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 287169 0 0
gen_host_fifo[1].idInRange 422065402 372293 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4413759 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 287169 0 0
T2 229442 1378 0 0
T3 407043 0 0 0
T7 233870 1434 0 0
T8 872427 697 0 0
T9 138042 83 0 0
T10 193752 655 0 0
T11 434492 695 0 0
T12 42084 49 0 0
T13 402999 8 0 0
T14 29474 4 0 0
T15 0 8 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 372293 0 0
T2 229442 2458 0 0
T3 407043 0 0 0
T7 233870 2168 0 0
T8 872427 782 0 0
T9 138042 122 0 0
T10 193752 737 0 0
T11 434492 907 0 0
T12 42084 49 0 0
T13 402999 9 0 0
T14 29474 7 0 0
T15 0 11 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4413759 0 0
T2 229442 25828 0 0
T3 407043 0 0 0
T7 233870 31679 0 0
T8 872427 108719 0 0
T9 138042 3166 0 0
T10 193752 16326 0 0
T11 434492 100162 0 0
T12 42084 283 0 0
T13 402999 1617 0 0
T14 29474 11 0 0
T15 0 66 0 0

Line Coverage for Instance : tb.dut.u_sm1_53
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_53
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_53
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 282805 0 0
gen_host_fifo[1].idInRange 422065402 362226 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4493228 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 282805 0 0
T2 229442 1109 0 0
T3 407043 838 0 0
T7 233870 291 0 0
T8 872427 718 0 0
T9 138042 79 0 0
T10 193752 625 0 0
T11 434492 766 0 0
T12 42084 41 0 0
T13 402999 81 0 0
T14 29474 1129 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 362226 0 0
T2 229442 1342 0 0
T3 407043 924 0 0
T7 233870 2558 0 0
T8 872427 927 0 0
T9 138042 87 0 0
T10 193752 47 0 0
T11 434492 960 0 0
T12 42084 39 0 0
T13 402999 7 0 0
T14 29474 861 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4493228 0 0
T2 229442 23075 0 0
T3 407043 96312 0 0
T7 233870 32754 0 0
T8 872427 116032 0 0
T9 138042 1306 0 0
T10 193752 17478 0 0
T11 434492 125065 0 0
T12 42084 326 0 0
T13 402999 2606 0 0
T14 29474 584 0 0

Line Coverage for Instance : tb.dut.u_sm1_54
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_54
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_54
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 333105 0 0
gen_host_fifo[1].idInRange 422065402 449843 0 0
maxM 900 900 0 0
rspIdInRange 422065402 5261990 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 333105 0 0
T2 229442 688 0 0
T3 407043 795 0 0
T7 233870 476 0 0
T8 872427 725 0 0
T9 138042 60 0 0
T10 193752 679 0 0
T11 434492 644 0 0
T12 42084 39 0 0
T13 402999 3 0 0
T14 29474 3 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 449843 0 0
T2 229442 3895 0 0
T3 407043 975 0 0
T7 233870 3488 0 0
T8 872427 893 0 0
T9 138042 95 0 0
T10 193752 2893 0 0
T11 434492 770 0 0
T12 42084 60 0 0
T13 402999 7 0 0
T14 29474 8 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 5261990 0 0
T2 229442 21362 0 0
T3 407043 103680 0 0
T7 233870 31582 0 0
T8 872427 114716 0 0
T9 138042 3923 0 0
T10 193752 20813 0 0
T11 434492 92339 0 0
T12 42084 358 0 0
T13 402999 435 0 0
T14 29474 11 0 0

Line Coverage for Instance : tb.dut.u_sm1_55
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_55
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T7
11CoveredT2,T8,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110CoveredT1,T2,T3
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT2,T8,T7
110Not Covered
111CoveredT2,T8,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T8,T7

Assert Coverage for Instance : tb.dut.u_sm1_55
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 292684 0 0
gen_host_fifo[1].idInRange 422065402 384679 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4571364 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 292684 0 0
T2 229442 466 0 0
T3 407043 0 0 0
T7 233870 1542 0 0
T8 872427 745 0 0
T9 138042 64 0 0
T10 193752 955 0 0
T11 434492 0 0 0
T12 42084 41 0 0
T13 402999 532 0 0
T14 29474 2961 0 0
T15 0 8 0 0
T16 0 56 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 384679 0 0
T2 229442 1297 0 0
T3 407043 0 0 0
T7 233870 1569 0 0
T8 872427 867 0 0
T9 138042 83 0 0
T10 193752 1433 0 0
T11 434492 0 0 0
T12 42084 39 0 0
T13 402999 2 0 0
T14 29474 2119 0 0
T15 0 10 0 0
T16 0 80 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4571364 0 0
T2 229442 25670 0 0
T3 407043 0 0 0
T7 233870 31109 0 0
T8 872427 124361 0 0
T9 138042 1673 0 0
T10 193752 19577 0 0
T11 434492 0 0 0
T12 42084 332 0 0
T13 402999 1662 0 0
T14 29474 1495 0 0
T15 0 69 0 0
T16 0 224 0 0

Line Coverage for Instance : tb.dut.u_sm1_56
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_56
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T8
11CoveredT2,T3,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110CoveredT1,T2,T3
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T8
110Not Covered
111CoveredT2,T3,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_56
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 307787 0 0
gen_host_fifo[1].idInRange 422065402 398990 0 0
maxM 900 900 0 0
rspIdInRange 422065402 4649260 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 307787 0 0
T2 229442 1584 0 0
T3 407043 763 0 0
T7 233870 804 0 0
T8 872427 1375 0 0
T9 138042 74 0 0
T10 193752 225 0 0
T11 434492 708 0 0
T12 42084 48 0 0
T13 402999 110 0 0
T14 29474 5 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 398990 0 0
T2 229442 1810 0 0
T3 407043 906 0 0
T7 233870 2430 0 0
T8 872427 1762 0 0
T9 138042 81 0 0
T10 193752 2572 0 0
T11 434492 840 0 0
T12 42084 38 0 0
T13 402999 6 0 0
T14 29474 6 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 4649260 0 0
T2 229442 21268 0 0
T3 407043 91476 0 0
T7 233870 27433 0 0
T8 872427 184484 0 0
T9 138042 3012 0 0
T10 193752 18028 0 0
T11 434492 130812 0 0
T12 42084 396 0 0
T13 402999 5218 0 0
T14 29474 11 0 0

Line Coverage for Instance : tb.dut.u_sm1_30
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_30
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT2,T3,T7
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT1,T2,T3
11CoveredT2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT1,T2,T3
11CoveredT2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT2,T3,T7
110CoveredT2,T3,T8
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT2,T3,T8
111CoveredT2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT2,T3,T8
111CoveredT2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

Assert Coverage for Instance : tb.dut.u_sm1_30
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 422065402 10357691 0 0
gen_host_fifo[1].idInRange 422065402 1917943 0 0
gen_host_fifo[2].idInRange 422065402 2025692 0 0
maxM 900 900 0 0
rspIdInRange 422065402 18268871 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 10357691 0 0
T1 291226 247 0 0
T2 229442 139274 0 0
T3 407043 4794 0 0
T7 233870 166768 0 0
T8 872427 3979 0 0
T9 138042 1910 0 0
T10 193752 121459 0 0
T11 434492 4359 0 0
T12 42084 1488 0 0
T13 402999 7305 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 1917943 0 0
T2 229442 19633 0 0
T3 407043 1724 0 0
T7 233870 40199 0 0
T8 872427 0 0 0
T9 138042 308 0 0
T10 193752 20012 0 0
T11 434492 1529 0 0
T12 42084 270 0 0
T13 402999 3009 0 0
T14 29474 792 0 0
T15 0 57 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 2025692 0 0
T2 229442 21159 0 0
T3 407043 1834 0 0
T7 233870 28197 0 0
T8 872427 0 0 0
T9 138042 396 0 0
T10 193752 16805 0 0
T11 434492 1779 0 0
T12 42084 212 0 0
T13 402999 1291 0 0
T14 29474 530 0 0
T15 0 45 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 422065402 18268871 0 0
T1 291226 58 0 0
T2 229442 74322 0 0
T3 407043 192478 0 0
T7 233870 88726 0 0
T8 872427 328771 0 0
T9 138042 145327 0 0
T10 193752 74076 0 0
T11 434492 179601 0 0
T12 42084 1707 0 0
T13 402999 6102 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%