Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7565979	0	0
GntImpliesValid_A	2147483647	7565979	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7565979	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	459935961	0	0
ReadyAndValidImplyGrant_A	2147483647	7565979	0	0
ReqAndReadyImplyGrant_A	2147483647	7565979	0	0
ReqImpliesValid_A	2147483647	34289411	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44905	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7565979	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6989424	6988584	0	0
T2	5506608	5506440	0	0
T3	9769032	9768936	0	0
T7	5612880	5612832	0	0
T8	20938248	20938128	0	0
T9	3313008	3312936	0	0
T10	4650048	4649904	0	0
T11	10427808	10427736	0	0
T12	1010016	1009056	0	0
T13	9671976	9671784	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7565979	0	0
T1	1456130	721	0	0
T2	5506608	5509	0	0
T3	9769032	9866	0	0
T7	5612880	6036	0	0
T8	20938248	14047	0	0
T9	3313008	4825	0	0
T10	4650048	4036	0	0
T11	10427808	10332	0	0
T12	1010016	2757	0	0
T13	9671976	435	0	0
T14	560006	6857	0	0
T15	0	176	0	0
T16	0	639	0	0
T17	0	925	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7565979	0	0
T1	1456130	721	0	0
T2	5506608	5509	0	0
T3	9769032	9866	0	0
T7	5612880	6036	0	0
T8	20938248	14047	0	0
T9	3313008	4825	0	0
T10	4650048	4036	0	0
T11	10427808	10332	0	0
T12	1010016	2757	0	0
T13	9671976	435	0	0
T14	560006	6857	0	0
T15	0	176	0	0
T16	0	639	0	0
T17	0	925	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6989424	6988584	0	0
T2	5506608	5506440	0	0
T3	9769032	9768936	0	0
T7	5612880	5612832	0	0
T8	20938248	20938128	0	0
T9	3313008	3312936	0	0
T10	4650048	4649904	0	0
T11	10427808	10427736	0	0
T12	1010016	1009056	0	0
T13	9671976	9671784	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6989424	6988584	0	0
T2	5506608	5506440	0	0
T3	9769032	9768936	0	0
T7	5612880	5612832	0	0
T8	20938248	20938128	0	0
T9	3313008	3312936	0	0
T10	4650048	4649904	0	0
T11	10427808	10427736	0	0
T12	1010016	1009056	0	0
T13	9671976	9671784	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7565979	0	0
T1	1456130	721	0	0
T2	5506608	5509	0	0
T3	9769032	9866	0	0
T7	5612880	6036	0	0
T8	20938248	14047	0	0
T9	3313008	4825	0	0
T10	4650048	4036	0	0
T11	10427808	10332	0	0
T12	1010016	2757	0	0
T13	9671976	435	0	0
T14	560006	6857	0	0
T15	0	176	0	0
T16	0	639	0	0
T17	0	925	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	459935961	0	0
T1	5824520	245059	0	0
T2	5506608	1879345	0	0
T3	9769032	369373	0	0
T7	5612880	1801690	0	0
T8	20938248	806846	0	0
T9	3313008	134387	0	0
T10	4650048	1527659	0	0
T11	10427808	393086	0	0
T12	1010016	55547	0	0
T13	9671976	500851	0	0
T14	117896	293	0	0
T15	0	623	0	0
T16	0	2956	0	0
T17	0	1374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7565979	0	0
T1	1456130	721	0	0
T2	5506608	5509	0	0
T3	9769032	9866	0	0
T7	5612880	6036	0	0
T8	20938248	14047	0	0
T9	3313008	4825	0	0
T10	4650048	4036	0	0
T11	10427808	10332	0	0
T12	1010016	2757	0	0
T13	9671976	435	0	0
T14	560006	6857	0	0
T15	0	176	0	0
T16	0	639	0	0
T17	0	925	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7565979	0	0
T1	1456130	721	0	0
T2	5506608	5509	0	0
T3	9769032	9866	0	0
T7	5612880	6036	0	0
T8	20938248	14047	0	0
T9	3313008	4825	0	0
T10	4650048	4036	0	0
T11	10427808	10332	0	0
T12	1010016	2757	0	0
T13	9671976	435	0	0
T14	560006	6857	0	0
T15	0	176	0	0
T16	0	639	0	0
T17	0	925	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34289411	0	0
T1	1456130	1584	0	0
T2	5506608	323559	0	0
T3	9769032	25681	0	0
T7	5612880	365201	0	0
T8	20938248	43177	0	0
T9	3313008	8122	0	0
T10	4650048	275013	0	0
T11	10427808	25895	0	0
T12	1010016	4722	0	0
T13	9671976	20370	0	0
T14	560006	22197	0	0
T15	0	236	0	0
T16	0	920	0	0
T17	0	991	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44905	0	21600
T2	229442	1	0	1
T3	407043	15	0	1
T7	233870	0	0	1
T8	872427	0	0	1
T9	138042	0	0	1
T10	193752	0	0	1
T11	434492	9	0	1
T12	42084	0	0	1
T13	402999	0	0	1
T14	58948	533	0	2
T15	11344	0	0	1
T16	47128	0	0	1
T17	31180	38	0	1
T18	89258	12	0	1
T19	8477	11	0	1
T20	65407	159	0	1
T21	0	1	0	0
T22	0	2	0	0
T23	0	21	0	0
T24	0	1	0	0
T25	0	44	0	0
T26	0	18	0	0
T27	46722	0	0	1
T28	29386	0	0	1
T29	8418	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6989424	6988584	0	0
T2	5506608	5506440	0	0
T3	9769032	9768936	0	0
T7	5612880	5612832	0	0
T8	20938248	20938128	0	0
T9	3313008	3312936	0	0
T10	4650048	4649904	0	0
T11	10427808	10427736	0	0
T12	1010016	1009056	0	0
T13	9671976	9671784	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7565979	0	0
T1	1456130	721	0	0
T2	5506608	5509	0	0
T3	9769032	9866	0	0
T7	5612880	6036	0	0
T8	20938248	14047	0	0
T9	3313008	4825	0	0
T10	4650048	4036	0	0
T11	10427808	10332	0	0
T12	1010016	2757	0	0
T13	9671976	435	0	0
T14	560006	6857	0	0
T15	0	176	0	0
T16	0	639	0	0
T17	0	925	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	825843	0	0
GntImpliesValid_A	422065402	825843	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	825843	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	12221877	0	0
ReadyAndValidImplyGrant_A	422065402	825843	0	0
ReqAndReadyImplyGrant_A	422065402	825843	0	0
ReqImpliesValid_A	422065402	2447448	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	825843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	825843	0	0
T1	291226	51	0	0
T2	229442	583	0	0
T3	407043	1483	0	0
T7	233870	671	0	0
T8	872427	1789	0	0
T9	138042	509	0	0
T10	193752	510	0	0
T11	434492	696	0	0
T12	42084	269	0	0
T13	402999	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	825843	0	0
T1	291226	51	0	0
T2	229442	583	0	0
T3	407043	1483	0	0
T7	233870	671	0	0
T8	872427	1789	0	0
T9	138042	509	0	0
T10	193752	510	0	0
T11	434492	696	0	0
T12	42084	269	0	0
T13	402999	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	825843	0	0
T1	291226	51	0	0
T2	229442	583	0	0
T3	407043	1483	0	0
T7	233870	671	0	0
T8	872427	1789	0	0
T9	138042	509	0	0
T10	193752	510	0	0
T11	434492	696	0	0
T12	42084	269	0	0
T13	402999	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	12221877	0	0
T1	291226	215	0	0
T2	229442	157694	0	0
T3	407043	5537	0	0
T7	233870	214754	0	0
T8	872427	6660	0	0
T9	138042	2079	0	0
T10	193752	162348	0	0
T11	434492	2874	0	0
T12	42084	2044	0	0
T13	402999	13765	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	825843	0	0
T1	291226	51	0	0
T2	229442	583	0	0
T3	407043	1483	0	0
T7	233870	671	0	0
T8	872427	1789	0	0
T9	138042	509	0	0
T10	193752	510	0	0
T11	434492	696	0	0
T12	42084	269	0	0
T13	402999	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	825843	0	0
T1	291226	51	0	0
T2	229442	583	0	0
T3	407043	1483	0	0
T7	233870	671	0	0
T8	872427	1789	0	0
T9	138042	509	0	0
T10	193752	510	0	0
T11	434492	696	0	0
T12	42084	269	0	0
T13	402999	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	2447448	0	0
T1	291226	96	0	0
T2	229442	13355	0	0
T3	407043	2913	0	0
T7	233870	27620	0	0
T8	872427	3209	0	0
T9	138042	680	0	0
T10	193752	12927	0	0
T11	434492	954	0	0
T12	42084	284	0	0
T13	402999	2067	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	825843	0	0
T1	291226	51	0	0
T2	229442	583	0	0
T3	407043	1483	0	0
T7	233870	671	0	0
T8	872427	1789	0	0
T9	138042	509	0	0
T10	193752	510	0	0
T11	434492	696	0	0
T12	42084	269	0	0
T13	402999	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	838266	0	0
GntImpliesValid_A	422065402	838266	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	838266	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	12443609	0	0
ReadyAndValidImplyGrant_A	422065402	838266	0	0
ReqAndReadyImplyGrant_A	422065402	838266	0	0
ReqImpliesValid_A	422065402	2444482	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	838266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	838266	0	0
T1	291226	47	0	0
T2	229442	612	0	0
T3	407043	706	0	0
T7	233870	658	0	0
T8	872427	2372	0	0
T9	138042	541	0	0
T10	193752	483	0	0
T11	434492	2232	0	0
T12	42084	306	0	0
T13	402999	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	838266	0	0
T1	291226	47	0	0
T2	229442	612	0	0
T3	407043	706	0	0
T7	233870	658	0	0
T8	872427	2372	0	0
T9	138042	541	0	0
T10	193752	483	0	0
T11	434492	2232	0	0
T12	42084	306	0	0
T13	402999	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	838266	0	0
T1	291226	47	0	0
T2	229442	612	0	0
T3	407043	706	0	0
T7	233870	658	0	0
T8	872427	2372	0	0
T9	138042	541	0	0
T10	193752	483	0	0
T11	434492	2232	0	0
T12	42084	306	0	0
T13	402999	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	12443609	0	0
T1	291226	220	0	0
T2	229442	196690	0	0
T3	407043	2988	0	0
T7	233870	214610	0	0
T8	872427	8380	0	0
T9	138042	2208	0	0
T10	193752	152044	0	0
T11	434492	7654	0	0
T12	42084	2366	0	0
T13	402999	13345	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	838266	0	0
T1	291226	47	0	0
T2	229442	612	0	0
T3	407043	706	0	0
T7	233870	658	0	0
T8	872427	2372	0	0
T9	138042	541	0	0
T10	193752	483	0	0
T11	434492	2232	0	0
T12	42084	306	0	0
T13	402999	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	838266	0	0
T1	291226	47	0	0
T2	229442	612	0	0
T3	407043	706	0	0
T7	233870	658	0	0
T8	872427	2372	0	0
T9	138042	541	0	0
T10	193752	483	0	0
T11	434492	2232	0	0
T12	42084	306	0	0
T13	402999	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	2444482	0	0
T1	291226	59	0	0
T2	229442	25920	0	0
T3	407043	1012	0	0
T7	233870	25658	0	0
T8	872427	4975	0	0
T9	138042	735	0	0
T10	193752	18027	0	0
T11	434492	4709	0	0
T12	42084	353	0	0
T13	402999	924	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	838266	0	0
T1	291226	47	0	0
T2	229442	612	0	0
T3	407043	706	0	0
T7	233870	658	0	0
T8	872427	2372	0	0
T9	138042	541	0	0
T10	193752	483	0	0
T11	434492	2232	0	0
T12	42084	306	0	0
T13	402999	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	218146	0	0
GntImpliesValid_A	422065402	218146	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	218146	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3127743	0	0
ReadyAndValidImplyGrant_A	422065402	218146	0	0
ReqAndReadyImplyGrant_A	422065402	218146	0	0
ReqImpliesValid_A	422065402	596557	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	218146	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	218146	0	0
T2	229442	159	0	0
T3	407043	1003	0	0
T7	233870	150	0	0
T8	872427	0	0	0
T9	138042	124	0	0
T10	193752	104	0	0
T11	434492	0	0	0
T12	42084	97	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	11	0	0
T16	0	93	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	218146	0	0
T2	229442	159	0	0
T3	407043	1003	0	0
T7	233870	150	0	0
T8	872427	0	0	0
T9	138042	124	0	0
T10	193752	104	0	0
T11	434492	0	0	0
T12	42084	97	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	11	0	0
T16	0	93	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	218146	0	0
T2	229442	159	0	0
T3	407043	1003	0	0
T7	233870	150	0	0
T8	872427	0	0	0
T9	138042	124	0	0
T10	193752	104	0	0
T11	434492	0	0	0
T12	42084	97	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	11	0	0
T16	0	93	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3127743	0	0
T1	291226	1	0	0
T2	229442	49567	0	0
T3	407043	3357	0	0
T7	233870	47964	0	0
T8	872427	1	0	0
T9	138042	524	0	0
T10	193752	34315	0	0
T11	434492	1	0	0
T12	42084	701	0	0
T13	402999	4052	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	218146	0	0
T2	229442	159	0	0
T3	407043	1003	0	0
T7	233870	150	0	0
T8	872427	0	0	0
T9	138042	124	0	0
T10	193752	104	0	0
T11	434492	0	0	0
T12	42084	97	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	11	0	0
T16	0	93	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	218146	0	0
T2	229442	159	0	0
T3	407043	1003	0	0
T7	233870	150	0	0
T8	872427	0	0	0
T9	138042	124	0	0
T10	193752	104	0	0
T11	434492	0	0	0
T12	42084	97	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	11	0	0
T16	0	93	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	596557	0	0
T2	229442	5969	0	0
T3	407043	2518	0	0
T7	233870	1550	0	0
T8	872427	0	0	0
T9	138042	140	0	0
T10	193752	1967	0	0
T11	434492	0	0	0
T12	42084	102	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	15	0	0
T16	0	102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	218146	0	0
T2	229442	159	0	0
T3	407043	1003	0	0
T7	233870	150	0	0
T8	872427	0	0	0
T9	138042	124	0	0
T10	193752	104	0	0
T11	434492	0	0	0
T12	42084	97	0	0
T13	402999	15	0	0
T14	29474	11	0	0
T15	0	11	0	0
T16	0	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	209029	0	0
GntImpliesValid_A	422065402	209029	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	209029	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3145100	0	0
ReadyAndValidImplyGrant_A	422065402	209029	0	0
ReqAndReadyImplyGrant_A	422065402	209029	0	0
ReqImpliesValid_A	422065402	573944	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	209029	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209029	0	0
T2	229442	178	0	0
T3	407043	478	0	0
T7	233870	189	0	0
T8	872427	0	0	0
T9	138042	152	0	0
T10	193752	111	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209029	0	0
T2	229442	178	0	0
T3	407043	478	0	0
T7	233870	189	0	0
T8	872427	0	0	0
T9	138042	152	0	0
T10	193752	111	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209029	0	0
T2	229442	178	0	0
T3	407043	478	0	0
T7	233870	189	0	0
T8	872427	0	0	0
T9	138042	152	0	0
T10	193752	111	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3145100	0	0
T1	291226	1	0	0
T2	229442	61086	0	0
T3	407043	1486	0	0
T7	233870	60129	0	0
T8	872427	1	0	0
T9	138042	658	0	0
T10	193752	38098	0	0
T11	434492	1	0	0
T12	42084	397	0	0
T13	402999	3684	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209029	0	0
T2	229442	178	0	0
T3	407043	478	0	0
T7	233870	189	0	0
T8	872427	0	0	0
T9	138042	152	0	0
T10	193752	111	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209029	0	0
T2	229442	178	0	0
T3	407043	478	0	0
T7	233870	189	0	0
T8	872427	0	0	0
T9	138042	152	0	0
T10	193752	111	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	573944	0	0
T2	229442	3416	0	0
T3	407043	1101	0	0
T7	233870	3364	0	0
T8	872427	0	0	0
T9	138042	177	0	0
T10	193752	2054	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209029	0	0
T2	229442	178	0	0
T3	407043	478	0	0
T7	233870	189	0	0
T8	872427	0	0	0
T9	138042	152	0	0
T10	193752	111	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	11	0	0
T14	29474	12	0	0
T15	0	6	0	0
T16	0	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T2,T8,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T8,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T8,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T7
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T7
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	215812	0	0
GntImpliesValid_A	422065402	215812	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	215812	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	4538743	0	0
ReadyAndValidImplyGrant_A	422065402	215812	0	0
ReqAndReadyImplyGrant_A	422065402	215812	0	0
ReqImpliesValid_A	422065402	1050181	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	215812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215812	0	0
T2	229442	158	0	0
T3	407043	0	0	0
T7	233870	179	0	0
T8	872427	1124	0	0
T9	138042	140	0	0
T10	193752	100	0	0
T11	434492	542	0	0
T12	42084	57	0	0
T13	402999	16	0	0
T14	29474	6	0	0
T15	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215812	0	0
T2	229442	158	0	0
T3	407043	0	0	0
T7	233870	179	0	0
T8	872427	1124	0	0
T9	138042	140	0	0
T10	193752	100	0	0
T11	434492	542	0	0
T12	42084	57	0	0
T13	402999	16	0	0
T14	29474	6	0	0
T15	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215812	0	0
T2	229442	158	0	0
T3	407043	0	0	0
T7	233870	179	0	0
T8	872427	1124	0	0
T9	138042	140	0	0
T10	193752	100	0	0
T11	434492	542	0	0
T12	42084	57	0	0
T13	402999	16	0	0
T14	29474	6	0	0
T15	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	4538743	0	0
T2	229442	53268	0	0
T3	407043	0	0	0
T7	233870	16823	0	0
T8	872427	37525	0	0
T9	138042	795	0	0
T10	193752	60297	0	0
T11	434492	2555	0	0
T12	42084	712	0	0
T13	402999	2517	0	0
T14	29474	28	0	0
T15	0	129	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215812	0	0
T2	229442	158	0	0
T3	407043	0	0	0
T7	233870	179	0	0
T8	872427	1124	0	0
T9	138042	140	0	0
T10	193752	100	0	0
T11	434492	542	0	0
T12	42084	57	0	0
T13	402999	16	0	0
T14	29474	6	0	0
T15	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215812	0	0
T2	229442	158	0	0
T3	407043	0	0	0
T7	233870	179	0	0
T8	872427	1124	0	0
T9	138042	140	0	0
T10	193752	100	0	0
T11	434492	542	0	0
T12	42084	57	0	0
T13	402999	16	0	0
T14	29474	6	0	0
T15	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	1050181	0	0
T2	229442	1932	0	0
T3	407043	0	0	0
T7	233870	706	0	0
T8	872427	13354	0	0
T9	138042	194	0	0
T10	193752	3555	0	0
T11	434492	1451	0	0
T12	42084	57	0	0
T13	402999	230	0	0
T14	29474	6	0	0
T15	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215812	0	0
T2	229442	158	0	0
T3	407043	0	0	0
T7	233870	179	0	0
T8	872427	1124	0	0
T9	138042	140	0	0
T10	193752	100	0	0
T11	434492	542	0	0
T12	42084	57	0	0
T13	402999	16	0	0
T14	29474	6	0	0
T15	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T9

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	204793	0	0
GntImpliesValid_A	422065402	204793	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	204793	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	5507635	0	0
ReadyAndValidImplyGrant_A	422065402	204793	0	0
ReqAndReadyImplyGrant_A	422065402	204793	0	0
ReqImpliesValid_A	422065402	1278375	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	204793	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	204793	0	0
T2	229442	145	0	0
T3	407043	0	0	0
T7	233870	174	0	0
T8	872427	0	0	0
T9	138042	141	0	0
T10	193752	124	0	0
T11	434492	447	0	0
T12	42084	63	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	204793	0	0
T2	229442	145	0	0
T3	407043	0	0	0
T7	233870	174	0	0
T8	872427	0	0	0
T9	138042	141	0	0
T10	193752	124	0	0
T11	434492	447	0	0
T12	42084	63	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	204793	0	0
T2	229442	145	0	0
T3	407043	0	0	0
T7	233870	174	0	0
T8	872427	0	0	0
T9	138042	141	0	0
T10	193752	124	0	0
T11	434492	447	0	0
T12	42084	63	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	5507635	0	0
T2	229442	118804	0	0
T3	407043	0	0	0
T7	233870	22415	0	0
T8	872427	0	0	0
T9	138042	1783	0	0
T10	193752	29921	0	0
T11	434492	2030	0	0
T12	42084	875	0	0
T13	402999	632	0	0
T14	29474	53	0	0
T15	0	99	0	0
T16	0	1952	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	204793	0	0
T2	229442	145	0	0
T3	407043	0	0	0
T7	233870	174	0	0
T8	872427	0	0	0
T9	138042	141	0	0
T10	193752	124	0	0
T11	434492	447	0	0
T12	42084	63	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	204793	0	0
T2	229442	145	0	0
T3	407043	0	0	0
T7	233870	174	0	0
T8	872427	0	0	0
T9	138042	141	0	0
T10	193752	124	0	0
T11	434492	447	0	0
T12	42084	63	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	1278375	0	0
T2	229442	20348	0	0
T3	407043	0	0	0
T7	233870	1465	0	0
T8	872427	0	0	0
T9	138042	311	0	0
T10	193752	947	0	0
T11	434492	1374	0	0
T12	42084	72	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	204793	0	0
T2	229442	145	0	0
T3	407043	0	0	0
T7	233870	174	0	0
T8	872427	0	0	0
T9	138042	141	0	0
T10	193752	124	0	0
T11	434492	447	0	0
T12	42084	63	0	0
T13	402999	13	0	0
T14	29474	11	0	0
T15	0	10	0	0
T16	0	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	200126	0	0
GntImpliesValid_A	422065402	200126	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	200126	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	4698379	0	0
ReadyAndValidImplyGrant_A	422065402	200126	0	0
ReqAndReadyImplyGrant_A	422065402	200126	0	0
ReqImpliesValid_A	422065402	1061221	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	200126	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	200126	0	0
T2	229442	147	0	0
T3	407043	550	0	0
T7	233870	180	0	0
T8	872427	460	0	0
T9	138042	139	0	0
T10	193752	102	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	14	0	0
T14	29474	1474	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	200126	0	0
T2	229442	147	0	0
T3	407043	550	0	0
T7	233870	180	0	0
T8	872427	460	0	0
T9	138042	139	0	0
T10	193752	102	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	14	0	0
T14	29474	1474	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	200126	0	0
T2	229442	147	0	0
T3	407043	550	0	0
T7	233870	180	0	0
T8	872427	460	0	0
T9	138042	139	0	0
T10	193752	102	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	14	0	0
T14	29474	1474	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	4698379	0	0
T2	229442	55687	0	0
T3	407043	4231	0	0
T7	233870	14636	0	0
T8	872427	2686	0	0
T9	138042	979	0	0
T10	193752	30584	0	0
T11	434492	0	0	0
T12	42084	1573	0	0
T13	402999	4216	0	0
T14	29474	172	0	0
T15	0	223	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	200126	0	0
T2	229442	147	0	0
T3	407043	550	0	0
T7	233870	180	0	0
T8	872427	460	0	0
T9	138042	139	0	0
T10	193752	102	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	14	0	0
T14	29474	1474	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	200126	0	0
T2	229442	147	0	0
T3	407043	550	0	0
T7	233870	180	0	0
T8	872427	460	0	0
T9	138042	139	0	0
T10	193752	102	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	14	0	0
T14	29474	1474	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	1061221	0	0
T2	229442	4551	0	0
T3	407043	2026	0	0
T7	233870	512	0	0
T8	872427	1535	0	0
T9	138042	224	0	0
T10	193752	2740	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	550	0	0
T14	29474	12114	0	0
T15	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	200126	0	0
T2	229442	147	0	0
T3	407043	550	0	0
T7	233870	180	0	0
T8	872427	460	0	0
T9	138042	139	0	0
T10	193752	102	0	0
T11	434492	0	0	0
T12	42084	79	0	0
T13	402999	14	0	0
T14	29474	1474	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T9

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	209707	0	0
GntImpliesValid_A	422065402	209707	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	209707	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	4996907	0	0
ReadyAndValidImplyGrant_A	422065402	209707	0	0
ReqAndReadyImplyGrant_A	422065402	209707	0	0
ReqImpliesValid_A	422065402	1153746	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	209707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209707	0	0
T2	229442	164	0	0
T3	407043	0	0	0
T7	233870	172	0	0
T8	872427	0	0	0
T9	138042	134	0	0
T10	193752	120	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	90	0	0
T17	0	297	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209707	0	0
T2	229442	164	0	0
T3	407043	0	0	0
T7	233870	172	0	0
T8	872427	0	0	0
T9	138042	134	0	0
T10	193752	120	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	90	0	0
T17	0	297	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209707	0	0
T2	229442	164	0	0
T3	407043	0	0	0
T7	233870	172	0	0
T8	872427	0	0	0
T9	138042	134	0	0
T10	193752	120	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	90	0	0
T17	0	297	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	4996907	0	0
T2	229442	79163	0	0
T3	407043	0	0	0
T7	233870	54739	0	0
T8	872427	0	0	0
T9	138042	776	0	0
T10	193752	244166	0	0
T11	434492	0	0	0
T12	42084	570	0	0
T13	402999	974	0	0
T14	29474	40	0	0
T15	0	172	0	0
T16	0	1004	0	0
T17	0	1374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209707	0	0
T2	229442	164	0	0
T3	407043	0	0	0
T7	233870	172	0	0
T8	872427	0	0	0
T9	138042	134	0	0
T10	193752	120	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	90	0	0
T17	0	297	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209707	0	0
T2	229442	164	0	0
T3	407043	0	0	0
T7	233870	172	0	0
T8	872427	0	0	0
T9	138042	134	0	0
T10	193752	120	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	90	0	0
T17	0	297	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	1153746	0	0
T2	229442	5477	0	0
T3	407043	0	0	0
T7	233870	4247	0	0
T8	872427	0	0	0
T9	138042	181	0	0
T10	193752	32837	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	126	0	0
T17	0	351	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209707	0	0
T2	229442	164	0	0
T3	407043	0	0	0
T7	233870	172	0	0
T8	872427	0	0	0
T9	138042	134	0	0
T10	193752	120	0	0
T11	434492	0	0	0
T12	42084	84	0	0
T13	402999	11	0	0
T14	29474	6	0	0
T15	0	13	0	0
T16	0	90	0	0
T17	0	297	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T2,T8,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T8,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T7
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	199877	0	0
GntImpliesValid_A	422065402	199877	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	199877	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3049407	0	0
ReadyAndValidImplyGrant_A	422065402	199877	0	0
ReqAndReadyImplyGrant_A	422065402	199877	0	0
ReqImpliesValid_A	422065402	529332	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	199877	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	199877	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	550	0	0
T9	138042	140	0	0
T10	193752	101	0	0
T11	434492	432	0	0
T12	42084	80	0	0
T13	402999	12	0	0
T14	29474	425	0	0
T15	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	199877	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	550	0	0
T9	138042	140	0	0
T10	193752	101	0	0
T11	434492	432	0	0
T12	42084	80	0	0
T13	402999	12	0	0
T14	29474	425	0	0
T15	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	199877	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	550	0	0
T9	138042	140	0	0
T10	193752	101	0	0
T11	434492	432	0	0
T12	42084	80	0	0
T13	402999	12	0	0
T14	29474	425	0	0
T15	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3049407	0	0
T1	291226	1	0	0
T2	229442	45312	0	0
T3	407043	1	0	0
T7	233870	54968	0	0
T8	872427	1889	0	0
T9	138042	607	0	0
T10	193752	32671	0	0
T11	434492	1293	0	0
T12	42084	618	0	0
T13	402999	2574	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	199877	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	550	0	0
T9	138042	140	0	0
T10	193752	101	0	0
T11	434492	432	0	0
T12	42084	80	0	0
T13	402999	12	0	0
T14	29474	425	0	0
T15	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	199877	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	550	0	0
T9	138042	140	0	0
T10	193752	101	0	0
T11	434492	432	0	0
T12	42084	80	0	0
T13	402999	12	0	0
T14	29474	425	0	0
T15	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	529332	0	0
T2	229442	2809	0	0
T3	407043	0	0	0
T7	233870	3607	0	0
T8	872427	1207	0	0
T9	138042	158	0	0
T10	193752	1351	0	0
T11	434492	1110	0	0
T12	42084	86	0	0
T13	402999	584	0	0
T14	29474	680	0	0
T15	0	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	199877	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	550	0	0
T9	138042	140	0	0
T10	193752	101	0	0
T11	434492	432	0	0
T12	42084	80	0	0
T13	402999	12	0	0
T14	29474	425	0	0
T15	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	209746	0	0
GntImpliesValid_A	422065402	209746	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	209746	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3144595	0	0
ReadyAndValidImplyGrant_A	422065402	209746	0	0
ReqAndReadyImplyGrant_A	422065402	209746	0	0
ReqImpliesValid_A	422065402	585323	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	209746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209746	0	0
T2	229442	166	0	0
T3	407043	503	0	0
T7	233870	155	0	0
T8	872427	532	0	0
T9	138042	129	0	0
T10	193752	108	0	0
T11	434492	562	0	0
T12	42084	81	0	0
T13	402999	6	0	0
T14	29474	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209746	0	0
T2	229442	166	0	0
T3	407043	503	0	0
T7	233870	155	0	0
T8	872427	532	0	0
T9	138042	129	0	0
T10	193752	108	0	0
T11	434492	562	0	0
T12	42084	81	0	0
T13	402999	6	0	0
T14	29474	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209746	0	0
T2	229442	166	0	0
T3	407043	503	0	0
T7	233870	155	0	0
T8	872427	532	0	0
T9	138042	129	0	0
T10	193752	108	0	0
T11	434492	562	0	0
T12	42084	81	0	0
T13	402999	6	0	0
T14	29474	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3144595	0	0
T1	291226	1	0	0
T2	229442	58499	0	0
T3	407043	1690	0	0
T7	233870	50577	0	0
T8	872427	1763	0	0
T9	138042	591	0	0
T10	193752	41304	0	0
T11	434492	1972	0	0
T12	42084	672	0	0
T13	402999	1495	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209746	0	0
T2	229442	166	0	0
T3	407043	503	0	0
T7	233870	155	0	0
T8	872427	532	0	0
T9	138042	129	0	0
T10	193752	108	0	0
T11	434492	562	0	0
T12	42084	81	0	0
T13	402999	6	0	0
T14	29474	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209746	0	0
T2	229442	166	0	0
T3	407043	503	0	0
T7	233870	155	0	0
T8	872427	532	0	0
T9	138042	129	0	0
T10	193752	108	0	0
T11	434492	562	0	0
T12	42084	81	0	0
T13	402999	6	0	0
T14	29474	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	585323	0	0
T2	229442	3051	0	0
T3	407043	1182	0	0
T7	233870	3312	0	0
T8	872427	1221	0	0
T9	138042	141	0	0
T10	193752	2327	0	0
T11	434492	1239	0	0
T12	42084	85	0	0
T13	402999	6	0	0
T14	29474	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	209746	0	0
T2	229442	166	0	0
T3	407043	503	0	0
T7	233870	155	0	0
T8	872427	532	0	0
T9	138042	129	0	0
T10	193752	108	0	0
T11	434492	562	0	0
T12	42084	81	0	0
T13	402999	6	0	0
T14	29474	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	227058	0	0
GntImpliesValid_A	422065402	227058	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	227058	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3140130	0	0
ReadyAndValidImplyGrant_A	422065402	227058	0	0
ReqAndReadyImplyGrant_A	422065402	227058	0	0
ReqImpliesValid_A	422065402	609533	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	227058	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	227058	0	0
T2	229442	151	0	0
T3	407043	483	0	0
T7	233870	157	0	0
T8	872427	487	0	0
T9	138042	146	0	0
T10	193752	85	0	0
T11	434492	425	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	536	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	227058	0	0
T2	229442	151	0	0
T3	407043	483	0	0
T7	233870	157	0	0
T8	872427	487	0	0
T9	138042	146	0	0
T10	193752	85	0	0
T11	434492	425	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	536	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	227058	0	0
T2	229442	151	0	0
T3	407043	483	0	0
T7	233870	157	0	0
T8	872427	487	0	0
T9	138042	146	0	0
T10	193752	85	0	0
T11	434492	425	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	536	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3140130	0	0
T1	291226	1	0	0
T2	229442	47626	0	0
T3	407043	1519	0	0
T7	233870	45256	0	0
T8	872427	1696	0	0
T9	138042	606	0	0
T10	193752	29500	0	0
T11	434492	1258	0	0
T12	42084	617	0	0
T13	402999	5222	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	227058	0	0
T2	229442	151	0	0
T3	407043	483	0	0
T7	233870	157	0	0
T8	872427	487	0	0
T9	138042	146	0	0
T10	193752	85	0	0
T11	434492	425	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	536	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	227058	0	0
T2	229442	151	0	0
T3	407043	483	0	0
T7	233870	157	0	0
T8	872427	487	0	0
T9	138042	146	0	0
T10	193752	85	0	0
T11	434492	425	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	536	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	609533	0	0
T2	229442	4115	0	0
T3	407043	1225	0	0
T7	233870	3395	0	0
T8	872427	1173	0	0
T9	138042	169	0	0
T10	193752	1231	0	0
T11	434492	1153	0	0
T12	42084	101	0	0
T13	402999	346	0	0
T14	29474	800	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	227058	0	0
T2	229442	151	0	0
T3	407043	483	0	0
T7	233870	157	0	0
T8	872427	487	0	0
T9	138042	146	0	0
T10	193752	85	0	0
T11	434492	425	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	536	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T2,T8,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T8,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T7
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	212252	0	0
GntImpliesValid_A	422065402	212252	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	212252	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3087284	0	0
ReadyAndValidImplyGrant_A	422065402	212252	0	0
ReqAndReadyImplyGrant_A	422065402	212252	0	0
ReqImpliesValid_A	422065402	558349	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	212252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	212252	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	187	0	0
T8	872427	495	0	0
T9	138042	144	0	0
T10	193752	109	0	0
T11	434492	546	0	0
T12	42084	84	0	0
T13	402999	20	0	0
T14	29474	9	0	0
T15	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	212252	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	187	0	0
T8	872427	495	0	0
T9	138042	144	0	0
T10	193752	109	0	0
T11	434492	546	0	0
T12	42084	84	0	0
T13	402999	20	0	0
T14	29474	9	0	0
T15	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	212252	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	187	0	0
T8	872427	495	0	0
T9	138042	144	0	0
T10	193752	109	0	0
T11	434492	546	0	0
T12	42084	84	0	0
T13	402999	20	0	0
T14	29474	9	0	0
T15	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3087284	0	0
T1	291226	1	0	0
T2	229442	49688	0	0
T3	407043	1	0	0
T7	233870	54288	0	0
T8	872427	1610	0	0
T9	138042	564	0	0
T10	193752	29873	0	0
T11	434492	1962	0	0
T12	42084	658	0	0
T13	402999	6367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	212252	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	187	0	0
T8	872427	495	0	0
T9	138042	144	0	0
T10	193752	109	0	0
T11	434492	546	0	0
T12	42084	84	0	0
T13	402999	20	0	0
T14	29474	9	0	0
T15	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	212252	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	187	0	0
T8	872427	495	0	0
T9	138042	144	0	0
T10	193752	109	0	0
T11	434492	546	0	0
T12	42084	84	0	0
T13	402999	20	0	0
T14	29474	9	0	0
T15	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	558349	0	0
T2	229442	3362	0	0
T3	407043	0	0	0
T7	233870	4562	0	0
T8	872427	1179	0	0
T9	138042	179	0	0
T10	193752	3586	0	0
T11	434492	1108	0	0
T12	42084	93	0	0
T13	402999	1874	0	0
T14	29474	9	0	0
T15	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	212252	0	0
T2	229442	148	0	0
T3	407043	0	0	0
T7	233870	187	0	0
T8	872427	495	0	0
T9	138042	144	0	0
T10	193752	109	0	0
T11	434492	546	0	0
T12	42084	84	0	0
T13	402999	20	0	0
T14	29474	9	0	0
T15	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	201989	0	0
GntImpliesValid_A	422065402	201989	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	201989	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3118298	0	0
ReadyAndValidImplyGrant_A	422065402	201989	0	0
ReqAndReadyImplyGrant_A	422065402	201989	0	0
ReqImpliesValid_A	422065402	518489	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	201989	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201989	0	0
T2	229442	141	0	0
T3	407043	0	0	0
T7	233870	191	0	0
T8	872427	0	0	0
T9	138042	139	0	0
T10	193752	114	0	0
T11	434492	0	0	0
T12	42084	88	0	0
T13	402999	12	0	0
T14	29474	1050	0	0
T15	0	11	0	0
T16	0	87	0	0
T17	0	325	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201989	0	0
T2	229442	141	0	0
T3	407043	0	0	0
T7	233870	191	0	0
T8	872427	0	0	0
T9	138042	139	0	0
T10	193752	114	0	0
T11	434492	0	0	0
T12	42084	88	0	0
T13	402999	12	0	0
T14	29474	1050	0	0
T15	0	11	0	0
T16	0	87	0	0
T17	0	325	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201989	0	0
T2	229442	141	0	0
T3	407043	0	0	0
T7	233870	191	0	0
T8	872427	0	0	0
T9	138042	139	0	0
T10	193752	114	0	0
T11	434492	0	0	0
T12	42084	88	0	0
T13	402999	12	0	0
T14	29474	1050	0	0
T15	0	11	0	0
T16	0	87	0	0
T17	0	325	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3118298	0	0
T1	291226	1	0	0
T2	229442	45990	0	0
T3	407043	1	0	0
T7	233870	56192	0	0
T8	872427	1	0	0
T9	138042	591	0	0
T10	193752	35384	0	0
T11	434492	1	0	0
T12	42084	703	0	0
T13	402999	3354	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201989	0	0
T2	229442	141	0	0
T3	407043	0	0	0
T7	233870	191	0	0
T8	872427	0	0	0
T9	138042	139	0	0
T10	193752	114	0	0
T11	434492	0	0	0
T12	42084	88	0	0
T13	402999	12	0	0
T14	29474	1050	0	0
T15	0	11	0	0
T16	0	87	0	0
T17	0	325	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201989	0	0
T2	229442	141	0	0
T3	407043	0	0	0
T7	233870	191	0	0
T8	872427	0	0	0
T9	138042	139	0	0
T10	193752	114	0	0
T11	434492	0	0	0
T12	42084	88	0	0
T13	402999	12	0	0
T14	29474	1050	0	0
T15	0	11	0	0
T16	0	87	0	0
T17	0	325	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	518489	0	0
T2	229442	2944	0	0
T3	407043	0	0	0
T7	233870	2862	0	0
T8	872427	0	0	0
T9	138042	162	0	0
T10	193752	2082	0	0
T11	434492	0	0	0
T12	42084	102	0	0
T13	402999	655	0	0
T14	29474	2047	0	0
T15	0	11	0	0
T16	0	155	0	0
T17	0	331	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201989	0	0
T2	229442	141	0	0
T3	407043	0	0	0
T7	233870	191	0	0
T8	872427	0	0	0
T9	138042	139	0	0
T10	193752	114	0	0
T11	434492	0	0	0
T12	42084	88	0	0
T13	402999	12	0	0
T14	29474	1050	0	0
T15	0	11	0	0
T16	0	87	0	0
T17	0	325	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	202254	0	0
GntImpliesValid_A	422065402	202254	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	202254	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3045939	0	0
ReadyAndValidImplyGrant_A	422065402	202254	0	0
ReqAndReadyImplyGrant_A	422065402	202254	0	0
ReqImpliesValid_A	422065402	513160	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	202254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	202254	0	0
T2	229442	155	0	0
T3	407043	458	0	0
T7	233870	177	0	0
T8	872427	997	0	0
T9	138042	129	0	0
T10	193752	110	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	18	0	0
T14	29474	590	0	0
T15	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	202254	0	0
T2	229442	155	0	0
T3	407043	458	0	0
T7	233870	177	0	0
T8	872427	997	0	0
T9	138042	129	0	0
T10	193752	110	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	18	0	0
T14	29474	590	0	0
T15	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	202254	0	0
T2	229442	155	0	0
T3	407043	458	0	0
T7	233870	177	0	0
T8	872427	997	0	0
T9	138042	129	0	0
T10	193752	110	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	18	0	0
T14	29474	590	0	0
T15	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3045939	0	0
T1	291226	1	0	0
T2	229442	48329	0	0
T3	407043	1417	0	0
T7	233870	51983	0	0
T8	872427	3695	0	0
T9	138042	584	0	0
T10	193752	35635	0	0
T11	434492	1	0	0
T12	42084	584	0	0
T13	402999	5293	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	202254	0	0
T2	229442	155	0	0
T3	407043	458	0	0
T7	233870	177	0	0
T8	872427	997	0	0
T9	138042	129	0	0
T10	193752	110	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	18	0	0
T14	29474	590	0	0
T15	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	202254	0	0
T2	229442	155	0	0
T3	407043	458	0	0
T7	233870	177	0	0
T8	872427	997	0	0
T9	138042	129	0	0
T10	193752	110	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	18	0	0
T14	29474	590	0	0
T15	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	513160	0	0
T2	229442	2235	0	0
T3	407043	1112	0	0
T7	233870	5130	0	0
T8	872427	1980	0	0
T9	138042	146	0	0
T10	193752	2647	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	526	0	0
T14	29474	1163	0	0
T15	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	202254	0	0
T2	229442	155	0	0
T3	407043	458	0	0
T7	233870	177	0	0
T8	872427	997	0	0
T9	138042	129	0	0
T10	193752	110	0	0
T11	434492	0	0	0
T12	42084	77	0	0
T13	402999	18	0	0
T14	29474	590	0	0
T15	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	215272	0	0
GntImpliesValid_A	422065402	215272	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	215272	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3107066	0	0
ReadyAndValidImplyGrant_A	422065402	215272	0	0
ReqAndReadyImplyGrant_A	422065402	215272	0	0
ReqImpliesValid_A	422065402	553814	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	215272	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215272	0	0
T1	291226	519	0	0
T2	229442	157	0	0
T3	407043	402	0	0
T7	233870	168	0	0
T8	872427	0	0	0
T9	138042	137	0	0
T10	193752	118	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215272	0	0
T1	291226	519	0	0
T2	229442	157	0	0
T3	407043	402	0	0
T7	233870	168	0	0
T8	872427	0	0	0
T9	138042	137	0	0
T10	193752	118	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215272	0	0
T1	291226	519	0	0
T2	229442	157	0	0
T3	407043	402	0	0
T7	233870	168	0	0
T8	872427	0	0	0
T9	138042	137	0	0
T10	193752	118	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3107066	0	0
T1	291226	1810	0	0
T2	229442	51163	0	0
T3	407043	1170	0	0
T7	233870	54122	0	0
T8	872427	1	0	0
T9	138042	592	0	0
T10	193752	37237	0	0
T11	434492	1	0	0
T12	42084	678	0	0
T13	402999	1017	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215272	0	0
T1	291226	519	0	0
T2	229442	157	0	0
T3	407043	402	0	0
T7	233870	168	0	0
T8	872427	0	0	0
T9	138042	137	0	0
T10	193752	118	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215272	0	0
T1	291226	519	0	0
T2	229442	157	0	0
T3	407043	402	0	0
T7	233870	168	0	0
T8	872427	0	0	0
T9	138042	137	0	0
T10	193752	118	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	553814	0	0
T1	291226	1134	0	0
T2	229442	1628	0	0
T3	407043	1095	0	0
T7	233870	4323	0	0
T8	872427	0	0	0
T9	138042	149	0	0
T10	193752	1207	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	215272	0	0
T1	291226	519	0	0
T2	229442	157	0	0
T3	407043	402	0	0
T7	233870	168	0	0
T8	872427	0	0	0
T9	138042	137	0	0
T10	193752	118	0	0
T11	434492	0	0	0
T12	42084	83	0	0
T13	402999	4	0	0
T14	0	11	0	0
T15	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	210526	0	0
GntImpliesValid_A	422065402	210526	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	210526	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3051296	0	0
ReadyAndValidImplyGrant_A	422065402	210526	0	0
ReqAndReadyImplyGrant_A	422065402	210526	0	0
ReqImpliesValid_A	422065402	577481	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	210526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210526	0	0
T2	229442	166	0	0
T3	407043	0	0	0
T7	233870	176	0	0
T8	872427	0	0	0
T9	138042	92	0	0
T10	193752	112	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	17	0	0
T16	0	100	0	0
T17	0	303	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210526	0	0
T2	229442	166	0	0
T3	407043	0	0	0
T7	233870	176	0	0
T8	872427	0	0	0
T9	138042	92	0	0
T10	193752	112	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	17	0	0
T16	0	100	0	0
T17	0	303	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210526	0	0
T2	229442	166	0	0
T3	407043	0	0	0
T7	233870	176	0	0
T8	872427	0	0	0
T9	138042	92	0	0
T10	193752	112	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	17	0	0
T16	0	100	0	0
T17	0	303	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3051296	0	0
T1	291226	1	0	0
T2	229442	57609	0	0
T3	407043	1	0	0
T7	233870	51505	0	0
T8	872427	1	0	0
T9	138042	399	0	0
T10	193752	35635	0	0
T11	434492	1	0	0
T12	42084	535	0	0
T13	402999	3638	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210526	0	0
T2	229442	166	0	0
T3	407043	0	0	0
T7	233870	176	0	0
T8	872427	0	0	0
T9	138042	92	0	0
T10	193752	112	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	17	0	0
T16	0	100	0	0
T17	0	303	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210526	0	0
T2	229442	166	0	0
T3	407043	0	0	0
T7	233870	176	0	0
T8	872427	0	0	0
T9	138042	92	0	0
T10	193752	112	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	17	0	0
T16	0	100	0	0
T17	0	303	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	577481	0	0
T2	229442	2283	0	0
T3	407043	0	0	0
T7	233870	4286	0	0
T8	872427	0	0	0
T9	138042	104	0	0
T10	193752	4619	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	20	0	0
T16	0	135	0	0
T17	0	309	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210526	0	0
T2	229442	166	0	0
T3	407043	0	0	0
T7	233870	176	0	0
T8	872427	0	0	0
T9	138042	92	0	0
T10	193752	112	0	0
T11	434492	0	0	0
T12	42084	64	0	0
T13	402999	14	0	0
T14	29474	14	0	0
T15	0	17	0	0
T16	0	100	0	0
T17	0	303	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T2,T8,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T8,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T7
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	224179	0	0
GntImpliesValid_A	422065402	224179	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	224179	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3184378	0	0
ReadyAndValidImplyGrant_A	422065402	224179	0	0
ReqAndReadyImplyGrant_A	422065402	224179	0	0
ReqImpliesValid_A	422065402	603142	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	224179	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	224179	0	0
T2	229442	131	0	0
T3	407043	0	0	0
T7	233870	160	0	0
T8	872427	439	0	0
T9	138042	129	0	0
T10	193752	99	0	0
T11	434492	419	0	0
T12	42084	82	0	0
T13	402999	15	0	0
T14	29474	582	0	0
T15	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	224179	0	0
T2	229442	131	0	0
T3	407043	0	0	0
T7	233870	160	0	0
T8	872427	439	0	0
T9	138042	129	0	0
T10	193752	99	0	0
T11	434492	419	0	0
T12	42084	82	0	0
T13	402999	15	0	0
T14	29474	582	0	0
T15	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	224179	0	0
T2	229442	131	0	0
T3	407043	0	0	0
T7	233870	160	0	0
T8	872427	439	0	0
T9	138042	129	0	0
T10	193752	99	0	0
T11	434492	419	0	0
T12	42084	82	0	0
T13	402999	15	0	0
T14	29474	582	0	0
T15	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3184378	0	0
T1	291226	1	0	0
T2	229442	41549	0	0
T3	407043	1	0	0
T7	233870	56105	0	0
T8	872427	1356	0	0
T9	138042	559	0	0
T10	193752	32531	0	0
T11	434492	1231	0	0
T12	42084	540	0	0
T13	402999	5846	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	224179	0	0
T2	229442	131	0	0
T3	407043	0	0	0
T7	233870	160	0	0
T8	872427	439	0	0
T9	138042	129	0	0
T10	193752	99	0	0
T11	434492	419	0	0
T12	42084	82	0	0
T13	402999	15	0	0
T14	29474	582	0	0
T15	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	224179	0	0
T2	229442	131	0	0
T3	407043	0	0	0
T7	233870	160	0	0
T8	872427	439	0	0
T9	138042	129	0	0
T10	193752	99	0	0
T11	434492	419	0	0
T12	42084	82	0	0
T13	402999	15	0	0
T14	29474	582	0	0
T15	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	603142	0	0
T2	229442	2234	0	0
T3	407043	0	0	0
T7	233870	3592	0	0
T8	872427	1117	0	0
T9	138042	155	0	0
T10	193752	2197	0	0
T11	434492	1083	0	0
T12	42084	99	0	0
T13	402999	15	0	0
T14	29474	1155	0	0
T15	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	224179	0	0
T2	229442	131	0	0
T3	407043	0	0	0
T7	233870	160	0	0
T8	872427	439	0	0
T9	138042	129	0	0
T10	193752	99	0	0
T11	434492	419	0	0
T12	42084	82	0	0
T13	402999	15	0	0
T14	29474	582	0	0
T15	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T2,T8,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T8,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T7
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	201481	0	0
GntImpliesValid_A	422065402	201481	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	201481	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3003416	0	0
ReadyAndValidImplyGrant_A	422065402	201481	0	0
ReqAndReadyImplyGrant_A	422065402	201481	0	0
ReqImpliesValid_A	422065402	548999	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	201481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201481	0	0
T2	229442	139	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	463	0	0
T9	138042	148	0	0
T10	193752	91	0	0
T11	434492	436	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201481	0	0
T2	229442	139	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	463	0	0
T9	138042	148	0	0
T10	193752	91	0	0
T11	434492	436	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201481	0	0
T2	229442	139	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	463	0	0
T9	138042	148	0	0
T10	193752	91	0	0
T11	434492	436	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3003416	0	0
T1	291226	1	0	0
T2	229442	44957	0	0
T3	407043	1	0	0
T7	233870	58162	0	0
T8	872427	1548	0	0
T9	138042	623	0	0
T10	193752	26737	0	0
T11	434492	1347	0	0
T12	42084	622	0	0
T13	402999	5343	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201481	0	0
T2	229442	139	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	463	0	0
T9	138042	148	0	0
T10	193752	91	0	0
T11	434492	436	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201481	0	0
T2	229442	139	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	463	0	0
T9	138042	148	0	0
T10	193752	91	0	0
T11	434492	436	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	548999	0	0
T2	229442	3836	0	0
T3	407043	0	0	0
T7	233870	3602	0	0
T8	872427	1090	0	0
T9	138042	205	0	0
T10	193752	1392	0	0
T11	434492	1156	0	0
T12	42084	98	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	201481	0	0
T2	229442	139	0	0
T3	407043	0	0	0
T7	233870	167	0	0
T8	872427	463	0	0
T9	138042	148	0	0
T10	193752	91	0	0
T11	434492	436	0	0
T12	42084	82	0	0
T13	402999	17	0	0
T14	29474	11	0	0
T15	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	210125	0	0
GntImpliesValid_A	422065402	210125	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	210125	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3001991	0	0
ReadyAndValidImplyGrant_A	422065402	210125	0	0
ReqAndReadyImplyGrant_A	422065402	210125	0	0
ReqImpliesValid_A	422065402	544956	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	210125	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210125	0	0
T2	229442	140	0	0
T3	407043	502	0	0
T7	233870	166	0	0
T8	872427	571	0	0
T9	138042	128	0	0
T10	193752	97	0	0
T11	434492	555	0	0
T12	42084	80	0	0
T13	402999	15	0	0
T14	29474	584	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210125	0	0
T2	229442	140	0	0
T3	407043	502	0	0
T7	233870	166	0	0
T8	872427	571	0	0
T9	138042	128	0	0
T10	193752	97	0	0
T11	434492	555	0	0
T12	42084	80	0	0
T13	402999	15	0	0
T14	29474	584	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210125	0	0
T2	229442	140	0	0
T3	407043	502	0	0
T7	233870	166	0	0
T8	872427	571	0	0
T9	138042	128	0	0
T10	193752	97	0	0
T11	434492	555	0	0
T12	42084	80	0	0
T13	402999	15	0	0
T14	29474	584	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3001991	0	0
T1	291226	1	0	0
T2	229442	46810	0	0
T3	407043	1636	0	0
T7	233870	55200	0	0
T8	872427	1912	0	0
T9	138042	555	0	0
T10	193752	26828	0	0
T11	434492	1933	0	0
T12	42084	602	0	0
T13	402999	4875	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210125	0	0
T2	229442	140	0	0
T3	407043	502	0	0
T7	233870	166	0	0
T8	872427	571	0	0
T9	138042	128	0	0
T10	193752	97	0	0
T11	434492	555	0	0
T12	42084	80	0	0
T13	402999	15	0	0
T14	29474	584	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210125	0	0
T2	229442	140	0	0
T3	407043	502	0	0
T7	233870	166	0	0
T8	872427	571	0	0
T9	138042	128	0	0
T10	193752	97	0	0
T11	434492	555	0	0
T12	42084	80	0	0
T13	402999	15	0	0
T14	29474	584	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	544956	0	0
T2	229442	2451	0	0
T3	407043	1275	0	0
T7	233870	2849	0	0
T8	872427	1249	0	0
T9	138042	166	0	0
T10	193752	672	0	0
T11	434492	1274	0	0
T12	42084	80	0	0
T13	402999	88	0	0
T14	29474	1147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	210125	0	0
T2	229442	140	0	0
T3	407043	502	0	0
T7	233870	166	0	0
T8	872427	571	0	0
T9	138042	128	0	0
T10	193752	97	0	0
T11	434492	555	0	0
T12	42084	80	0	0
T13	402999	15	0	0
T14	29474	584	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	219192	0	0
GntImpliesValid_A	422065402	219192	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	219192	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3086436	0	0
ReadyAndValidImplyGrant_A	422065402	219192	0	0
ReqAndReadyImplyGrant_A	422065402	219192	0	0
ReqImpliesValid_A	422065402	635790	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	219192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	219192	0	0
T2	229442	148	0	0
T3	407043	545	0	0
T7	233870	180	0	0
T8	872427	466	0	0
T9	138042	132	0	0
T10	193752	107	0	0
T11	434492	428	0	0
T12	42084	78	0	0
T13	402999	10	0	0
T14	29474	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	219192	0	0
T2	229442	148	0	0
T3	407043	545	0	0
T7	233870	180	0	0
T8	872427	466	0	0
T9	138042	132	0	0
T10	193752	107	0	0
T11	434492	428	0	0
T12	42084	78	0	0
T13	402999	10	0	0
T14	29474	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	219192	0	0
T2	229442	148	0	0
T3	407043	545	0	0
T7	233870	180	0	0
T8	872427	466	0	0
T9	138042	132	0	0
T10	193752	107	0	0
T11	434492	428	0	0
T12	42084	78	0	0
T13	402999	10	0	0
T14	29474	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3086436	0	0
T1	291226	1	0	0
T2	229442	46573	0	0
T3	407043	1845	0	0
T7	233870	60603	0	0
T8	872427	1547	0	0
T9	138042	590	0	0
T10	193752	34165	0	0
T11	434492	1349	0	0
T12	42084	558	0	0
T13	402999	3128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	219192	0	0
T2	229442	148	0	0
T3	407043	545	0	0
T7	233870	180	0	0
T8	872427	466	0	0
T9	138042	132	0	0
T10	193752	107	0	0
T11	434492	428	0	0
T12	42084	78	0	0
T13	402999	10	0	0
T14	29474	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	219192	0	0
T2	229442	148	0	0
T3	407043	545	0	0
T7	233870	180	0	0
T8	872427	466	0	0
T9	138042	132	0	0
T10	193752	107	0	0
T11	434492	428	0	0
T12	42084	78	0	0
T13	402999	10	0	0
T14	29474	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	635790	0	0
T2	229442	4583	0	0
T3	407043	1302	0	0
T7	233870	3964	0	0
T8	872427	1176	0	0
T9	138042	155	0	0
T10	193752	3572	0	0
T11	434492	1035	0	0
T12	42084	99	0	0
T13	402999	10	0	0
T14	29474	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	219192	0	0
T2	229442	148	0	0
T3	407043	545	0	0
T7	233870	180	0	0
T8	872427	466	0	0
T9	138042	132	0	0
T10	193752	107	0	0
T11	434492	428	0	0
T12	42084	78	0	0
T13	402999	10	0	0
T14	29474	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T7
1	0	Covered	T2,T8,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T2,T8,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T7
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	206119	0	0
GntImpliesValid_A	422065402	206119	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	206119	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3061572	0	0
ReadyAndValidImplyGrant_A	422065402	206119	0	0
ReqAndReadyImplyGrant_A	422065402	206119	0	0
ReqImpliesValid_A	422065402	568425	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	206119	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	206119	0	0
T2	229442	156	0	0
T3	407043	0	0	0
T7	233870	164	0	0
T8	872427	567	0	0
T9	138042	122	0	0
T10	193752	108	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	10	0	0
T14	29474	1495	0	0
T15	0	14	0	0
T16	0	97	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	206119	0	0
T2	229442	156	0	0
T3	407043	0	0	0
T7	233870	164	0	0
T8	872427	567	0	0
T9	138042	122	0	0
T10	193752	108	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	10	0	0
T14	29474	1495	0	0
T15	0	14	0	0
T16	0	97	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	206119	0	0
T2	229442	156	0	0
T3	407043	0	0	0
T7	233870	164	0	0
T8	872427	567	0	0
T9	138042	122	0	0
T10	193752	108	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	10	0	0
T14	29474	1495	0	0
T15	0	14	0	0
T16	0	97	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3061572	0	0
T1	291226	1	0	0
T2	229442	49493	0	0
T3	407043	1	0	0
T7	233870	53660	0	0
T8	872427	2031	0	0
T9	138042	549	0	0
T10	193752	37711	0	0
T11	434492	1	0	0
T12	42084	572	0	0
T13	402999	4885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	206119	0	0
T2	229442	156	0	0
T3	407043	0	0	0
T7	233870	164	0	0
T8	872427	567	0	0
T9	138042	122	0	0
T10	193752	108	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	10	0	0
T14	29474	1495	0	0
T15	0	14	0	0
T16	0	97	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	206119	0	0
T2	229442	156	0	0
T3	407043	0	0	0
T7	233870	164	0	0
T8	872427	567	0	0
T9	138042	122	0	0
T10	193752	108	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	10	0	0
T14	29474	1495	0	0
T15	0	14	0	0
T16	0	97	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	568425	0	0
T2	229442	1763	0	0
T3	407043	0	0	0
T7	233870	3111	0	0
T8	872427	1232	0	0
T9	138042	147	0	0
T10	193752	2388	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	534	0	0
T14	29474	2970	0	0
T15	0	18	0	0
T16	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	206119	0	0
T2	229442	156	0	0
T3	407043	0	0	0
T7	233870	164	0	0
T8	872427	567	0	0
T9	138042	122	0	0
T10	193752	108	0	0
T11	434492	0	0	0
T12	42084	80	0	0
T13	402999	10	0	0
T14	29474	1495	0	0
T15	0	14	0	0
T16	0	97	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	213204	0	0
GntImpliesValid_A	422065402	213204	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	213204	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	3104236	0	0
ReadyAndValidImplyGrant_A	422065402	213204	0	0
ReqAndReadyImplyGrant_A	422065402	213204	0	0
ReqImpliesValid_A	422065402	591779	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	0	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	213204	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	213204	0	0
T2	229442	151	0	0
T3	407043	509	0	0
T7	233870	163	0	0
T8	872427	907	0	0
T9	138042	137	0	0
T10	193752	113	0	0
T11	434492	565	0	0
T12	42084	85	0	0
T13	402999	18	0	0
T14	29474	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	213204	0	0
T2	229442	151	0	0
T3	407043	509	0	0
T7	233870	163	0	0
T8	872427	907	0	0
T9	138042	137	0	0
T10	193752	113	0	0
T11	434492	565	0	0
T12	42084	85	0	0
T13	402999	18	0	0
T14	29474	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	213204	0	0
T2	229442	151	0	0
T3	407043	509	0	0
T7	233870	163	0	0
T8	872427	907	0	0
T9	138042	137	0	0
T10	193752	113	0	0
T11	434492	565	0	0
T12	42084	85	0	0
T13	402999	18	0	0
T14	29474	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	3104236	0	0
T1	291226	1	0	0
T2	229442	47262	0	0
T3	407043	1650	0	0
T7	233870	53793	0	0
T8	872427	3004	0	0
T9	138042	590	0	0
T10	193752	36425	0	0
T11	434492	2030	0	0
T12	42084	587	0	0
T13	402999	6848	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	213204	0	0
T2	229442	151	0	0
T3	407043	509	0	0
T7	233870	163	0	0
T8	872427	907	0	0
T9	138042	137	0	0
T10	193752	113	0	0
T11	434492	565	0	0
T12	42084	85	0	0
T13	402999	18	0	0
T14	29474	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	213204	0	0
T2	229442	151	0	0
T3	407043	509	0	0
T7	233870	163	0	0
T8	872427	907	0	0
T9	138042	137	0	0
T10	193752	113	0	0
T11	434492	565	0	0
T12	42084	85	0	0
T13	402999	18	0	0
T14	29474	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	591779	0	0
T2	229442	3394	0	0
T3	407043	1225	0	0
T7	233870	3234	0	0
T8	872427	2271	0	0
T9	138042	155	0	0
T10	193752	2797	0	0
T11	434492	1192	0	0
T12	42084	86	0	0
T13	402999	116	0	0
T14	29474	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	213204	0	0
T2	229442	151	0	0
T3	407043	509	0	0
T7	233870	163	0	0
T8	872427	907	0	0
T9	138042	137	0	0
T10	193752	113	0	0
T11	434492	565	0	0
T12	42084	85	0	0
T13	402999	18	0	0
T14	29474	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	840399	0	0
GntImpliesValid_A	422065402	840399	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	840399	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	11619317	0	0
ReadyAndValidImplyGrant_A	422065402	840399	0	0
ReqAndReadyImplyGrant_A	422065402	840399	0	0
ReqImpliesValid_A	422065402	2210119	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	15801	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	840399	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	840399	0	0
T1	291226	46	0	0
T2	229442	689	0	0
T3	407043	729	0	0
T7	233870	652	0	0
T8	872427	917	0	0
T9	138042	527	0	0
T10	193752	447	0	0
T11	434492	682	0	0
T12	42084	332	0	0
T13	402999	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	840399	0	0
T1	291226	46	0	0
T2	229442	689	0	0
T3	407043	729	0	0
T7	233870	652	0	0
T8	872427	917	0	0
T9	138042	527	0	0
T10	193752	447	0	0
T11	434492	682	0	0
T12	42084	332	0	0
T13	402999	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	840399	0	0
T1	291226	46	0	0
T2	229442	689	0	0
T3	407043	729	0	0
T7	233870	652	0	0
T8	872427	917	0	0
T9	138042	527	0	0
T10	193752	447	0	0
T11	434492	682	0	0
T12	42084	332	0	0
T13	402999	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	11619317	0	0
T1	291226	158	0	0
T2	229442	225002	0	0
T3	407043	2338	0	0
T7	233870	188568	0	0
T8	872427	3017	0	0
T9	138042	1755	0	0
T10	193752	133524	0	0
T11	434492	2217	0	0
T12	42084	2094	0	0
T13	402999	12711	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	840399	0	0
T1	291226	46	0	0
T2	229442	689	0	0
T3	407043	729	0	0
T7	233870	652	0	0
T8	872427	917	0	0
T9	138042	527	0	0
T10	193752	447	0	0
T11	434492	682	0	0
T12	42084	332	0	0
T13	402999	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	840399	0	0
T1	291226	46	0	0
T2	229442	689	0	0
T3	407043	729	0	0
T7	233870	652	0	0
T8	872427	917	0	0
T9	138042	527	0	0
T10	193752	447	0	0
T11	434492	682	0	0
T12	42084	332	0	0
T13	402999	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	2210119	0	0
T1	291226	48	0	0
T2	229442	25745	0	0
T3	407043	951	0	0
T7	233870	19986	0	0
T8	872427	1230	0	0
T9	138042	681	0	0
T10	193752	12867	0	0
T11	434492	903	0	0
T12	42084	439	0	0
T13	402999	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	15801	0	900
T14	29474	1	0	1
T15	11344	0	0	1
T16	47128	0	0	1
T17	31180	17	0	1
T18	89258	0	0	1
T19	8477	7	0	1
T20	65407	133	0	1
T21	0	1	0	0
T22	0	1	0	0
T23	0	10	0	0
T24	0	1	0	0
T25	0	44	0	0
T26	0	18	0	0
T27	46722	0	0	1
T28	29386	0	0	1
T29	8418	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	840399	0	0
T1	291226	46	0	0
T2	229442	689	0	0
T3	407043	729	0	0
T7	233870	652	0	0
T8	872427	917	0	0
T9	138042	527	0	0
T10	193752	447	0	0
T11	434492	682	0	0
T12	42084	332	0	0
T13	402999	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422065402	421956327	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422065402	850584	0	0
GntImpliesValid_A	422065402	850584	0	0
GrantKnown_A	422065402	421956327	0	0
IdxKnown_A	422065402	421956327	0	0
IndexIsCorrect_A	422065402	850584	0	0
LockArbDecision_A	422065402	0	0	0
NoReadyValidNoGrant_A	422065402	354450607	0	0
ReadyAndValidImplyGrant_A	422065402	850584	0	0
ReqAndReadyImplyGrant_A	422065402	850584	0	0
ReqImpliesValid_A	422065402	13534766	0	0
ReqStaysHighUntilGranted0_M	422065402	0	0	0
RoundRobin_A	422065402	29104	0	900
ValidKnown_A	422065402	421956327	0	0
gen_data_port_assertion.DataFlow_A	422065402	850584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	850584	0	0
T1	291226	58	0	0
T2	229442	577	0	0
T3	407043	1515	0	0
T7	233870	633	0	0
T8	872427	911	0	0
T9	138042	566	0	0
T10	193752	463	0	0
T11	434492	1365	0	0
T12	42084	280	0	0
T13	402999	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	850584	0	0
T1	291226	58	0	0
T2	229442	577	0	0
T3	407043	1515	0	0
T7	233870	633	0	0
T8	872427	911	0	0
T9	138042	566	0	0
T10	193752	463	0	0
T11	434492	1365	0	0
T12	42084	280	0	0
T13	402999	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	850584	0	0
T1	291226	58	0	0
T2	229442	577	0	0
T3	407043	1515	0	0
T7	233870	633	0	0
T8	872427	911	0	0
T9	138042	566	0	0
T10	193752	463	0	0
T11	434492	1365	0	0
T12	42084	280	0	0
T13	402999	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	354450607	0	0
T1	291226	242641	0	0
T2	229442	201524	0	0
T3	407043	338502	0	0
T7	233870	210638	0	0
T8	872427	726522	0	0
T9	138042	114830	0	0
T10	193752	170726	0	0
T11	434492	361374	0	0
T12	42084	35669	0	0
T13	402999	385070	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	850584	0	0
T1	291226	58	0	0
T2	229442	577	0	0
T3	407043	1515	0	0
T7	233870	633	0	0
T8	872427	911	0	0
T9	138042	566	0	0
T10	193752	463	0	0
T11	434492	1365	0	0
T12	42084	280	0	0
T13	402999	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	850584	0	0
T1	291226	58	0	0
T2	229442	577	0	0
T3	407043	1515	0	0
T7	233870	633	0	0
T8	872427	911	0	0
T9	138042	566	0	0
T10	193752	463	0	0
T11	434492	1365	0	0
T12	42084	280	0	0
T13	402999	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	13534766	0	0
T1	291226	247	0	0
T2	229442	176158	0	0
T3	407043	6744	0	0
T7	233870	228264	0	0
T8	872427	3979	0	0
T9	138042	2608	0	0
T10	193752	155024	0	0
T11	434492	6154	0	0
T12	42084	1955	0	0
T13	402999	11605	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	29104	0	900
T2	229442	1	0	1
T3	407043	15	0	1
T7	233870	0	0	1
T8	872427	0	0	1
T9	138042	0	0	1
T10	193752	0	0	1
T11	434492	9	0	1
T12	42084	0	0	1
T13	402999	0	0	1
T14	29474	532	0	1
T17	0	21	0	0
T18	0	12	0	0
T19	0	4	0	0
T20	0	26	0	0
T22	0	1	0	0
T23	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	421956327	0	0
T1	291226	291191	0	0
T2	229442	229435	0	0
T3	407043	407039	0	0
T7	233870	233868	0	0
T8	872427	872422	0	0
T9	138042	138039	0	0
T10	193752	193746	0	0
T11	434492	434489	0	0
T12	42084	42044	0	0
T13	402999	402991	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422065402	850584	0	0
T1	291226	58	0	0
T2	229442	577	0	0
T3	407043	1515	0	0
T7	233870	633	0	0
T8	872427	911	0	0
T9	138042	566	0	0
T10	193752	463	0	0
T11	434492	1365	0	0
T12	42084	280	0	0
T13	402999	40	0	0