Line Coverage for Module :
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Line Coverage for Module :
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Module :
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T10,T11 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T10,T11 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
tlul_socket_m1
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
23584970 |
0 |
0 |
T1 |
8842104 |
10481 |
0 |
0 |
T2 |
385704 |
17507 |
0 |
0 |
T3 |
1528008 |
4470 |
0 |
0 |
T4 |
0 |
2232 |
0 |
0 |
T7 |
2881632 |
8266 |
0 |
0 |
T8 |
43656 |
278 |
0 |
0 |
T9 |
1564992 |
6257 |
0 |
0 |
T10 |
43992 |
247 |
0 |
0 |
T11 |
832512 |
16801 |
0 |
0 |
T12 |
324672 |
6194 |
0 |
0 |
T13 |
1425960 |
5968 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13443268 |
0 |
0 |
T1 |
8842104 |
4219 |
0 |
0 |
T2 |
385704 |
12900 |
0 |
0 |
T3 |
1528008 |
1627 |
0 |
0 |
T4 |
0 |
2302 |
0 |
0 |
T7 |
2881632 |
3035 |
0 |
0 |
T8 |
43656 |
136 |
0 |
0 |
T9 |
1564992 |
2957 |
0 |
0 |
T10 |
43992 |
106 |
0 |
0 |
T11 |
832512 |
8860 |
0 |
0 |
T12 |
324672 |
3143 |
0 |
0 |
T13 |
1425960 |
2487 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1697368432 |
3928886 |
0 |
0 |
T1 |
1473684 |
1626 |
0 |
0 |
T2 |
64284 |
1307 |
0 |
0 |
T3 |
254668 |
678 |
0 |
0 |
T4 |
0 |
312 |
0 |
0 |
T7 |
480272 |
1116 |
0 |
0 |
T8 |
7276 |
15 |
0 |
0 |
T9 |
260832 |
919 |
0 |
0 |
T10 |
7332 |
20 |
0 |
0 |
T11 |
138752 |
1086 |
0 |
0 |
T12 |
54112 |
469 |
0 |
0 |
T13 |
237660 |
908 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21600 |
21600 |
0 |
0 |
T1 |
24 |
24 |
0 |
0 |
T2 |
24 |
24 |
0 |
0 |
T3 |
24 |
24 |
0 |
0 |
T7 |
24 |
24 |
0 |
0 |
T8 |
24 |
24 |
0 |
0 |
T9 |
24 |
24 |
0 |
0 |
T10 |
24 |
24 |
0 |
0 |
T11 |
24 |
24 |
0 |
0 |
T12 |
24 |
24 |
0 |
0 |
T13 |
24 |
24 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
160743130 |
0 |
0 |
T1 |
8842104 |
83650 |
0 |
0 |
T2 |
385704 |
6919 |
0 |
0 |
T3 |
1528008 |
20179 |
0 |
0 |
T4 |
0 |
2765 |
0 |
0 |
T7 |
2881632 |
37631 |
0 |
0 |
T8 |
43656 |
379 |
0 |
0 |
T9 |
1564992 |
15983 |
0 |
0 |
T10 |
43992 |
346 |
0 |
0 |
T11 |
832512 |
18707 |
0 |
0 |
T12 |
324672 |
8425 |
0 |
0 |
T13 |
1425960 |
16570 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_28
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_28
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_28
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
1660625 |
0 |
0 |
T1 |
368421 |
706 |
0 |
0 |
T2 |
16071 |
518 |
0 |
0 |
T3 |
63667 |
303 |
0 |
0 |
T7 |
120068 |
660 |
0 |
0 |
T8 |
1819 |
43 |
0 |
0 |
T9 |
65208 |
499 |
0 |
0 |
T10 |
1833 |
24 |
0 |
0 |
T11 |
34688 |
1719 |
0 |
0 |
T12 |
13528 |
748 |
0 |
0 |
T13 |
59415 |
494 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
397409 |
0 |
0 |
T1 |
368421 |
6 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
95 |
0 |
0 |
T4 |
0 |
104 |
0 |
0 |
T7 |
120068 |
126 |
0 |
0 |
T8 |
1819 |
7 |
0 |
0 |
T9 |
65208 |
106 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
161 |
0 |
0 |
T12 |
13528 |
122 |
0 |
0 |
T13 |
59415 |
98 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
507892 |
0 |
0 |
T1 |
368421 |
2 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
50 |
0 |
0 |
T4 |
0 |
111 |
0 |
0 |
T7 |
120068 |
141 |
0 |
0 |
T8 |
1819 |
1 |
0 |
0 |
T9 |
65208 |
130 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
147 |
0 |
0 |
T12 |
13528 |
111 |
0 |
0 |
T13 |
59415 |
164 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
18156476 |
0 |
0 |
T1 |
368421 |
11205 |
0 |
0 |
T2 |
16071 |
518 |
0 |
0 |
T3 |
63667 |
2557 |
0 |
0 |
T7 |
120068 |
4944 |
0 |
0 |
T8 |
1819 |
51 |
0 |
0 |
T9 |
65208 |
2854 |
0 |
0 |
T10 |
1833 |
35 |
0 |
0 |
T11 |
34688 |
2001 |
0 |
0 |
T12 |
13528 |
969 |
0 |
0 |
T13 |
59415 |
1400 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_29
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_29
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_29
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
1883850 |
0 |
0 |
T1 |
368421 |
236 |
0 |
0 |
T2 |
16071 |
668 |
0 |
0 |
T3 |
63667 |
347 |
0 |
0 |
T7 |
120068 |
624 |
0 |
0 |
T8 |
1819 |
54 |
0 |
0 |
T9 |
65208 |
605 |
0 |
0 |
T10 |
1833 |
42 |
0 |
0 |
T11 |
34688 |
1952 |
0 |
0 |
T12 |
13528 |
998 |
0 |
0 |
T13 |
59415 |
528 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
524438 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
51 |
0 |
0 |
T4 |
0 |
124 |
0 |
0 |
T7 |
120068 |
126 |
0 |
0 |
T8 |
1819 |
8 |
0 |
0 |
T9 |
65208 |
117 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
205 |
0 |
0 |
T12 |
13528 |
133 |
0 |
0 |
T13 |
59415 |
84 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
633876 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
73 |
0 |
0 |
T4 |
0 |
99 |
0 |
0 |
T7 |
120068 |
121 |
0 |
0 |
T8 |
1819 |
1 |
0 |
0 |
T9 |
65208 |
110 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
171 |
0 |
0 |
T12 |
13528 |
125 |
0 |
0 |
T13 |
59415 |
84 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
19648885 |
0 |
0 |
T1 |
368421 |
15290 |
0 |
0 |
T2 |
16071 |
524 |
0 |
0 |
T3 |
63667 |
2956 |
0 |
0 |
T7 |
120068 |
5101 |
0 |
0 |
T8 |
1819 |
48 |
0 |
0 |
T9 |
65208 |
2994 |
0 |
0 |
T10 |
1833 |
44 |
0 |
0 |
T11 |
34688 |
1945 |
0 |
0 |
T12 |
13528 |
966 |
0 |
0 |
T13 |
59415 |
1203 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_31
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_31
| Total | Covered | Percent |
Conditions | 33 | 29 | 87.88 |
Logical | 33 | 29 | 87.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_31
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
2011870 |
0 |
0 |
T1 |
368421 |
679 |
0 |
0 |
T2 |
16071 |
2272 |
0 |
0 |
T3 |
63667 |
324 |
0 |
0 |
T7 |
120068 |
630 |
0 |
0 |
T8 |
1819 |
33 |
0 |
0 |
T9 |
65208 |
541 |
0 |
0 |
T10 |
1833 |
45 |
0 |
0 |
T11 |
34688 |
2596 |
0 |
0 |
T12 |
13528 |
965 |
0 |
0 |
T13 |
59415 |
540 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
605320 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
1585 |
0 |
0 |
T3 |
63667 |
69 |
0 |
0 |
T7 |
120068 |
118 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
98 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
608 |
0 |
0 |
T12 |
13528 |
121 |
0 |
0 |
T13 |
59415 |
97 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
774344 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
1307 |
0 |
0 |
T3 |
63667 |
85 |
0 |
0 |
T7 |
120068 |
103 |
0 |
0 |
T8 |
1819 |
9 |
0 |
0 |
T9 |
65208 |
92 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
617 |
0 |
0 |
T12 |
13528 |
126 |
0 |
0 |
T13 |
59415 |
140 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
17998220 |
0 |
0 |
T1 |
368421 |
11341 |
0 |
0 |
T2 |
16071 |
1316 |
0 |
0 |
T3 |
63667 |
2879 |
0 |
0 |
T7 |
120068 |
5489 |
0 |
0 |
T8 |
1819 |
42 |
0 |
0 |
T9 |
65208 |
2900 |
0 |
0 |
T10 |
1833 |
37 |
0 |
0 |
T11 |
34688 |
2745 |
0 |
0 |
T12 |
13528 |
933 |
0 |
0 |
T13 |
59415 |
1443 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_33
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_33
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_33
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
309653 |
0 |
0 |
T1 |
368421 |
6 |
0 |
0 |
T2 |
16071 |
1001 |
0 |
0 |
T3 |
63667 |
56 |
0 |
0 |
T7 |
120068 |
108 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
92 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
123 |
0 |
0 |
T12 |
13528 |
137 |
0 |
0 |
T13 |
59415 |
68 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
408401 |
0 |
0 |
T1 |
368421 |
7 |
0 |
0 |
T2 |
16071 |
632 |
0 |
0 |
T3 |
63667 |
46 |
0 |
0 |
T7 |
120068 |
88 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
72 |
0 |
0 |
T10 |
1833 |
2 |
0 |
0 |
T11 |
34688 |
150 |
0 |
0 |
T12 |
13528 |
129 |
0 |
0 |
T13 |
59415 |
126 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4816063 |
0 |
0 |
T1 |
368421 |
1621 |
0 |
0 |
T2 |
16071 |
501 |
0 |
0 |
T3 |
63667 |
520 |
0 |
0 |
T7 |
120068 |
861 |
0 |
0 |
T8 |
1819 |
6 |
0 |
0 |
T9 |
65208 |
254 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
272 |
0 |
0 |
T12 |
13528 |
254 |
0 |
0 |
T13 |
59415 |
444 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_34
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_34
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_34
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
274644 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
57 |
0 |
0 |
T4 |
0 |
111 |
0 |
0 |
T7 |
120068 |
88 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
83 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
614 |
0 |
0 |
T12 |
13528 |
114 |
0 |
0 |
T13 |
59415 |
102 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
359605 |
0 |
0 |
T1 |
368421 |
82 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
57 |
0 |
0 |
T4 |
0 |
107 |
0 |
0 |
T7 |
120068 |
95 |
0 |
0 |
T8 |
1819 |
2 |
0 |
0 |
T9 |
65208 |
107 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
333 |
0 |
0 |
T12 |
13528 |
124 |
0 |
0 |
T13 |
59415 |
74 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4140262 |
0 |
0 |
T1 |
368421 |
1560 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
490 |
0 |
0 |
T4 |
0 |
208 |
0 |
0 |
T7 |
120068 |
723 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
202 |
0 |
0 |
T10 |
1833 |
13 |
0 |
0 |
T11 |
34688 |
601 |
0 |
0 |
T12 |
13528 |
218 |
0 |
0 |
T13 |
59415 |
534 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_36
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_36
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_36
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
715662 |
0 |
0 |
T1 |
368421 |
9 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
49 |
0 |
0 |
T4 |
0 |
181 |
0 |
0 |
T7 |
120068 |
90 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
84 |
0 |
0 |
T10 |
1833 |
2 |
0 |
0 |
T11 |
34688 |
202 |
0 |
0 |
T12 |
13528 |
205 |
0 |
0 |
T13 |
59415 |
43 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
877766 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
43 |
0 |
0 |
T4 |
0 |
265 |
0 |
0 |
T7 |
120068 |
85 |
0 |
0 |
T8 |
1819 |
12 |
0 |
0 |
T9 |
65208 |
162 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
178 |
0 |
0 |
T12 |
13528 |
168 |
0 |
0 |
T13 |
59415 |
66 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
3738708 |
0 |
0 |
T1 |
368421 |
2574 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
346 |
0 |
0 |
T4 |
0 |
236 |
0 |
0 |
T7 |
120068 |
811 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
232 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
307 |
0 |
0 |
T12 |
13528 |
250 |
0 |
0 |
T13 |
59415 |
512 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_38
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_38
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T13,T14,T24 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_38
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
702186 |
0 |
0 |
T1 |
368421 |
1714 |
0 |
0 |
T2 |
16071 |
2865 |
0 |
0 |
T3 |
63667 |
51 |
0 |
0 |
T7 |
120068 |
99 |
0 |
0 |
T8 |
1819 |
11 |
0 |
0 |
T9 |
65208 |
108 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
257 |
0 |
0 |
T12 |
13528 |
251 |
0 |
0 |
T13 |
59415 |
64 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
857374 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
2554 |
0 |
0 |
T3 |
63667 |
58 |
0 |
0 |
T7 |
120068 |
107 |
0 |
0 |
T8 |
1819 |
2 |
0 |
0 |
T9 |
65208 |
391 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
241 |
0 |
0 |
T12 |
13528 |
156 |
0 |
0 |
T13 |
59415 |
57 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4363668 |
0 |
0 |
T1 |
368421 |
1022 |
0 |
0 |
T2 |
16071 |
522 |
0 |
0 |
T3 |
63667 |
463 |
0 |
0 |
T7 |
120068 |
741 |
0 |
0 |
T8 |
1819 |
7 |
0 |
0 |
T9 |
65208 |
148 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
318 |
0 |
0 |
T12 |
13528 |
227 |
0 |
0 |
T13 |
59415 |
674 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_40
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_40
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_40
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
588796 |
0 |
0 |
T1 |
368421 |
5 |
0 |
0 |
T2 |
16071 |
4756 |
0 |
0 |
T3 |
63667 |
47 |
0 |
0 |
T7 |
120068 |
100 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
79 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
1150 |
0 |
0 |
T12 |
13528 |
187 |
0 |
0 |
T13 |
59415 |
49 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
724796 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
4471 |
0 |
0 |
T3 |
63667 |
24 |
0 |
0 |
T7 |
120068 |
85 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
72 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
1139 |
0 |
0 |
T12 |
13528 |
208 |
0 |
0 |
T13 |
59415 |
46 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4444640 |
0 |
0 |
T1 |
368421 |
569 |
0 |
0 |
T2 |
16071 |
503 |
0 |
0 |
T3 |
63667 |
383 |
0 |
0 |
T7 |
120068 |
736 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
222 |
0 |
0 |
T10 |
1833 |
13 |
0 |
0 |
T11 |
34688 |
429 |
0 |
0 |
T12 |
13528 |
251 |
0 |
0 |
T13 |
59415 |
410 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_42
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_42
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T14,T24 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_42
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
779821 |
0 |
0 |
T1 |
368421 |
8 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
58 |
0 |
0 |
T4 |
0 |
706 |
0 |
0 |
T7 |
120068 |
115 |
0 |
0 |
T8 |
1819 |
13 |
0 |
0 |
T9 |
65208 |
69 |
0 |
0 |
T10 |
1833 |
2 |
0 |
0 |
T11 |
34688 |
197 |
0 |
0 |
T12 |
13528 |
162 |
0 |
0 |
T13 |
59415 |
201 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
919840 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
40 |
0 |
0 |
T4 |
0 |
581 |
0 |
0 |
T7 |
120068 |
105 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
68 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
207 |
0 |
0 |
T12 |
13528 |
197 |
0 |
0 |
T13 |
59415 |
194 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4137579 |
0 |
0 |
T1 |
368421 |
3741 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
502 |
0 |
0 |
T4 |
0 |
211 |
0 |
0 |
T7 |
120068 |
826 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
167 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
333 |
0 |
0 |
T12 |
13528 |
231 |
0 |
0 |
T13 |
59415 |
421 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_43
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_43
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
296386 |
0 |
0 |
T1 |
368421 |
8 |
0 |
0 |
T2 |
16071 |
1065 |
0 |
0 |
T3 |
63667 |
54 |
0 |
0 |
T7 |
120068 |
109 |
0 |
0 |
T8 |
1819 |
6 |
0 |
0 |
T9 |
65208 |
60 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
191 |
0 |
0 |
T12 |
13528 |
133 |
0 |
0 |
T13 |
59415 |
71 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
403883 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
824 |
0 |
0 |
T3 |
63667 |
49 |
0 |
0 |
T7 |
120068 |
87 |
0 |
0 |
T8 |
1819 |
6 |
0 |
0 |
T9 |
65208 |
57 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
170 |
0 |
0 |
T12 |
13528 |
120 |
0 |
0 |
T13 |
59415 |
83 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4613431 |
0 |
0 |
T1 |
368421 |
3664 |
0 |
0 |
T2 |
16071 |
558 |
0 |
0 |
T3 |
63667 |
473 |
0 |
0 |
T7 |
120068 |
901 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
165 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
353 |
0 |
0 |
T12 |
13528 |
235 |
0 |
0 |
T13 |
59415 |
562 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_44
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_44
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
298494 |
0 |
0 |
T1 |
368421 |
2 |
0 |
0 |
T2 |
16071 |
1909 |
0 |
0 |
T3 |
63667 |
48 |
0 |
0 |
T7 |
120068 |
127 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
77 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
170 |
0 |
0 |
T12 |
13528 |
120 |
0 |
0 |
T13 |
59415 |
69 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
378429 |
0 |
0 |
T1 |
368421 |
322 |
0 |
0 |
T2 |
16071 |
1444 |
0 |
0 |
T3 |
63667 |
51 |
0 |
0 |
T7 |
120068 |
87 |
0 |
0 |
T8 |
1819 |
11 |
0 |
0 |
T9 |
65208 |
96 |
0 |
0 |
T10 |
1833 |
1 |
0 |
0 |
T11 |
34688 |
151 |
0 |
0 |
T12 |
13528 |
107 |
0 |
0 |
T13 |
59415 |
68 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4766485 |
0 |
0 |
T1 |
368421 |
926 |
0 |
0 |
T2 |
16071 |
993 |
0 |
0 |
T3 |
63667 |
428 |
0 |
0 |
T7 |
120068 |
817 |
0 |
0 |
T8 |
1819 |
14 |
0 |
0 |
T9 |
65208 |
198 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
312 |
0 |
0 |
T12 |
13528 |
219 |
0 |
0 |
T13 |
59415 |
663 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_45
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_45
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
337833 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
48 |
0 |
0 |
T4 |
0 |
115 |
0 |
0 |
T7 |
120068 |
117 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
73 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
165 |
0 |
0 |
T12 |
13528 |
138 |
0 |
0 |
T13 |
59415 |
72 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
454671 |
0 |
0 |
T1 |
368421 |
1 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
41 |
0 |
0 |
T4 |
0 |
114 |
0 |
0 |
T7 |
120068 |
85 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
106 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
135 |
0 |
0 |
T12 |
13528 |
116 |
0 |
0 |
T13 |
59415 |
97 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
3283355 |
0 |
0 |
T1 |
368421 |
1076 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
344 |
0 |
0 |
T4 |
0 |
216 |
0 |
0 |
T7 |
120068 |
822 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
210 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
292 |
0 |
0 |
T12 |
13528 |
243 |
0 |
0 |
T13 |
59415 |
505 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_46
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_46
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
303394 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
46 |
0 |
0 |
T4 |
0 |
107 |
0 |
0 |
T7 |
120068 |
94 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
80 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
158 |
0 |
0 |
T12 |
13528 |
119 |
0 |
0 |
T13 |
59415 |
55 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
419797 |
0 |
0 |
T1 |
368421 |
499 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
49 |
0 |
0 |
T4 |
0 |
96 |
0 |
0 |
T7 |
120068 |
88 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
92 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
146 |
0 |
0 |
T12 |
13528 |
113 |
0 |
0 |
T13 |
59415 |
57 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4299240 |
0 |
0 |
T1 |
368421 |
1318 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
446 |
0 |
0 |
T4 |
0 |
192 |
0 |
0 |
T7 |
120068 |
695 |
0 |
0 |
T8 |
1819 |
8 |
0 |
0 |
T9 |
65208 |
181 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
299 |
0 |
0 |
T12 |
13528 |
219 |
0 |
0 |
T13 |
59415 |
344 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_47
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_47
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
305733 |
0 |
0 |
T1 |
368421 |
51 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
68 |
0 |
0 |
T4 |
0 |
125 |
0 |
0 |
T7 |
120068 |
92 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
49 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
149 |
0 |
0 |
T12 |
13528 |
137 |
0 |
0 |
T13 |
59415 |
58 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
402319 |
0 |
0 |
T1 |
368421 |
8 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
52 |
0 |
0 |
T4 |
0 |
95 |
0 |
0 |
T7 |
120068 |
98 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
123 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
156 |
0 |
0 |
T12 |
13528 |
98 |
0 |
0 |
T13 |
59415 |
55 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4014589 |
0 |
0 |
T1 |
368421 |
4754 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
449 |
0 |
0 |
T4 |
0 |
202 |
0 |
0 |
T7 |
120068 |
790 |
0 |
0 |
T8 |
1819 |
9 |
0 |
0 |
T9 |
65208 |
207 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
301 |
0 |
0 |
T12 |
13528 |
218 |
0 |
0 |
T13 |
59415 |
468 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_48
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
340241 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
890 |
0 |
0 |
T3 |
63667 |
53 |
0 |
0 |
T7 |
120068 |
124 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
54 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
2308 |
0 |
0 |
T12 |
13528 |
146 |
0 |
0 |
T13 |
59415 |
67 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
442114 |
0 |
0 |
T1 |
368421 |
129 |
0 |
0 |
T2 |
16071 |
674 |
0 |
0 |
T3 |
63667 |
41 |
0 |
0 |
T7 |
120068 |
107 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
86 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
1838 |
0 |
0 |
T12 |
13528 |
126 |
0 |
0 |
T13 |
59415 |
66 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4199851 |
0 |
0 |
T1 |
368421 |
2404 |
0 |
0 |
T2 |
16071 |
450 |
0 |
0 |
T3 |
63667 |
449 |
0 |
0 |
T7 |
120068 |
1011 |
0 |
0 |
T8 |
1819 |
9 |
0 |
0 |
T9 |
65208 |
176 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
1764 |
0 |
0 |
T12 |
13528 |
261 |
0 |
0 |
T13 |
59415 |
545 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_49
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
334206 |
0 |
0 |
T1 |
368421 |
6 |
0 |
0 |
T2 |
16071 |
1059 |
0 |
0 |
T3 |
63667 |
55 |
0 |
0 |
T7 |
120068 |
114 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
108 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
424 |
0 |
0 |
T12 |
13528 |
127 |
0 |
0 |
T13 |
59415 |
76 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
446984 |
0 |
0 |
T1 |
368421 |
112 |
0 |
0 |
T2 |
16071 |
716 |
0 |
0 |
T3 |
63667 |
48 |
0 |
0 |
T7 |
120068 |
97 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
72 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
363 |
0 |
0 |
T12 |
13528 |
120 |
0 |
0 |
T13 |
59415 |
71 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4027081 |
0 |
0 |
T1 |
368421 |
1785 |
0 |
0 |
T2 |
16071 |
530 |
0 |
0 |
T3 |
63667 |
411 |
0 |
0 |
T7 |
120068 |
1073 |
0 |
0 |
T8 |
1819 |
9 |
0 |
0 |
T9 |
65208 |
272 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
701 |
0 |
0 |
T12 |
13528 |
239 |
0 |
0 |
T13 |
59415 |
601 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_50
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_50
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
326784 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
69 |
0 |
0 |
T4 |
0 |
123 |
0 |
0 |
T7 |
120068 |
94 |
0 |
0 |
T8 |
1819 |
13 |
0 |
0 |
T9 |
65208 |
67 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
162 |
0 |
0 |
T12 |
13528 |
123 |
0 |
0 |
T13 |
59415 |
79 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
449144 |
0 |
0 |
T1 |
368421 |
6 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
50 |
0 |
0 |
T4 |
0 |
83 |
0 |
0 |
T7 |
120068 |
89 |
0 |
0 |
T8 |
1819 |
9 |
0 |
0 |
T9 |
65208 |
102 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
153 |
0 |
0 |
T12 |
13528 |
136 |
0 |
0 |
T13 |
59415 |
106 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4415435 |
0 |
0 |
T1 |
368421 |
812 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
517 |
0 |
0 |
T4 |
0 |
186 |
0 |
0 |
T7 |
120068 |
859 |
0 |
0 |
T8 |
1819 |
20 |
0 |
0 |
T9 |
65208 |
175 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
309 |
0 |
0 |
T12 |
13528 |
249 |
0 |
0 |
T13 |
59415 |
507 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_51
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_51
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
315112 |
0 |
0 |
T1 |
368421 |
2 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
36 |
0 |
0 |
T4 |
0 |
143 |
0 |
0 |
T7 |
120068 |
97 |
0 |
0 |
T8 |
1819 |
2 |
0 |
0 |
T9 |
65208 |
166 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
1075 |
0 |
0 |
T12 |
13528 |
115 |
0 |
0 |
T13 |
59415 |
108 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
425750 |
0 |
0 |
T1 |
368421 |
514 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
64 |
0 |
0 |
T4 |
0 |
106 |
0 |
0 |
T7 |
120068 |
78 |
0 |
0 |
T8 |
1819 |
2 |
0 |
0 |
T9 |
65208 |
142 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
878 |
0 |
0 |
T12 |
13528 |
116 |
0 |
0 |
T13 |
59415 |
109 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4204122 |
0 |
0 |
T1 |
368421 |
605 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
354 |
0 |
0 |
T4 |
0 |
227 |
0 |
0 |
T7 |
120068 |
784 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
373 |
0 |
0 |
T10 |
1833 |
11 |
0 |
0 |
T11 |
34688 |
850 |
0 |
0 |
T12 |
13528 |
216 |
0 |
0 |
T13 |
59415 |
768 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_52
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_52
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
291202 |
0 |
0 |
T1 |
368421 |
145 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
47 |
0 |
0 |
T4 |
0 |
117 |
0 |
0 |
T7 |
120068 |
111 |
0 |
0 |
T8 |
1819 |
2 |
0 |
0 |
T9 |
65208 |
81 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
174 |
0 |
0 |
T12 |
13528 |
123 |
0 |
0 |
T13 |
59415 |
54 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
393788 |
0 |
0 |
T1 |
368421 |
5 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
38 |
0 |
0 |
T4 |
0 |
108 |
0 |
0 |
T7 |
120068 |
89 |
0 |
0 |
T8 |
1819 |
6 |
0 |
0 |
T9 |
65208 |
128 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
150 |
0 |
0 |
T12 |
13528 |
130 |
0 |
0 |
T13 |
59415 |
71 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4819349 |
0 |
0 |
T1 |
368421 |
2194 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
488 |
0 |
0 |
T4 |
0 |
214 |
0 |
0 |
T7 |
120068 |
937 |
0 |
0 |
T8 |
1819 |
8 |
0 |
0 |
T9 |
65208 |
271 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
316 |
0 |
0 |
T12 |
13528 |
239 |
0 |
0 |
T13 |
59415 |
484 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_53
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_53
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
324031 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
48 |
0 |
0 |
T4 |
0 |
122 |
0 |
0 |
T7 |
120068 |
95 |
0 |
0 |
T8 |
1819 |
2 |
0 |
0 |
T9 |
65208 |
109 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
185 |
0 |
0 |
T12 |
13528 |
111 |
0 |
0 |
T13 |
59415 |
75 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
418591 |
0 |
0 |
T1 |
368421 |
94 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
82 |
0 |
0 |
T4 |
0 |
113 |
0 |
0 |
T7 |
120068 |
117 |
0 |
0 |
T8 |
1819 |
5 |
0 |
0 |
T9 |
65208 |
74 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
145 |
0 |
0 |
T12 |
13528 |
118 |
0 |
0 |
T13 |
59415 |
90 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4387714 |
0 |
0 |
T1 |
368421 |
921 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
479 |
0 |
0 |
T4 |
0 |
221 |
0 |
0 |
T7 |
120068 |
842 |
0 |
0 |
T8 |
1819 |
7 |
0 |
0 |
T9 |
65208 |
229 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
322 |
0 |
0 |
T12 |
13528 |
223 |
0 |
0 |
T13 |
59415 |
633 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_54
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_54
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
334055 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
57 |
0 |
0 |
T4 |
0 |
132 |
0 |
0 |
T7 |
120068 |
99 |
0 |
0 |
T8 |
1819 |
7 |
0 |
0 |
T9 |
65208 |
114 |
0 |
0 |
T10 |
1833 |
9 |
0 |
0 |
T11 |
34688 |
750 |
0 |
0 |
T12 |
13528 |
121 |
0 |
0 |
T13 |
59415 |
101 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
445320 |
0 |
0 |
T1 |
368421 |
5 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
48 |
0 |
0 |
T4 |
0 |
114 |
0 |
0 |
T7 |
120068 |
99 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
105 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
938 |
0 |
0 |
T12 |
13528 |
127 |
0 |
0 |
T13 |
59415 |
76 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4571047 |
0 |
0 |
T1 |
368421 |
1438 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
501 |
0 |
0 |
T4 |
0 |
232 |
0 |
0 |
T7 |
120068 |
865 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
236 |
0 |
0 |
T10 |
1833 |
11 |
0 |
0 |
T11 |
34688 |
1325 |
0 |
0 |
T12 |
13528 |
231 |
0 |
0 |
T13 |
59415 |
570 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_55
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T13 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_55
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
313140 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
42 |
0 |
0 |
T4 |
0 |
124 |
0 |
0 |
T7 |
120068 |
127 |
0 |
0 |
T8 |
1819 |
6 |
0 |
0 |
T9 |
65208 |
56 |
0 |
0 |
T10 |
1833 |
6 |
0 |
0 |
T11 |
34688 |
148 |
0 |
0 |
T12 |
13528 |
119 |
0 |
0 |
T13 |
59415 |
84 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
420544 |
0 |
0 |
T1 |
368421 |
476 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
62 |
0 |
0 |
T4 |
0 |
92 |
0 |
0 |
T7 |
120068 |
96 |
0 |
0 |
T8 |
1819 |
3 |
0 |
0 |
T9 |
65208 |
100 |
0 |
0 |
T10 |
1833 |
4 |
0 |
0 |
T11 |
34688 |
168 |
0 |
0 |
T12 |
13528 |
127 |
0 |
0 |
T13 |
59415 |
85 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4372913 |
0 |
0 |
T1 |
368421 |
1277 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
293 |
0 |
0 |
T4 |
0 |
206 |
0 |
0 |
T7 |
120068 |
1001 |
0 |
0 |
T8 |
1819 |
8 |
0 |
0 |
T9 |
65208 |
202 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
312 |
0 |
0 |
T12 |
13528 |
234 |
0 |
0 |
T13 |
59415 |
538 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
2 |
2 |
105 |
2 |
2 |
108 |
2 |
2 |
163 |
2 |
2 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
2 |
2 |
238 |
2 |
2 |
242 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_sm1_56
| Total | Covered | Percent |
Conditions | 22 | 20 | 90.91 |
Logical | 22 | 20 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T13,T14 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_56
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
302976 |
0 |
0 |
T1 |
368421 |
4 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
57 |
0 |
0 |
T4 |
0 |
126 |
0 |
0 |
T7 |
120068 |
95 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
59 |
0 |
0 |
T10 |
1833 |
3 |
0 |
0 |
T11 |
34688 |
165 |
0 |
0 |
T12 |
13528 |
135 |
0 |
0 |
T13 |
59415 |
85 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
408527 |
0 |
0 |
T1 |
368421 |
3 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
53 |
0 |
0 |
T4 |
0 |
106 |
0 |
0 |
T7 |
120068 |
88 |
0 |
0 |
T8 |
1819 |
6 |
0 |
0 |
T9 |
65208 |
73 |
0 |
0 |
T10 |
1833 |
7 |
0 |
0 |
T11 |
34688 |
122 |
0 |
0 |
T12 |
13528 |
129 |
0 |
0 |
T13 |
59415 |
56 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
4468849 |
0 |
0 |
T1 |
368421 |
2269 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
521 |
0 |
0 |
T4 |
0 |
214 |
0 |
0 |
T7 |
120068 |
765 |
0 |
0 |
T8 |
1819 |
10 |
0 |
0 |
T9 |
65208 |
224 |
0 |
0 |
T10 |
1833 |
10 |
0 |
0 |
T11 |
34688 |
280 |
0 |
0 |
T12 |
13528 |
245 |
0 |
0 |
T13 |
59415 |
644 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_30
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
3 |
3 |
105 |
3 |
3 |
108 |
3 |
3 |
163 |
3 |
3 |
166 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
231 |
1 |
1 |
236 |
3 |
3 |
238 |
3 |
3 |
242 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_sm1_30
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T11 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 236
EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
---------1--------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 236
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Covered | T3,T10,T11 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T10,T11 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 238
EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
-----------1---------- ------------------2------------------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T10,T11 |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 238
SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
Assert Coverage for Instance : tb.dut.u_sm1_30
Assertion Details
gen_host_fifo[0].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
10234276 |
0 |
0 |
T1 |
368421 |
6871 |
0 |
0 |
T2 |
16071 |
504 |
0 |
0 |
T3 |
63667 |
2450 |
0 |
0 |
T7 |
120068 |
4257 |
0 |
0 |
T8 |
1819 |
43 |
0 |
0 |
T9 |
65208 |
2944 |
0 |
0 |
T10 |
1833 |
35 |
0 |
0 |
T11 |
34688 |
1767 |
0 |
0 |
T12 |
13528 |
660 |
0 |
0 |
T13 |
59415 |
2825 |
0 |
0 |
gen_host_fifo[1].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
1858458 |
0 |
0 |
T1 |
368421 |
1925 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
416 |
0 |
0 |
T4 |
0 |
94 |
0 |
0 |
T7 |
120068 |
795 |
0 |
0 |
T8 |
1819 |
7 |
0 |
0 |
T9 |
65208 |
408 |
0 |
0 |
T10 |
1833 |
8 |
0 |
0 |
T11 |
34688 |
125 |
0 |
0 |
T12 |
13528 |
102 |
0 |
0 |
T13 |
59415 |
555 |
0 |
0 |
gen_host_fifo[2].idInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
2012774 |
0 |
0 |
T1 |
368421 |
1617 |
0 |
0 |
T2 |
16071 |
0 |
0 |
0 |
T3 |
63667 |
470 |
0 |
0 |
T4 |
0 |
102 |
0 |
0 |
T7 |
120068 |
751 |
0 |
0 |
T8 |
1819 |
4 |
0 |
0 |
T9 |
65208 |
587 |
0 |
0 |
T10 |
1833 |
5 |
0 |
0 |
T11 |
34688 |
151 |
0 |
0 |
T12 |
13528 |
107 |
0 |
0 |
T13 |
59415 |
520 |
0 |
0 |
maxM
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
rspIdInRange
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424342108 |
18855168 |
0 |
0 |
T1 |
368421 |
9284 |
0 |
0 |
T2 |
16071 |
504 |
0 |
0 |
T3 |
63667 |
2930 |
0 |
0 |
T7 |
120068 |
5237 |
0 |
0 |
T8 |
1819 |
54 |
0 |
0 |
T9 |
65208 |
2891 |
0 |
0 |
T10 |
1833 |
48 |
0 |
0 |
T11 |
34688 |
2020 |
0 |
0 |
T12 |
13528 |
855 |
0 |
0 |
T13 |
59415 |
1697 |
0 |
0 |