Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7968922	0	0
GntImpliesValid_A	2147483647	7968922	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7968922	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	460753165	0	0
ReadyAndValidImplyGrant_A	2147483647	7968922	0	0
ReqAndReadyImplyGrant_A	2147483647	7968922	0	0
ReqImpliesValid_A	2147483647	35276076	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42679	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7968922	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8842104	8841504	0	0
T2	385704	385272	0	0
T3	1528008	1527168	0	0
T7	2881632	2881128	0	0
T8	43656	42744	0	0
T9	1564992	1564200	0	0
T10	43992	43392	0	0
T11	832512	801144	0	0
T12	324672	323760	0	0
T13	1425960	1425408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968922	0	0
T1	8842104	352	0	0
T2	385704	6919	0	0
T3	1528008	3619	0	0
T4	0	2765	0	0
T7	2881632	6792	0	0
T8	43656	379	0	0
T9	1564992	4695	0	0
T10	43992	346	0	0
T11	832512	18742	0	0
T12	324672	8425	0	0
T13	1425960	4369	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968922	0	0
T1	8842104	352	0	0
T2	385704	6919	0	0
T3	1528008	3619	0	0
T4	0	2765	0	0
T7	2881632	6792	0	0
T8	43656	379	0	0
T9	1564992	4695	0	0
T10	43992	346	0	0
T11	832512	18742	0	0
T12	324672	8425	0	0
T13	1425960	4369	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8842104	8841504	0	0
T2	385704	385272	0	0
T3	1528008	1527168	0	0
T7	2881632	2881128	0	0
T8	43656	42744	0	0
T9	1564992	1564200	0	0
T10	43992	43392	0	0
T11	832512	801144	0	0
T12	324672	323760	0	0
T13	1425960	1425408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8842104	8841504	0	0
T2	385704	385272	0	0
T3	1528008	1527168	0	0
T7	2881632	2881128	0	0
T8	43656	42744	0	0
T9	1564992	1564200	0	0
T10	43992	43392	0	0
T11	832512	801144	0	0
T12	324672	323760	0	0
T13	1425960	1425408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968922	0	0
T1	8842104	352	0	0
T2	385704	6919	0	0
T3	1528008	3619	0	0
T4	0	2765	0	0
T7	2881632	6792	0	0
T8	43656	379	0	0
T9	1564992	4695	0	0
T10	43992	346	0	0
T11	832512	18742	0	0
T12	324672	8425	0	0
T13	1425960	4369	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	460753165	0	0
T1	8842104	457029	0	0
T2	385704	840	0	0
T3	1528008	78883	0	0
T4	0	6120	0	0
T7	2881632	152172	0	0
T8	43656	525	0	0
T9	1564992	91626	0	0
T10	43992	612	0	0
T11	832512	18991	0	0
T12	324672	9447	0	0
T13	1425960	80923	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968922	0	0
T1	8842104	352	0	0
T2	385704	6919	0	0
T3	1528008	3619	0	0
T4	0	2765	0	0
T7	2881632	6792	0	0
T8	43656	379	0	0
T9	1564992	4695	0	0
T10	43992	346	0	0
T11	832512	18742	0	0
T12	324672	8425	0	0
T13	1425960	4369	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968922	0	0
T1	8842104	352	0	0
T2	385704	6919	0	0
T3	1528008	3619	0	0
T4	0	2765	0	0
T7	2881632	6792	0	0
T8	43656	379	0	0
T9	1564992	4695	0	0
T10	43992	346	0	0
T11	832512	18742	0	0
T12	324672	8425	0	0
T13	1425960	4369	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35276076	0	0
T1	8842104	16326	0	0
T2	385704	17578	0	0
T3	1528008	6718	0	0
T4	0	4190	0	0
T7	2881632	12339	0	0
T8	43656	429	0	0
T9	1564992	9995	0	0
T10	43992	373	0	0
T11	832512	23174	0	0
T12	324672	9678	0	0
T13	1425960	9230	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42679	0	21600
T4	38876	20	0	2
T5	138374	0	0	2
T11	69376	37	0	2
T12	27056	33	0	2
T13	118830	0	0	2
T14	236764	1	0	2
T15	7092	3	0	2
T16	39010	13	0	2
T17	0	21	0	0
T18	0	5	0	0
T19	0	97	0	0
T20	0	5	0	0
T21	0	296	0	0
T22	0	15	0	0
T23	19862	0	0	2
T24	776084	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8842104	8841504	0	0
T2	385704	385272	0	0
T3	1528008	1527168	0	0
T7	2881632	2881128	0	0
T8	43656	42744	0	0
T9	1564992	1564200	0	0
T10	43992	43392	0	0
T11	832512	801144	0	0
T12	324672	323760	0	0
T13	1425960	1425408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968922	0	0
T1	8842104	352	0	0
T2	385704	6919	0	0
T3	1528008	3619	0	0
T4	0	2765	0	0
T7	2881632	6792	0	0
T8	43656	379	0	0
T9	1564992	4695	0	0
T10	43992	346	0	0
T11	832512	18742	0	0
T12	324672	8425	0	0
T13	1425960	4369	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	890235	0	0
GntImpliesValid_A	424342108	890235	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	890235	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	12091102	0	0
ReadyAndValidImplyGrant_A	424342108	890235	0	0
ReqAndReadyImplyGrant_A	424342108	890235	0	0
ReqImpliesValid_A	424342108	2499710	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	890235	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	890235	0	0
T1	368421	42	0	0
T2	16071	524	0	0
T3	63667	434	0	0
T7	120068	766	0	0
T8	1819	48	0	0
T9	65208	532	0	0
T10	1833	44	0	0
T11	34688	1948	0	0
T12	13528	966	0	0
T13	59415	461	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	890235	0	0
T1	368421	42	0	0
T2	16071	524	0	0
T3	63667	434	0	0
T7	120068	766	0	0
T8	1819	48	0	0
T9	65208	532	0	0
T10	1833	44	0	0
T11	34688	1948	0	0
T12	13528	966	0	0
T13	59415	461	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	890235	0	0
T1	368421	42	0	0
T2	16071	524	0	0
T3	63667	434	0	0
T7	120068	766	0	0
T8	1819	48	0	0
T9	65208	532	0	0
T10	1833	44	0	0
T11	34688	1948	0	0
T12	13528	966	0	0
T13	59415	461	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	12091102	0	0
T1	368421	14618	0	0
T2	16071	381	0	0
T3	63667	3231	0	0
T7	120068	5588	0	0
T8	1819	34	0	0
T9	65208	4117	0	0
T10	1833	34	0	0
T11	34688	1603	0	0
T12	13528	702	0	0
T13	59415	3543	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	890235	0	0
T1	368421	42	0	0
T2	16071	524	0	0
T3	63667	434	0	0
T7	120068	766	0	0
T8	1819	48	0	0
T9	65208	532	0	0
T10	1833	44	0	0
T11	34688	1948	0	0
T12	13528	966	0	0
T13	59415	461	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	890235	0	0
T1	368421	42	0	0
T2	16071	524	0	0
T3	63667	434	0	0
T7	120068	766	0	0
T8	1819	48	0	0
T9	65208	532	0	0
T10	1833	44	0	0
T11	34688	1948	0	0
T12	13528	966	0	0
T13	59415	461	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2499710	0	0
T1	368421	242	0	0
T2	16071	668	0	0
T3	63667	470	0	0
T7	120068	870	0	0
T8	1819	63	0	0
T9	65208	820	0	0
T10	1833	55	0	0
T11	34688	2309	0	0
T12	13528	1231	0	0
T13	59415	693	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	890235	0	0
T1	368421	42	0	0
T2	16071	524	0	0
T3	63667	434	0	0
T7	120068	766	0	0
T8	1819	48	0	0
T9	65208	532	0	0
T10	1833	44	0	0
T11	34688	1948	0	0
T12	13528	966	0	0
T13	59415	461	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	898025	0	0
GntImpliesValid_A	424342108	898025	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	898025	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	12436203	0	0
ReadyAndValidImplyGrant_A	424342108	898025	0	0
ReqAndReadyImplyGrant_A	424342108	898025	0	0
ReqImpliesValid_A	424342108	2729192	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	898025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	898025	0	0
T1	368421	42	0	0
T2	16071	1316	0	0
T3	63667	434	0	0
T7	120068	775	0	0
T8	1819	42	0	0
T9	65208	497	0	0
T10	1833	37	0	0
T11	34688	2748	0	0
T12	13528	933	0	0
T13	59415	500	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	898025	0	0
T1	368421	42	0	0
T2	16071	1316	0	0
T3	63667	434	0	0
T7	120068	775	0	0
T8	1819	42	0	0
T9	65208	497	0	0
T10	1833	37	0	0
T11	34688	2748	0	0
T12	13528	933	0	0
T13	59415	500	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	898025	0	0
T1	368421	42	0	0
T2	16071	1316	0	0
T3	63667	434	0	0
T7	120068	775	0	0
T8	1819	42	0	0
T9	65208	497	0	0
T10	1833	37	0	0
T11	34688	2748	0	0
T12	13528	933	0	0
T13	59415	500	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	12436203	0	0
T1	368421	15173	0	0
T2	16071	361	0	0
T3	63667	3283	0	0
T7	120068	5934	0	0
T8	1819	38	0	0
T9	65208	3688	0	0
T10	1833	24	0	0
T11	34688	2018	0	0
T12	13528	682	0	0
T13	59415	3819	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	898025	0	0
T1	368421	42	0	0
T2	16071	1316	0	0
T3	63667	434	0	0
T7	120068	775	0	0
T8	1819	42	0	0
T9	65208	497	0	0
T10	1833	37	0	0
T11	34688	2748	0	0
T12	13528	933	0	0
T13	59415	500	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	898025	0	0
T1	368421	42	0	0
T2	16071	1316	0	0
T3	63667	434	0	0
T7	120068	775	0	0
T8	1819	42	0	0
T9	65208	497	0	0
T10	1833	37	0	0
T11	34688	2748	0	0
T12	13528	933	0	0
T13	59415	500	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2729192	0	0
T1	368421	687	0	0
T2	16071	2272	0	0
T3	63667	477	0	0
T7	120068	851	0	0
T8	1819	47	0	0
T9	65208	708	0	0
T10	1833	51	0	0
T11	34688	3495	0	0
T12	13528	1185	0	0
T13	59415	777	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	898025	0	0
T1	368421	42	0	0
T2	16071	1316	0	0
T3	63667	434	0	0
T7	120068	775	0	0
T8	1819	42	0	0
T9	65208	497	0	0
T10	1833	37	0	0
T11	34688	2748	0	0
T12	13528	933	0	0
T13	59415	500	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	224069	0	0
GntImpliesValid_A	424342108	224069	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	224069	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3051833	0	0
ReadyAndValidImplyGrant_A	424342108	224069	0	0
ReqAndReadyImplyGrant_A	424342108	224069	0	0
ReqImpliesValid_A	424342108	599435	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	224069	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224069	0	0
T1	368421	13	0	0
T2	16071	501	0	0
T3	63667	102	0	0
T7	120068	193	0	0
T8	1819	6	0	0
T9	65208	140	0	0
T10	1833	7	0	0
T11	34688	272	0	0
T12	13528	254	0	0
T13	59415	124	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224069	0	0
T1	368421	13	0	0
T2	16071	501	0	0
T3	63667	102	0	0
T7	120068	193	0	0
T8	1819	6	0	0
T9	65208	140	0	0
T10	1833	7	0	0
T11	34688	272	0	0
T12	13528	254	0	0
T13	59415	124	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224069	0	0
T1	368421	13	0	0
T2	16071	501	0	0
T3	63667	102	0	0
T7	120068	193	0	0
T8	1819	6	0	0
T9	65208	140	0	0
T10	1833	7	0	0
T11	34688	272	0	0
T12	13528	254	0	0
T13	59415	124	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3051833	0	0
T1	368421	5166	0	0
T2	16071	2	0	0
T3	63667	717	0	0
T7	120068	1400	0	0
T8	1819	7	0	0
T9	65208	1044	0	0
T10	1833	8	0	0
T11	34688	288	0	0
T12	13528	243	0	0
T13	59415	864	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224069	0	0
T1	368421	13	0	0
T2	16071	501	0	0
T3	63667	102	0	0
T7	120068	193	0	0
T8	1819	6	0	0
T9	65208	140	0	0
T10	1833	7	0	0
T11	34688	272	0	0
T12	13528	254	0	0
T13	59415	124	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224069	0	0
T1	368421	13	0	0
T2	16071	501	0	0
T3	63667	102	0	0
T7	120068	193	0	0
T8	1819	6	0	0
T9	65208	140	0	0
T10	1833	7	0	0
T11	34688	272	0	0
T12	13528	254	0	0
T13	59415	124	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	599435	0	0
T1	368421	13	0	0
T2	16071	1001	0	0
T3	63667	102	0	0
T7	120068	196	0	0
T8	1819	6	0	0
T9	65208	164	0	0
T10	1833	7	0	0
T11	34688	273	0	0
T12	13528	266	0	0
T13	59415	194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224069	0	0
T1	368421	13	0	0
T2	16071	501	0	0
T3	63667	102	0	0
T7	120068	193	0	0
T8	1819	6	0	0
T9	65208	140	0	0
T10	1833	7	0	0
T11	34688	272	0	0
T12	13528	254	0	0
T13	59415	124	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	214274	0	0
GntImpliesValid_A	424342108	214274	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	214274	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	2904065	0	0
ReadyAndValidImplyGrant_A	424342108	214274	0	0
ReqAndReadyImplyGrant_A	424342108	214274	0	0
ReqImpliesValid_A	424342108	538615	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	214274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214274	0	0
T1	368421	9	0	0
T2	16071	0	0	0
T3	63667	107	0	0
T4	0	208	0	0
T7	120068	181	0	0
T8	1819	5	0	0
T9	65208	134	0	0
T10	1833	13	0	0
T11	34688	602	0	0
T12	13528	218	0	0
T13	59415	126	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214274	0	0
T1	368421	9	0	0
T2	16071	0	0	0
T3	63667	107	0	0
T4	0	208	0	0
T7	120068	181	0	0
T8	1819	5	0	0
T9	65208	134	0	0
T10	1833	13	0	0
T11	34688	602	0	0
T12	13528	218	0	0
T13	59415	126	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214274	0	0
T1	368421	9	0	0
T2	16071	0	0	0
T3	63667	107	0	0
T4	0	208	0	0
T7	120068	181	0	0
T8	1819	5	0	0
T9	65208	134	0	0
T10	1833	13	0	0
T11	34688	602	0	0
T12	13528	218	0	0
T13	59415	126	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2904065	0	0
T1	368421	2899	0	0
T2	16071	1	0	0
T3	63667	822	0	0
T7	120068	1351	0	0
T8	1819	6	0	0
T9	65208	1036	0	0
T10	1833	13	0	0
T11	34688	399	0	0
T12	13528	205	0	0
T13	59415	917	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214274	0	0
T1	368421	9	0	0
T2	16071	0	0	0
T3	63667	107	0	0
T4	0	208	0	0
T7	120068	181	0	0
T8	1819	5	0	0
T9	65208	134	0	0
T10	1833	13	0	0
T11	34688	602	0	0
T12	13528	218	0	0
T13	59415	126	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214274	0	0
T1	368421	9	0	0
T2	16071	0	0	0
T3	63667	107	0	0
T4	0	208	0	0
T7	120068	181	0	0
T8	1819	5	0	0
T9	65208	134	0	0
T10	1833	13	0	0
T11	34688	602	0	0
T12	13528	218	0	0
T13	59415	126	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	538615	0	0
T1	368421	86	0	0
T2	16071	0	0	0
T3	63667	114	0	0
T4	0	217	0	0
T7	120068	182	0	0
T8	1819	5	0	0
T9	65208	189	0	0
T10	1833	14	0	0
T11	34688	822	0	0
T12	13528	232	0	0
T13	59415	176	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214274	0	0
T1	368421	9	0	0
T2	16071	0	0	0
T3	63667	107	0	0
T4	0	208	0	0
T7	120068	181	0	0
T8	1819	5	0	0
T9	65208	134	0	0
T10	1833	13	0	0
T11	34688	602	0	0
T12	13528	218	0	0
T13	59415	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	213954	0	0
GntImpliesValid_A	424342108	213954	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	213954	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	5111075	0	0
ReadyAndValidImplyGrant_A	424342108	213954	0	0
ReqAndReadyImplyGrant_A	424342108	213954	0	0
ReqImpliesValid_A	424342108	1231407	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	213954	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	213954	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	236	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	148	0	0
T10	1833	5	0	0
T11	34688	308	0	0
T12	13528	250	0	0
T13	59415	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	213954	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	236	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	148	0	0
T10	1833	5	0	0
T11	34688	308	0	0
T12	13528	250	0	0
T13	59415	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	213954	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	236	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	148	0	0
T10	1833	5	0	0
T11	34688	308	0	0
T12	13528	250	0	0
T13	59415	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	5111075	0	0
T1	368421	933	0	0
T2	16071	0	0	0
T3	63667	1030	0	0
T4	0	1331	0	0
T7	120068	1252	0	0
T8	1819	46	0	0
T9	65208	1601	0	0
T10	1833	50	0	0
T11	34688	2002	0	0
T12	13528	973	0	0
T13	59415	592	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	213954	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	236	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	148	0	0
T10	1833	5	0	0
T11	34688	308	0	0
T12	13528	250	0	0
T13	59415	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	213954	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	236	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	148	0	0
T10	1833	5	0	0
T11	34688	308	0	0
T12	13528	250	0	0
T13	59415	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	1231407	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	446	0	0
T7	120068	175	0	0
T8	1819	15	0	0
T9	65208	240	0	0
T10	1833	5	0	0
T11	34688	379	0	0
T12	13528	366	0	0
T13	59415	109	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	213954	0	0
T1	368421	13	0	0
T2	16071	0	0	0
T3	63667	92	0	0
T4	0	236	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	148	0	0
T10	1833	5	0	0
T11	34688	308	0	0
T12	13528	250	0	0
T13	59415	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	222867	0	0
GntImpliesValid_A	424342108	222867	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	222867	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	5099211	0	0
ReadyAndValidImplyGrant_A	424342108	222867	0	0
ReqAndReadyImplyGrant_A	424342108	222867	0	0
ReqImpliesValid_A	424342108	1196373	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	222867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	222867	0	0
T1	368421	7	0	0
T2	16071	522	0	0
T3	63667	96	0	0
T7	120068	182	0	0
T8	1819	7	0	0
T9	65208	130	0	0
T10	1833	8	0	0
T11	34688	319	0	0
T12	13528	227	0	0
T13	59415	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	222867	0	0
T1	368421	7	0	0
T2	16071	522	0	0
T3	63667	96	0	0
T7	120068	182	0	0
T8	1819	7	0	0
T9	65208	130	0	0
T10	1833	8	0	0
T11	34688	319	0	0
T12	13528	227	0	0
T13	59415	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	222867	0	0
T1	368421	7	0	0
T2	16071	522	0	0
T3	63667	96	0	0
T7	120068	182	0	0
T8	1819	7	0	0
T9	65208	130	0	0
T10	1833	8	0	0
T11	34688	319	0	0
T12	13528	227	0	0
T13	59415	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	5099211	0	0
T1	368421	6043	0	0
T2	16071	4	0	0
T3	63667	972	0	0
T7	120068	2504	0	0
T8	1819	37	0	0
T9	65208	4359	0	0
T10	1833	37	0	0
T11	34688	2256	0	0
T12	13528	1330	0	0
T13	59415	700	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	222867	0	0
T1	368421	7	0	0
T2	16071	522	0	0
T3	63667	96	0	0
T7	120068	182	0	0
T8	1819	7	0	0
T9	65208	130	0	0
T10	1833	8	0	0
T11	34688	319	0	0
T12	13528	227	0	0
T13	59415	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	222867	0	0
T1	368421	7	0	0
T2	16071	522	0	0
T3	63667	96	0	0
T7	120068	182	0	0
T8	1819	7	0	0
T9	65208	130	0	0
T10	1833	8	0	0
T11	34688	319	0	0
T12	13528	227	0	0
T13	59415	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	1196373	0	0
T1	368421	1717	0	0
T2	16071	2865	0	0
T3	63667	109	0	0
T7	120068	206	0	0
T8	1819	13	0	0
T9	65208	499	0	0
T10	1833	8	0	0
T11	34688	485	0	0
T12	13528	394	0	0
T13	59415	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	222867	0	0
T1	368421	7	0	0
T2	16071	522	0	0
T3	63667	96	0	0
T7	120068	182	0	0
T8	1819	7	0	0
T9	65208	130	0	0
T10	1833	8	0	0
T11	34688	319	0	0
T12	13528	227	0	0
T13	59415	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	210640	0	0
GntImpliesValid_A	424342108	210640	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	210640	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	4526716	0	0
ReadyAndValidImplyGrant_A	424342108	210640	0	0
ReqAndReadyImplyGrant_A	424342108	210640	0	0
ReqImpliesValid_A	424342108	1008189	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	210640	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	210640	0	0
T1	368421	8	0	0
T2	16071	503	0	0
T3	63667	71	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	117	0	0
T10	1833	13	0	0
T11	34688	440	0	0
T12	13528	251	0	0
T13	59415	95	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	210640	0	0
T1	368421	8	0	0
T2	16071	503	0	0
T3	63667	71	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	117	0	0
T10	1833	13	0	0
T11	34688	440	0	0
T12	13528	251	0	0
T13	59415	95	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	210640	0	0
T1	368421	8	0	0
T2	16071	503	0	0
T3	63667	71	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	117	0	0
T10	1833	13	0	0
T11	34688	440	0	0
T12	13528	251	0	0
T13	59415	95	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	4526716	0	0
T1	368421	2598	0	0
T2	16071	7	0	0
T3	63667	1094	0	0
T7	120068	1350	0	0
T8	1819	155	0	0
T9	65208	1116	0	0
T10	1833	237	0	0
T11	34688	2561	0	0
T12	13528	1123	0	0
T13	59415	800	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	210640	0	0
T1	368421	8	0	0
T2	16071	503	0	0
T3	63667	71	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	117	0	0
T10	1833	13	0	0
T11	34688	440	0	0
T12	13528	251	0	0
T13	59415	95	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	210640	0	0
T1	368421	8	0	0
T2	16071	503	0	0
T3	63667	71	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	117	0	0
T10	1833	13	0	0
T11	34688	440	0	0
T12	13528	251	0	0
T13	59415	95	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	1008189	0	0
T1	368421	8	0	0
T2	16071	4756	0	0
T3	63667	71	0	0
T7	120068	185	0	0
T8	1819	10	0	0
T9	65208	151	0	0
T10	1833	13	0	0
T11	34688	1431	0	0
T12	13528	389	0	0
T13	59415	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	210640	0	0
T1	368421	8	0	0
T2	16071	503	0	0
T3	63667	71	0	0
T7	120068	173	0	0
T8	1819	10	0	0
T9	65208	117	0	0
T10	1833	13	0	0
T11	34688	440	0	0
T12	13528	251	0	0
T13	59415	95	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	212090	0	0
GntImpliesValid_A	424342108	212090	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	212090	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	4961988	0	0
ReadyAndValidImplyGrant_A	424342108	212090	0	0
ReqAndReadyImplyGrant_A	424342108	212090	0	0
ReqImpliesValid_A	424342108	1263034	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	212090	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	212090	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	211	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	119	0	0
T10	1833	6	0	0
T11	34688	336	0	0
T12	13528	231	0	0
T13	59415	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	212090	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	211	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	119	0	0
T10	1833	6	0	0
T11	34688	336	0	0
T12	13528	231	0	0
T13	59415	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	212090	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	211	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	119	0	0
T10	1833	6	0	0
T11	34688	336	0	0
T12	13528	231	0	0
T13	59415	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	4961988	0	0
T1	368421	1464	0	0
T2	16071	0	0	0
T3	63667	1166	0	0
T4	0	4789	0	0
T7	120068	3488	0	0
T8	1819	56	0	0
T9	65208	1346	0	0
T10	1833	64	0	0
T11	34688	1681	0	0
T12	13528	1063	0	0
T13	59415	2720	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	212090	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	211	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	119	0	0
T10	1833	6	0	0
T11	34688	336	0	0
T12	13528	231	0	0
T13	59415	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	212090	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	211	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	119	0	0
T10	1833	6	0	0
T11	34688	336	0	0
T12	13528	231	0	0
T13	59415	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	1263034	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	1281	0	0
T7	120068	220	0	0
T8	1819	23	0	0
T9	65208	137	0	0
T10	1833	6	0	0
T11	34688	398	0	0
T12	13528	359	0	0
T13	59415	388	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	212090	0	0
T1	368421	12	0	0
T2	16071	0	0	0
T3	63667	98	0	0
T4	0	211	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	119	0	0
T10	1833	6	0	0
T11	34688	336	0	0
T12	13528	231	0	0
T13	59415	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	217174	0	0
GntImpliesValid_A	424342108	217174	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	217174	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3018366	0	0
ReadyAndValidImplyGrant_A	424342108	217174	0	0
ReqAndReadyImplyGrant_A	424342108	217174	0	0
ReqImpliesValid_A	424342108	593487	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	217174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217174	0	0
T1	368421	12	0	0
T2	16071	558	0	0
T3	63667	103	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	104	0	0
T10	1833	10	0	0
T11	34688	353	0	0
T12	13528	235	0	0
T13	59415	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217174	0	0
T1	368421	12	0	0
T2	16071	558	0	0
T3	63667	103	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	104	0	0
T10	1833	10	0	0
T11	34688	353	0	0
T12	13528	235	0	0
T13	59415	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217174	0	0
T1	368421	12	0	0
T2	16071	558	0	0
T3	63667	103	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	104	0	0
T10	1833	10	0	0
T11	34688	353	0	0
T12	13528	235	0	0
T13	59415	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3018366	0	0
T1	368421	3565	0	0
T2	16071	26	0	0
T3	63667	789	0	0
T7	120068	1499	0	0
T8	1819	9	0	0
T9	65208	840	0	0
T10	1833	11	0	0
T11	34688	363	0	0
T12	13528	219	0	0
T13	59415	968	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217174	0	0
T1	368421	12	0	0
T2	16071	558	0	0
T3	63667	103	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	104	0	0
T10	1833	10	0	0
T11	34688	353	0	0
T12	13528	235	0	0
T13	59415	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217174	0	0
T1	368421	12	0	0
T2	16071	558	0	0
T3	63667	103	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	104	0	0
T10	1833	10	0	0
T11	34688	353	0	0
T12	13528	235	0	0
T13	59415	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	593487	0	0
T1	368421	12	0	0
T2	16071	1091	0	0
T3	63667	103	0	0
T7	120068	196	0	0
T8	1819	12	0	0
T9	65208	117	0	0
T10	1833	10	0	0
T11	34688	360	0	0
T12	13528	252	0	0
T13	59415	154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217174	0	0
T1	368421	12	0	0
T2	16071	558	0	0
T3	63667	103	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	104	0	0
T10	1833	10	0	0
T11	34688	353	0	0
T12	13528	235	0	0
T13	59415	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	217547	0	0
GntImpliesValid_A	424342108	217547	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	217547	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3065368	0	0
ReadyAndValidImplyGrant_A	424342108	217547	0	0
ReqAndReadyImplyGrant_A	424342108	217547	0	0
ReqImpliesValid_A	424342108	566544	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	217547	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217547	0	0
T1	368421	9	0	0
T2	16071	993	0	0
T3	63667	97	0	0
T7	120068	193	0	0
T8	1819	14	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	312	0	0
T12	13528	219	0	0
T13	59415	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217547	0	0
T1	368421	9	0	0
T2	16071	993	0	0
T3	63667	97	0	0
T7	120068	193	0	0
T8	1819	14	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	312	0	0
T12	13528	219	0	0
T13	59415	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217547	0	0
T1	368421	9	0	0
T2	16071	993	0	0
T3	63667	97	0	0
T7	120068	193	0	0
T8	1819	14	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	312	0	0
T12	13528	219	0	0
T13	59415	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3065368	0	0
T1	368421	1344	0	0
T2	16071	39	0	0
T3	63667	687	0	0
T7	120068	1237	0	0
T8	1819	15	0	0
T9	65208	930	0	0
T10	1833	8	0	0
T11	34688	320	0	0
T12	13528	213	0	0
T13	59415	890	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217547	0	0
T1	368421	9	0	0
T2	16071	993	0	0
T3	63667	97	0	0
T7	120068	193	0	0
T8	1819	14	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	312	0	0
T12	13528	219	0	0
T13	59415	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217547	0	0
T1	368421	9	0	0
T2	16071	993	0	0
T3	63667	97	0	0
T7	120068	193	0	0
T8	1819	14	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	312	0	0
T12	13528	219	0	0
T13	59415	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	566544	0	0
T1	368421	324	0	0
T2	16071	1948	0	0
T3	63667	99	0	0
T7	120068	213	0	0
T8	1819	14	0	0
T9	65208	156	0	0
T10	1833	7	0	0
T11	34688	321	0	0
T12	13528	226	0	0
T13	59415	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217547	0	0
T1	368421	9	0	0
T2	16071	993	0	0
T3	63667	97	0	0
T7	120068	193	0	0
T8	1819	14	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	312	0	0
T12	13528	219	0	0
T13	59415	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T11
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	225857	0	0
GntImpliesValid_A	424342108	225857	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	225857	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3114026	0	0
ReadyAndValidImplyGrant_A	424342108	225857	0	0
ReqAndReadyImplyGrant_A	424342108	225857	0	0
ReqImpliesValid_A	424342108	648548	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	225857	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	225857	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	216	0	0
T7	120068	193	0	0
T8	1819	10	0	0
T9	65208	140	0	0
T10	1833	10	0	0
T11	34688	293	0	0
T12	13528	243	0	0
T13	59415	124	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	225857	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	216	0	0
T7	120068	193	0	0
T8	1819	10	0	0
T9	65208	140	0	0
T10	1833	10	0	0
T11	34688	293	0	0
T12	13528	243	0	0
T13	59415	124	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	225857	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	216	0	0
T7	120068	193	0	0
T8	1819	10	0	0
T9	65208	140	0	0
T10	1833	10	0	0
T11	34688	293	0	0
T12	13528	243	0	0
T13	59415	124	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3114026	0	0
T1	368421	2229	0	0
T2	16071	1	0	0
T3	63667	608	0	0
T7	120068	1425	0	0
T8	1819	11	0	0
T9	65208	998	0	0
T10	1833	11	0	0
T11	34688	303	0	0
T12	13528	233	0	0
T13	59415	896	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	225857	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	216	0	0
T7	120068	193	0	0
T8	1819	10	0	0
T9	65208	140	0	0
T10	1833	10	0	0
T11	34688	293	0	0
T12	13528	243	0	0
T13	59415	124	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	225857	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	216	0	0
T7	120068	193	0	0
T8	1819	10	0	0
T9	65208	140	0	0
T10	1833	10	0	0
T11	34688	293	0	0
T12	13528	243	0	0
T13	59415	124	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	648548	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	229	0	0
T7	120068	202	0	0
T8	1819	10	0	0
T9	65208	179	0	0
T10	1833	10	0	0
T11	34688	299	0	0
T12	13528	254	0	0
T13	59415	169	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	225857	0	0
T1	368421	4	0	0
T2	16071	0	0	0
T3	63667	89	0	0
T4	0	216	0	0
T7	120068	193	0	0
T8	1819	10	0	0
T9	65208	140	0	0
T10	1833	10	0	0
T11	34688	293	0	0
T12	13528	243	0	0
T13	59415	124	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	221016	0	0
GntImpliesValid_A	424342108	221016	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	221016	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3036741	0	0
ReadyAndValidImplyGrant_A	424342108	221016	0	0
ReqAndReadyImplyGrant_A	424342108	221016	0	0
ReqImpliesValid_A	424342108	606145	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	221016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	221016	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	192	0	0
T7	120068	175	0	0
T8	1819	8	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	300	0	0
T12	13528	219	0	0
T13	59415	95	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	221016	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	192	0	0
T7	120068	175	0	0
T8	1819	8	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	300	0	0
T12	13528	219	0	0
T13	59415	95	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	221016	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	192	0	0
T7	120068	175	0	0
T8	1819	8	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	300	0	0
T12	13528	219	0	0
T13	59415	95	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3036741	0	0
T1	368421	3124	0	0
T2	16071	1	0	0
T3	63667	787	0	0
T7	120068	1359	0	0
T8	1819	9	0	0
T9	65208	889	0	0
T10	1833	8	0	0
T11	34688	313	0	0
T12	13528	208	0	0
T13	59415	659	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	221016	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	192	0	0
T7	120068	175	0	0
T8	1819	8	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	300	0	0
T12	13528	219	0	0
T13	59415	95	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	221016	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	192	0	0
T7	120068	175	0	0
T8	1819	8	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	300	0	0
T12	13528	219	0	0
T13	59415	95	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	606145	0	0
T1	368421	503	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	202	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	172	0	0
T10	1833	7	0	0
T11	34688	303	0	0
T12	13528	231	0	0
T13	59415	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	221016	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	192	0	0
T7	120068	175	0	0
T8	1819	8	0	0
T9	65208	123	0	0
T10	1833	7	0	0
T11	34688	300	0	0
T12	13528	219	0	0
T13	59415	95	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	220760	0	0
GntImpliesValid_A	424342108	220760	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	220760	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	2997961	0	0
ReadyAndValidImplyGrant_A	424342108	220760	0	0
ReqAndReadyImplyGrant_A	424342108	220760	0	0
ReqImpliesValid_A	424342108	589655	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	220760	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220760	0	0
T1	368421	21	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	202	0	0
T7	120068	185	0	0
T8	1819	9	0	0
T9	65208	136	0	0
T10	1833	10	0	0
T11	34688	301	0	0
T12	13528	218	0	0
T13	59415	107	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220760	0	0
T1	368421	21	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	202	0	0
T7	120068	185	0	0
T8	1819	9	0	0
T9	65208	136	0	0
T10	1833	10	0	0
T11	34688	301	0	0
T12	13528	218	0	0
T13	59415	107	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220760	0	0
T1	368421	21	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	202	0	0
T7	120068	185	0	0
T8	1819	9	0	0
T9	65208	136	0	0
T10	1833	10	0	0
T11	34688	301	0	0
T12	13528	218	0	0
T13	59415	107	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2997961	0	0
T1	368421	5320	0	0
T2	16071	1	0	0
T3	63667	817	0	0
T7	120068	1393	0	0
T8	1819	10	0	0
T9	65208	1116	0	0
T10	1833	11	0	0
T11	34688	314	0	0
T12	13528	207	0	0
T13	59415	799	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220760	0	0
T1	368421	21	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	202	0	0
T7	120068	185	0	0
T8	1819	9	0	0
T9	65208	136	0	0
T10	1833	10	0	0
T11	34688	301	0	0
T12	13528	218	0	0
T13	59415	107	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220760	0	0
T1	368421	21	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	202	0	0
T7	120068	185	0	0
T8	1819	9	0	0
T9	65208	136	0	0
T10	1833	10	0	0
T11	34688	301	0	0
T12	13528	218	0	0
T13	59415	107	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	589655	0	0
T1	368421	59	0	0
T2	16071	0	0	0
T3	63667	120	0	0
T4	0	217	0	0
T7	120068	190	0	0
T8	1819	9	0	0
T9	65208	172	0	0
T10	1833	10	0	0
T11	34688	305	0	0
T12	13528	230	0	0
T13	59415	113	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220760	0	0
T1	368421	21	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	202	0	0
T7	120068	185	0	0
T8	1819	9	0	0
T9	65208	136	0	0
T10	1833	10	0	0
T11	34688	301	0	0
T12	13528	218	0	0
T13	59415	107	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	230512	0	0
GntImpliesValid_A	424342108	230512	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	230512	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3052206	0	0
ReadyAndValidImplyGrant_A	424342108	230512	0	0
ReqAndReadyImplyGrant_A	424342108	230512	0	0
ReqImpliesValid_A	424342108	641843	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	230512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230512	0	0
T1	368421	11	0	0
T2	16071	450	0	0
T3	63667	94	0	0
T7	120068	214	0	0
T8	1819	9	0	0
T9	65208	113	0	0
T10	1833	8	0	0
T11	34688	1767	0	0
T12	13528	261	0	0
T13	59415	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230512	0	0
T1	368421	11	0	0
T2	16071	450	0	0
T3	63667	94	0	0
T7	120068	214	0	0
T8	1819	9	0	0
T9	65208	113	0	0
T10	1833	8	0	0
T11	34688	1767	0	0
T12	13528	261	0	0
T13	59415	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230512	0	0
T1	368421	11	0	0
T2	16071	450	0	0
T3	63667	94	0	0
T7	120068	214	0	0
T8	1819	9	0	0
T9	65208	113	0	0
T10	1833	8	0	0
T11	34688	1767	0	0
T12	13528	261	0	0
T13	59415	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3052206	0	0
T1	368421	2726	0	0
T2	16071	5	0	0
T3	63667	676	0	0
T7	120068	1564	0	0
T8	1819	10	0	0
T9	65208	822	0	0
T10	1833	9	0	0
T11	34688	757	0	0
T12	13528	251	0	0
T13	59415	828	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230512	0	0
T1	368421	11	0	0
T2	16071	450	0	0
T3	63667	94	0	0
T7	120068	214	0	0
T8	1819	9	0	0
T9	65208	113	0	0
T10	1833	8	0	0
T11	34688	1767	0	0
T12	13528	261	0	0
T13	59415	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230512	0	0
T1	368421	11	0	0
T2	16071	450	0	0
T3	63667	94	0	0
T7	120068	214	0	0
T8	1819	9	0	0
T9	65208	113	0	0
T10	1833	8	0	0
T11	34688	1767	0	0
T12	13528	261	0	0
T13	59415	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	641843	0	0
T1	368421	133	0	0
T2	16071	896	0	0
T3	63667	94	0	0
T7	120068	231	0	0
T8	1819	9	0	0
T9	65208	140	0	0
T10	1833	8	0	0
T11	34688	2793	0	0
T12	13528	272	0	0
T13	59415	133	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230512	0	0
T1	368421	11	0	0
T2	16071	450	0	0
T3	63667	94	0	0
T7	120068	214	0	0
T8	1819	9	0	0
T9	65208	113	0	0
T10	1833	8	0	0
T11	34688	1767	0	0
T12	13528	261	0	0
T13	59415	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	230815	0	0
GntImpliesValid_A	424342108	230815	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	230815	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3052308	0	0
ReadyAndValidImplyGrant_A	424342108	230815	0	0
ReqAndReadyImplyGrant_A	424342108	230815	0	0
ReqImpliesValid_A	424342108	650208	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	230815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230815	0	0
T1	368421	11	0	0
T2	16071	530	0	0
T3	63667	97	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	145	0	0
T10	1833	10	0	0
T11	34688	703	0	0
T12	13528	239	0	0
T13	59415	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230815	0	0
T1	368421	11	0	0
T2	16071	530	0	0
T3	63667	97	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	145	0	0
T10	1833	10	0	0
T11	34688	703	0	0
T12	13528	239	0	0
T13	59415	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230815	0	0
T1	368421	11	0	0
T2	16071	530	0	0
T3	63667	97	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	145	0	0
T10	1833	10	0	0
T11	34688	703	0	0
T12	13528	239	0	0
T13	59415	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3052308	0	0
T1	368421	3810	0	0
T2	16071	2	0	0
T3	63667	812	0	0
T7	120068	1603	0	0
T8	1819	10	0	0
T9	65208	1085	0	0
T10	1833	11	0	0
T11	34688	658	0	0
T12	13528	232	0	0
T13	59415	1000	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230815	0	0
T1	368421	11	0	0
T2	16071	530	0	0
T3	63667	97	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	145	0	0
T10	1833	10	0	0
T11	34688	703	0	0
T12	13528	239	0	0
T13	59415	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230815	0	0
T1	368421	11	0	0
T2	16071	530	0	0
T3	63667	97	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	145	0	0
T10	1833	10	0	0
T11	34688	703	0	0
T12	13528	239	0	0
T13	59415	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	650208	0	0
T1	368421	118	0	0
T2	16071	1059	0	0
T3	63667	103	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	180	0	0
T10	1833	10	0	0
T11	34688	764	0	0
T12	13528	247	0	0
T13	59415	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	230815	0	0
T1	368421	11	0	0
T2	16071	530	0	0
T3	63667	97	0	0
T7	120068	211	0	0
T8	1819	9	0	0
T9	65208	145	0	0
T10	1833	10	0	0
T11	34688	703	0	0
T12	13528	239	0	0
T13	59415	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	220603	0	0
GntImpliesValid_A	424342108	220603	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	220603	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3034541	0	0
ReadyAndValidImplyGrant_A	424342108	220603	0	0
ReqAndReadyImplyGrant_A	424342108	220603	0	0
ReqImpliesValid_A	424342108	637148	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	220603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220603	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	103	0	0
T4	0	186	0	0
T7	120068	183	0	0
T8	1819	20	0	0
T9	65208	111	0	0
T10	1833	8	0	0
T11	34688	309	0	0
T12	13528	249	0	0
T13	59415	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220603	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	103	0	0
T4	0	186	0	0
T7	120068	183	0	0
T8	1819	20	0	0
T9	65208	111	0	0
T10	1833	8	0	0
T11	34688	309	0	0
T12	13528	249	0	0
T13	59415	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220603	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	103	0	0
T4	0	186	0	0
T7	120068	183	0	0
T8	1819	20	0	0
T9	65208	111	0	0
T10	1833	8	0	0
T11	34688	309	0	0
T12	13528	249	0	0
T13	59415	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3034541	0	0
T1	368421	3763	0	0
T2	16071	1	0	0
T3	63667	791	0	0
T7	120068	1436	0	0
T8	1819	19	0	0
T9	65208	931	0	0
T10	1833	9	0	0
T11	34688	320	0	0
T12	13528	241	0	0
T13	59415	911	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220603	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	103	0	0
T4	0	186	0	0
T7	120068	183	0	0
T8	1819	20	0	0
T9	65208	111	0	0
T10	1833	8	0	0
T11	34688	309	0	0
T12	13528	249	0	0
T13	59415	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220603	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	103	0	0
T4	0	186	0	0
T7	120068	183	0	0
T8	1819	20	0	0
T9	65208	111	0	0
T10	1833	8	0	0
T11	34688	309	0	0
T12	13528	249	0	0
T13	59415	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	637148	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	119	0	0
T4	0	201	0	0
T7	120068	183	0	0
T8	1819	22	0	0
T9	65208	160	0	0
T10	1833	8	0	0
T11	34688	315	0	0
T12	13528	258	0	0
T13	59415	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	220603	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	103	0	0
T4	0	186	0	0
T7	120068	183	0	0
T8	1819	20	0	0
T9	65208	111	0	0
T10	1833	8	0	0
T11	34688	309	0	0
T12	13528	249	0	0
T13	59415	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	241211	0	0
GntImpliesValid_A	424342108	241211	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	241211	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3060949	0	0
ReadyAndValidImplyGrant_A	424342108	241211	0	0
ReqAndReadyImplyGrant_A	424342108	241211	0	0
ReqImpliesValid_A	424342108	628061	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	241211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	241211	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	227	0	0
T7	120068	174	0	0
T8	1819	4	0	0
T9	65208	231	0	0
T10	1833	11	0	0
T11	34688	850	0	0
T12	13528	216	0	0
T13	59415	185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	241211	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	227	0	0
T7	120068	174	0	0
T8	1819	4	0	0
T9	65208	231	0	0
T10	1833	11	0	0
T11	34688	850	0	0
T12	13528	216	0	0
T13	59415	185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	241211	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	227	0	0
T7	120068	174	0	0
T8	1819	4	0	0
T9	65208	231	0	0
T10	1833	11	0	0
T11	34688	850	0	0
T12	13528	216	0	0
T13	59415	185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3060949	0	0
T1	368421	3784	0	0
T2	16071	1	0	0
T3	63667	718	0	0
T7	120068	1424	0	0
T8	1819	5	0	0
T9	65208	1723	0	0
T10	1833	12	0	0
T11	34688	416	0	0
T12	13528	202	0	0
T13	59415	1395	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	241211	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	227	0	0
T7	120068	174	0	0
T8	1819	4	0	0
T9	65208	231	0	0
T10	1833	11	0	0
T11	34688	850	0	0
T12	13528	216	0	0
T13	59415	185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	241211	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	227	0	0
T7	120068	174	0	0
T8	1819	4	0	0
T9	65208	231	0	0
T10	1833	11	0	0
T11	34688	850	0	0
T12	13528	216	0	0
T13	59415	185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	628061	0	0
T1	368421	516	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	249	0	0
T7	120068	175	0	0
T8	1819	4	0	0
T9	65208	308	0	0
T10	1833	11	0	0
T11	34688	1301	0	0
T12	13528	231	0	0
T13	59415	217	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	241211	0	0
T1	368421	11	0	0
T2	16071	0	0	0
T3	63667	100	0	0
T4	0	227	0	0
T7	120068	174	0	0
T8	1819	4	0	0
T9	65208	231	0	0
T10	1833	11	0	0
T11	34688	850	0	0
T12	13528	216	0	0
T13	59415	185	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	215326	0	0
GntImpliesValid_A	424342108	215326	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	215326	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3040764	0	0
ReadyAndValidImplyGrant_A	424342108	215326	0	0
ReqAndReadyImplyGrant_A	424342108	215326	0	0
ReqImpliesValid_A	424342108	575947	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	215326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	215326	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	214	0	0
T7	120068	197	0	0
T8	1819	8	0	0
T9	65208	152	0	0
T10	1833	8	0	0
T11	34688	317	0	0
T12	13528	239	0	0
T13	59415	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	215326	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	214	0	0
T7	120068	197	0	0
T8	1819	8	0	0
T9	65208	152	0	0
T10	1833	8	0	0
T11	34688	317	0	0
T12	13528	239	0	0
T13	59415	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	215326	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	214	0	0
T7	120068	197	0	0
T8	1819	8	0	0
T9	65208	152	0	0
T10	1833	8	0	0
T11	34688	317	0	0
T12	13528	239	0	0
T13	59415	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3040764	0	0
T1	368421	2236	0	0
T2	16071	1	0	0
T3	63667	552	0	0
T7	120068	1503	0	0
T8	1819	9	0	0
T9	65208	1116	0	0
T10	1833	9	0	0
T11	34688	328	0	0
T12	13528	228	0	0
T13	59415	796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	215326	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	214	0	0
T7	120068	197	0	0
T8	1819	8	0	0
T9	65208	152	0	0
T10	1833	8	0	0
T11	34688	317	0	0
T12	13528	239	0	0
T13	59415	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	215326	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	214	0	0
T7	120068	197	0	0
T8	1819	8	0	0
T9	65208	152	0	0
T10	1833	8	0	0
T11	34688	317	0	0
T12	13528	239	0	0
T13	59415	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	575947	0	0
T1	368421	150	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	221	0	0
T7	120068	200	0	0
T8	1819	8	0	0
T9	65208	209	0	0
T10	1833	8	0	0
T11	34688	323	0	0
T12	13528	251	0	0
T13	59415	125	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	215326	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	85	0	0
T4	0	214	0	0
T7	120068	197	0	0
T8	1819	8	0	0
T9	65208	152	0	0
T10	1833	8	0	0
T11	34688	317	0	0
T12	13528	239	0	0
T13	59415	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	224959	0	0
GntImpliesValid_A	424342108	224959	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	224959	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	2961640	0	0
ReadyAndValidImplyGrant_A	424342108	224959	0	0
ReqAndReadyImplyGrant_A	424342108	224959	0	0
ReqImpliesValid_A	424342108	615851	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	224959	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224959	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	221	0	0
T7	120068	204	0	0
T8	1819	7	0	0
T9	65208	126	0	0
T10	1833	10	0	0
T11	34688	322	0	0
T12	13528	223	0	0
T13	59415	143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224959	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	221	0	0
T7	120068	204	0	0
T8	1819	7	0	0
T9	65208	126	0	0
T10	1833	10	0	0
T11	34688	322	0	0
T12	13528	223	0	0
T13	59415	143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224959	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	221	0	0
T7	120068	204	0	0
T8	1819	7	0	0
T9	65208	126	0	0
T10	1833	10	0	0
T11	34688	322	0	0
T12	13528	223	0	0
T13	59415	143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2961640	0	0
T1	368421	3171	0	0
T2	16071	1	0	0
T3	63667	854	0	0
T7	120068	1542	0	0
T8	1819	8	0	0
T9	65208	984	0	0
T10	1833	11	0	0
T11	34688	332	0	0
T12	13528	218	0	0
T13	59415	997	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224959	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	221	0	0
T7	120068	204	0	0
T8	1819	7	0	0
T9	65208	126	0	0
T10	1833	10	0	0
T11	34688	322	0	0
T12	13528	223	0	0
T13	59415	143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224959	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	221	0	0
T7	120068	204	0	0
T8	1819	7	0	0
T9	65208	126	0	0
T10	1833	10	0	0
T11	34688	322	0	0
T12	13528	223	0	0
T13	59415	143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	615851	0	0
T1	368421	97	0	0
T2	16071	0	0	0
T3	63667	130	0	0
T4	0	234	0	0
T7	120068	212	0	0
T8	1819	7	0	0
T9	65208	183	0	0
T10	1833	10	0	0
T11	34688	329	0	0
T12	13528	229	0	0
T13	59415	165	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	224959	0	0
T1	368421	10	0	0
T2	16071	0	0	0
T3	63667	108	0	0
T4	0	221	0	0
T7	120068	204	0	0
T8	1819	7	0	0
T9	65208	126	0	0
T10	1833	10	0	0
T11	34688	322	0	0
T12	13528	223	0	0
T13	59415	143	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	227667	0	0
GntImpliesValid_A	424342108	227667	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	227667	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	2997839	0	0
ReadyAndValidImplyGrant_A	424342108	227667	0	0
ReqAndReadyImplyGrant_A	424342108	227667	0	0
ReqImpliesValid_A	424342108	637171	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	227667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	227667	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	101	0	0
T4	0	232	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	128	0	0
T10	1833	11	0	0
T11	34688	1325	0	0
T12	13528	231	0	0
T13	59415	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	227667	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	101	0	0
T4	0	232	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	128	0	0
T10	1833	11	0	0
T11	34688	1325	0	0
T12	13528	231	0	0
T13	59415	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	227667	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	101	0	0
T4	0	232	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	128	0	0
T10	1833	11	0	0
T11	34688	1325	0	0
T12	13528	231	0	0
T13	59415	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2997839	0	0
T1	368421	2612	0	0
T2	16071	1	0	0
T3	63667	727	0	0
T7	120068	1477	0	0
T8	1819	10	0	0
T9	65208	933	0	0
T10	1833	11	0	0
T11	34688	1124	0	0
T12	13528	218	0	0
T13	59415	964	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	227667	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	101	0	0
T4	0	232	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	128	0	0
T10	1833	11	0	0
T11	34688	1325	0	0
T12	13528	231	0	0
T13	59415	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	227667	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	101	0	0
T4	0	232	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	128	0	0
T10	1833	11	0	0
T11	34688	1325	0	0
T12	13528	231	0	0
T13	59415	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	637171	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	105	0	0
T4	0	245	0	0
T7	120068	198	0	0
T8	1819	11	0	0
T9	65208	219	0	0
T10	1833	12	0	0
T11	34688	1543	0	0
T12	13528	245	0	0
T13	59415	177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	227667	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	101	0	0
T4	0	232	0	0
T7	120068	190	0	0
T8	1819	10	0	0
T9	65208	128	0	0
T10	1833	11	0	0
T11	34688	1325	0	0
T12	13528	231	0	0
T13	59415	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	217486	0	0
GntImpliesValid_A	424342108	217486	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	217486	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	3003753	0	0
ReadyAndValidImplyGrant_A	424342108	217486	0	0
ReqAndReadyImplyGrant_A	424342108	217486	0	0
ReqImpliesValid_A	424342108	605447	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	217486	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217486	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	206	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	124	0	0
T10	1833	10	0	0
T11	34688	312	0	0
T12	13528	234	0	0
T13	59415	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217486	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	206	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	124	0	0
T10	1833	10	0	0
T11	34688	312	0	0
T12	13528	234	0	0
T13	59415	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217486	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	206	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	124	0	0
T10	1833	10	0	0
T11	34688	312	0	0
T12	13528	234	0	0
T13	59415	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	3003753	0	0
T1	368421	1454	0	0
T2	16071	1	0	0
T3	63667	693	0	0
T7	120068	1364	0	0
T8	1819	8	0	0
T9	65208	840	0	0
T10	1833	11	0	0
T11	34688	327	0	0
T12	13528	223	0	0
T13	59415	1036	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217486	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	206	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	124	0	0
T10	1833	10	0	0
T11	34688	312	0	0
T12	13528	234	0	0
T13	59415	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217486	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	206	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	124	0	0
T10	1833	10	0	0
T11	34688	312	0	0
T12	13528	234	0	0
T13	59415	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	605447	0	0
T1	368421	480	0	0
T2	16071	0	0	0
T3	63667	104	0	0
T4	0	216	0	0
T7	120068	222	0	0
T8	1819	9	0	0
T9	65208	156	0	0
T10	1833	10	0	0
T11	34688	314	0	0
T12	13528	246	0	0
T13	59415	169	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	217486	0	0
T1	368421	8	0	0
T2	16071	0	0	0
T3	63667	95	0	0
T4	0	206	0	0
T7	120068	182	0	0
T8	1819	8	0	0
T9	65208	124	0	0
T10	1833	10	0	0
T11	34688	312	0	0
T12	13528	234	0	0
T13	59415	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T11
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	214848	0	0
GntImpliesValid_A	424342108	214848	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	214848	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	2997802	0	0
ReadyAndValidImplyGrant_A	424342108	214848	0	0
ReqAndReadyImplyGrant_A	424342108	214848	0	0
ReqImpliesValid_A	424342108	589948	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	0	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	214848	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214848	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	214	0	0
T7	120068	182	0	0
T8	1819	10	0	0
T9	65208	114	0	0
T10	1833	10	0	0
T11	34688	280	0	0
T12	13528	245	0	0
T13	59415	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214848	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	214	0	0
T7	120068	182	0	0
T8	1819	10	0	0
T9	65208	114	0	0
T10	1833	10	0	0
T11	34688	280	0	0
T12	13528	245	0	0
T13	59415	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214848	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	214	0	0
T7	120068	182	0	0
T8	1819	10	0	0
T9	65208	114	0	0
T10	1833	10	0	0
T11	34688	280	0	0
T12	13528	245	0	0
T13	59415	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2997802	0	0
T1	368421	1840	0	0
T2	16071	1	0	0
T3	63667	944	0	0
T7	120068	1353	0	0
T8	1819	11	0	0
T9	65208	834	0	0
T10	1833	11	0	0
T11	34688	290	0	0
T12	13528	231	0	0
T13	59415	851	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214848	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	214	0	0
T7	120068	182	0	0
T8	1819	10	0	0
T9	65208	114	0	0
T10	1833	10	0	0
T11	34688	280	0	0
T12	13528	245	0	0
T13	59415	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214848	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	214	0	0
T7	120068	182	0	0
T8	1819	10	0	0
T9	65208	114	0	0
T10	1833	10	0	0
T11	34688	280	0	0
T12	13528	245	0	0
T13	59415	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	589948	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	232	0	0
T7	120068	183	0	0
T8	1819	10	0	0
T9	65208	132	0	0
T10	1833	10	0	0
T11	34688	287	0	0
T12	13528	260	0	0
T13	59415	141	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	214848	0	0
T1	368421	7	0	0
T2	16071	0	0	0
T3	63667	110	0	0
T4	0	214	0	0
T7	120068	182	0	0
T8	1819	10	0	0
T9	65208	114	0	0
T10	1833	10	0	0
T11	34688	280	0	0
T12	13528	245	0	0
T13	59415	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	884580	0	0
GntImpliesValid_A	424342108	884580	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	884580	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	11385145	0	0
ReadyAndValidImplyGrant_A	424342108	884580	0	0
ReqAndReadyImplyGrant_A	424342108	884580	0	0
ReqImpliesValid_A	424342108	2245619	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	18859	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	884580	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	884580	0	0
T1	368421	31	0	0
T2	16071	518	0	0
T3	63667	375	0	0
T7	120068	747	0	0
T8	1819	51	0	0
T9	65208	508	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	501	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	884580	0	0
T1	368421	31	0	0
T2	16071	518	0	0
T3	63667	375	0	0
T7	120068	747	0	0
T8	1819	51	0	0
T9	65208	508	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	501	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	884580	0	0
T1	368421	31	0	0
T2	16071	518	0	0
T3	63667	375	0	0
T7	120068	747	0	0
T8	1819	51	0	0
T9	65208	508	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	501	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	11385145	0	0
T1	368421	9885	0	0
T2	16071	1	0	0
T3	63667	2568	0	0
T7	120068	5019	0	0
T8	1819	1	0	0
T9	65208	3329	0	0
T10	1833	1	0	0
T11	34688	17	0	0
T12	13528	1	0	0
T13	59415	3302	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	884580	0	0
T1	368421	31	0	0
T2	16071	518	0	0
T3	63667	375	0	0
T7	120068	747	0	0
T8	1819	51	0	0
T9	65208	508	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	501	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	884580	0	0
T1	368421	31	0	0
T2	16071	518	0	0
T3	63667	375	0	0
T7	120068	747	0	0
T8	1819	51	0	0
T9	65208	508	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	501	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	2245619	0	0
T1	368421	714	0	0
T2	16071	518	0	0
T3	63667	447	0	0
T7	120068	919	0	0
T8	1819	51	0	0
T9	65208	735	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	753	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	18859	0	900
T4	19438	11	0	1
T5	69187	0	0	1
T11	34688	23	0	1
T12	13528	17	0	1
T13	59415	0	0	1
T14	118382	0	0	1
T15	3546	2	0	1
T16	19505	4	0	1
T18	0	2	0	0
T19	0	48	0	0
T20	0	2	0	0
T21	0	296	0	0
T22	0	15	0	0
T23	9931	0	0	1
T24	388042	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	884580	0	0
T1	368421	31	0	0
T2	16071	518	0	0
T3	63667	375	0	0
T7	120068	747	0	0
T8	1819	51	0	0
T9	65208	508	0	0
T10	1833	35	0	0
T11	34688	2004	0	0
T12	13528	969	0	0
T13	59415	501	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424342108	424220884	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424342108	872407	0	0
GntImpliesValid_A	424342108	872407	0	0
GrantKnown_A	424342108	424220884	0	0
IdxKnown_A	424342108	424220884	0	0
IndexIsCorrect_A	424342108	872407	0	0
LockArbDecision_A	424342108	0	0	0
NoReadyValidNoGrant_A	424342108	356751563	0	0
ReadyAndValidImplyGrant_A	424342108	872407	0	0
ReqAndReadyImplyGrant_A	424342108	872407	0	0
ReqImpliesValid_A	424342108	13378499	0	0
ReqStaysHighUntilGranted0_M	424342108	0	0	0
RoundRobin_A	424342108	23820	0	900
ValidKnown_A	424342108	424220884	0	0
gen_data_port_assertion.DataFlow_A	424342108	872407	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	872407	0	0
T1	368421	34	0	0
T2	16071	504	0	0
T3	63667	425	0	0
T7	120068	746	0	0
T8	1819	54	0	0
T9	65208	500	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	483	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	872407	0	0
T1	368421	34	0	0
T2	16071	504	0	0
T3	63667	425	0	0
T7	120068	746	0	0
T8	1819	54	0	0
T9	65208	500	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	483	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	872407	0	0
T1	368421	34	0	0
T2	16071	504	0	0
T3	63667	425	0	0
T7	120068	746	0	0
T8	1819	54	0	0
T9	65208	500	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	483	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	356751563	0	0
T1	368421	357272	0	0
T2	16071	1	0	0
T3	63667	53545	0	0
T7	120068	104107	0	0
T8	1819	1	0	0
T9	65208	55949	0	0
T10	1833	1	0	0
T11	34688	1	0	0
T12	13528	1	0	0
T13	59415	50676	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	872407	0	0
T1	368421	34	0	0
T2	16071	504	0	0
T3	63667	425	0	0
T7	120068	746	0	0
T8	1819	54	0	0
T9	65208	500	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	483	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	872407	0	0
T1	368421	34	0	0
T2	16071	504	0	0
T3	63667	425	0	0
T7	120068	746	0	0
T8	1819	54	0	0
T9	65208	500	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	483	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	13378499	0	0
T1	368421	10413	0	0
T2	16071	504	0	0
T3	63667	3282	0	0
T7	120068	5737	0	0
T8	1819	54	0	0
T9	65208	3869	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	3793	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	23820	0	900
T4	19438	9	0	1
T5	69187	0	0	1
T11	34688	14	0	1
T12	13528	16	0	1
T13	59415	0	0	1
T14	118382	1	0	1
T15	3546	1	0	1
T16	19505	9	0	1
T17	0	21	0	0
T18	0	3	0	0
T19	0	49	0	0
T20	0	3	0	0
T23	9931	0	0	1
T24	388042	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	424220884	0	0
T1	368421	368396	0	0
T2	16071	16053	0	0
T3	63667	63632	0	0
T7	120068	120047	0	0
T8	1819	1781	0	0
T9	65208	65175	0	0
T10	1833	1808	0	0
T11	34688	33381	0	0
T12	13528	13490	0	0
T13	59415	59392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424342108	872407	0	0
T1	368421	34	0	0
T2	16071	504	0	0
T3	63667	425	0	0
T7	120068	746	0	0
T8	1819	54	0	0
T9	65208	500	0	0
T10	1833	48	0	0
T11	34688	2021	0	0
T12	13528	855	0	0
T13	59415	483	0	0