Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1474248 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 234179 1 T1 640 T2 14 T3 125


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 580748 1 T1 1577 T2 33 T3 314
values[0x0] 547606 1 T1 1514 T2 38 T3 322
values[0x1] 580073 1 T1 1577 T2 34 T3 281


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1138892 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 569535 1 T1 1533 T2 34 T3 301


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26662 1 T1 75 T3 18 T7 19
valid_sources[0x01] 25852 1 T1 77 T3 28 T9 64
valid_sources[0x02] 26447 1 T1 100 T3 5 T7 32
valid_sources[0x03] 26678 1 T1 96 T7 16 T9 55
valid_sources[0x04] 27024 1 T1 103 T2 1 T3 18
valid_sources[0x05] 26072 1 T1 91 T3 6 T7 16
valid_sources[0x06] 27070 1 T1 67 T7 15 T9 51
valid_sources[0x07] 26680 1 T1 54 T3 28 T7 6
valid_sources[0x08] 26264 1 T1 76 T2 4 T7 37
valid_sources[0x09] 25836 1 T1 99 T2 4 T3 20
valid_sources[0x0a] 26590 1 T1 48 T3 7 T7 10
valid_sources[0x0b] 26228 1 T1 60 T7 20 T9 50
valid_sources[0x0c] 26346 1 T1 51 T7 60 T9 51
valid_sources[0x0d] 26492 1 T1 55 T9 54 T4 32
valid_sources[0x0e] 25866 1 T1 76 T2 6 T7 50
valid_sources[0x0f] 26675 1 T1 59 T3 10 T7 5
valid_sources[0x10] 26654 1 T1 46 T3 7 T7 11
valid_sources[0x11] 26703 1 T1 103 T7 46 T9 41
valid_sources[0x12] 26461 1 T1 92 T2 19 T3 38
valid_sources[0x13] 26719 1 T1 91 T3 15 T7 42
valid_sources[0x14] 26563 1 T1 60 T3 26 T7 10
valid_sources[0x15] 26422 1 T1 86 T7 38 T9 49
valid_sources[0x16] 26503 1 T1 80 T7 20 T9 53
valid_sources[0x17] 26477 1 T1 69 T3 34 T7 34
valid_sources[0x18] 26962 1 T1 68 T3 7 T7 30
valid_sources[0x19] 26380 1 T1 52 T3 14 T7 13
valid_sources[0x1a] 27807 1 T1 55 T7 22 T9 52
valid_sources[0x1b] 25769 1 T1 62 T3 38 T7 53
valid_sources[0x1c] 27727 1 T1 80 T3 19 T9 64
valid_sources[0x1d] 26161 1 T1 73 T3 39 T7 17
valid_sources[0x1e] 27825 1 T1 42 T3 87 T7 50
valid_sources[0x1f] 26502 1 T1 75 T3 16 T7 8
valid_sources[0x20] 26972 1 T1 62 T7 7 T9 55


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24760 1 T1 65 T3 13 T7 18
values[0x0] all_enables biggest_size 185112 1 T1 508 T2 13 T3 105
values[0x1] all_enables biggest_size 24307 1 T1 67 T2 1 T3 7


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1488757 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 241832 1 T1 652 T2 10 T3 128


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 592272 1 T1 1542 T2 32 T3 321
values[0x0] 545575 1 T1 1522 T2 33 T3 292
values[0x1] 592742 1 T1 1556 T2 35 T3 303


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1142551 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 588038 1 T1 1551 T2 33 T3 306


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26858 1 T1 58 T2 3 T3 7
valid_sources[0x01] 26766 1 T1 78 T2 2 T3 43
valid_sources[0x02] 26747 1 T1 79 T2 2 T3 10
valid_sources[0x03] 27262 1 T1 89 T2 3 T7 5
valid_sources[0x04] 27269 1 T1 68 T2 3 T3 20
valid_sources[0x05] 26759 1 T1 64 T3 11 T7 5
valid_sources[0x06] 26295 1 T1 78 T2 2 T7 24
valid_sources[0x07] 26617 1 T1 76 T2 3 T3 27
valid_sources[0x08] 27004 1 T1 78 T7 53 T8 7
valid_sources[0x09] 27254 1 T1 69 T2 1 T3 12
valid_sources[0x0a] 26812 1 T1 69 T3 6 T7 5
valid_sources[0x0b] 26400 1 T1 70 T7 26 T8 8
valid_sources[0x0c] 27573 1 T1 57 T7 62 T8 8
valid_sources[0x0d] 26909 1 T1 75 T8 3 T9 53
valid_sources[0x0e] 26275 1 T1 74 T2 3 T7 45
valid_sources[0x0f] 27491 1 T1 81 T3 13 T7 8
valid_sources[0x10] 26448 1 T1 65 T3 20 T7 13
valid_sources[0x11] 27260 1 T1 67 T2 2 T7 49
valid_sources[0x12] 27511 1 T1 74 T2 1 T3 35
valid_sources[0x13] 27247 1 T1 92 T2 2 T3 16
valid_sources[0x14] 26843 1 T1 86 T3 30 T7 15
valid_sources[0x15] 26759 1 T1 87 T2 1 T7 57
valid_sources[0x16] 27600 1 T1 69 T2 2 T7 17
valid_sources[0x17] 27329 1 T1 70 T3 52 T7 22
valid_sources[0x18] 26814 1 T1 85 T3 15 T7 37
valid_sources[0x19] 27089 1 T1 70 T2 2 T3 8
valid_sources[0x1a] 27226 1 T1 66 T7 20 T9 54
valid_sources[0x1b] 26964 1 T1 83 T2 2 T3 41
valid_sources[0x1c] 26748 1 T1 69 T3 15 T8 5
valid_sources[0x1d] 27157 1 T1 73 T2 1 T3 48
valid_sources[0x1e] 27749 1 T1 81 T2 3 T3 50
valid_sources[0x1f] 26715 1 T1 73 T2 5 T3 13
valid_sources[0x20] 27337 1 T1 80 T2 2 T7 15


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25230 1 T1 55 T2 1 T3 11
values[0x0] all_enables biggest_size 191337 1 T1 530 T2 9 T3 111
values[0x1] all_enables biggest_size 25265 1 T1 67 T3 6 T7 26


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1486973 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 237474 1 T1 622 T2 16 T3 149


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 585005 1 T1 1554 T2 32 T3 288
values[0x0] 554394 1 T1 1518 T2 39 T3 346
values[0x1] 585048 1 T1 1507 T2 31 T3 283


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1149847 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 574600 1 T1 1467 T2 30 T3 307


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26689 1 T1 65 T3 19 T7 7
valid_sources[0x01] 27082 1 T1 76 T2 2 T3 31
valid_sources[0x02] 26344 1 T1 93 T2 2 T3 12
valid_sources[0x03] 26479 1 T1 76 T7 6 T9 50
valid_sources[0x04] 27056 1 T1 68 T2 1 T3 18
valid_sources[0x05] 27019 1 T1 69 T2 2 T3 8
valid_sources[0x06] 26698 1 T1 66 T2 4 T7 27
valid_sources[0x07] 26842 1 T1 60 T2 1 T3 26
valid_sources[0x08] 26526 1 T1 76 T7 51 T9 52
valid_sources[0x09] 26669 1 T1 68 T2 3 T3 14
valid_sources[0x0a] 27463 1 T1 70 T2 3 T3 10
valid_sources[0x0b] 26517 1 T1 88 T2 4 T7 19
valid_sources[0x0c] 27281 1 T1 90 T2 1 T7 72
valid_sources[0x0d] 26447 1 T1 71 T9 53 T4 40
valid_sources[0x0e] 26813 1 T1 81 T2 1 T7 48
valid_sources[0x0f] 26992 1 T1 71 T2 1 T3 26
valid_sources[0x10] 27656 1 T1 73 T3 16 T7 6
valid_sources[0x11] 27322 1 T1 67 T2 4 T7 37
valid_sources[0x12] 26614 1 T1 64 T2 1 T3 26
valid_sources[0x13] 27545 1 T1 82 T2 1 T3 6
valid_sources[0x14] 26906 1 T1 67 T3 17 T7 10
valid_sources[0x15] 26185 1 T1 84 T2 5 T7 36
valid_sources[0x16] 27083 1 T1 64 T2 3 T7 7
valid_sources[0x17] 27747 1 T1 65 T2 3 T3 37
valid_sources[0x18] 26474 1 T1 71 T3 11 T7 46
valid_sources[0x19] 26842 1 T1 62 T3 8 T7 7
valid_sources[0x1a] 27587 1 T1 64 T7 19 T9 64
valid_sources[0x1b] 26601 1 T1 80 T3 52 T7 42
valid_sources[0x1c] 26493 1 T1 73 T2 2 T3 14
valid_sources[0x1d] 26673 1 T1 70 T2 2 T3 38
valid_sources[0x1e] 27328 1 T1 85 T2 3 T3 54
valid_sources[0x1f] 26940 1 T1 76 T2 1 T3 35
valid_sources[0x20] 26908 1 T1 68 T2 2 T7 17


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24924 1 T1 61 T2 1 T3 12
values[0x0] all_enables biggest_size 187754 1 T1 497 T2 12 T3 128
values[0x1] all_enables biggest_size 24796 1 T1 64 T2 3 T3 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%