Unified Coverage Report :: Group :: tl_agent_pkg::tl_d_chan_cov_cg

Group : tl_agent_pkg::tl_d_chan_cov_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

24 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125874

1

T2

5

T3

31

T7

39

auto[1]

76477

1

T2

5

T3

39

T7

68

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51928

1

T2

2

T3

18

T7

35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142383	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59968

1

T2

2

T3

27

T7

43

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16132

1

T3

7

T7

16

T9

79

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141346

1

T1

326

T2

10

T3

66

auto[1]

69264

1

T1

200

T2

2

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52889

1

T1

193

T2

2

T3

31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62637

1

T1

174

T2

9

T3

29

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16652

1

T1

72

T2

1

T3

10

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137128

1

T1

132

T2

10

T3

29

auto[1]

68980

1

T1

299

T3

47

T7

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51829

1

T1

139

T2

5

T3

29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61296

1

T1

146

T2

2

T3

23

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16208

1

T1

57

T3

11

T7

16

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132270

1

T1

348

T2

3

T3

75

auto[1]

72081

1

T1

180

T2

11

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51045

1

T1

188

T2

4

T3

14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60330

1

T1

172

T2

5

T3

30

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16017

1

T1

63

T2

2

T3

6

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133558

1

T1

1314

T2

4

T3

72

auto[1]

69585

1

T1

127

T2

1

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51143

1

T1

509

T2

3

T3

22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142839	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60304

1

T1

480

T3

22

T7

43

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15944

1

T1

170

T3

6

T7

13

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130824

1

T1

167

T3

56

T7

73

auto[1]

74963

1

T1

326

T2

4

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52199

1

T1

159

T3

26

T7

51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60984

1

T1

153

T2

3

T3

21

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16231

1

T1

52

T3

8

T7

17

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

541022

1

T1

659

T2

19

T3

130

auto[1]

293227

1

T1

517

T2

17

T3

137

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

212841

1

T1

397

T2

10

T3

91

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	580151	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254098

1

T1

404

T2

14

T3

94

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

67555

1

T1

136

T2

4

T3

30

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137248

1

T1

317

T2

2

T3

40

auto[1]

71524

1

T1

194

T2

8

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53394

1

T1

167

T2

4

T3

26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61934

1

T1

160

T2

2

T3

21

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16717

1

T1

48

T2

1

T3

7

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133832

1

T1

185

T2

4

T3

31

auto[1]

73727

1

T1

386

T2

2

T3

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54253

1

T1

200

T2

2

T3

26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63696

1

T1

194

T2

3

T3

21

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17500

1

T1

71

T2

2

T3

4

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137146

1

T2

11

T3

46

T7

67

auto[1]

72605

1

T3

10

T7

49

T9

259

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52036

1

T2

6

T3

17

T7

37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62114

1

T2

2

T3

17

T7

34

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16098

1

T2

1

T3

4

T7

9

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132419

1

T2

5

T3

72

T7

56

auto[1]

77869

1

T2

1

T3

10

T7

70

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53916

1

T2

3

T3

33

T7

47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63866

1

T2

2

T3

28

T7

40

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17258

1

T2

1

T3

13

T7

17

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139236

1

T2

5

T3

32

T7

63

auto[1]

70728

1

T2

5

T3

32

T7

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54787

1

T2

1

T3

21

T7

33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64133

1

T2

3

T3

26

T7

42

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17356

1

T2

1

T3

10

T7

13

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137341

1

T2

6

T3

49

T7

82

auto[1]

73546

1

T2

10

T3

25

T7

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53726

1

T2

4

T3

33

T7

41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146256	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64631

1

T2

2

T3

23

T7

36

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17246

1

T3

12

T7

6

T8

54

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136431

1

T2

8

T3

26

T7

116

auto[1]

70197

1

T2

4

T3

62

T7

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51532

1

T2

7

T3

31

T7

43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145856	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60772

1

T2

2

T3

21

T7

38

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15831

1

T3

8

T7

12

T4

9

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

551233

1

T1

353

T2

16

T3

221

auto[1]

282489

1

T1

626

T2

13

T3

99

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

212721

1

T1

326

T2

8

T3

104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	581224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

252498

1

T1

348

T2

9

T3

105

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

66898

1

T1

111

T2

3

T3

27

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135333

1

T1

221

T2

5

T3

30

auto[1]

68597

1

T1

190

T3

47

T7

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51381

1

T1

137

T2

2

T3

26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60416

1

T1

137

T2

1

T3

27

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15876

1

T1

44

T2

1

T3

8

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

556010

1

T1

1055

T2

17

T3

225

auto[1]

271225

1

T1

76

T2

13

T3

106

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

211821

1

T1

382

T2

9

T3

109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	575540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

251695

1

T1

399

T2

10

T3

111

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

67430

1

T1

143

T2

3

T3

33

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141344

1

T1

161

T3

33

T7

77

auto[1]

76489

1

T1

341

T2

6

T3

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54068

1

T1

155

T2

2

T3

18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64249

1

T1

155

T2

2

T3

24

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16744

1

T1

47

T2

1

T3

3

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

142314

1

T2

9

T3

42

T7

37

auto[1]

78092

1

T2

3

T3

40

T7

82

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56192

1

T2

2

T3

26

T7

39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153683	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66723

1

T2

5

T3

28

T7

42

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17779

1

T3

9

T7

14

T4

23

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138266

1

T1

278

T2

9

T3

28

auto[1]

75218

1

T1

179

T3

65

T7

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53834

1

T1

152

T2

3

T3

28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149971	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63513

1

T1

167

T2

2

T3

31

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16866

1

T1

57

T2

1

T3

6

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129280

1

T1

416

T2

2

T3

51

auto[1]

68062

1

T1

587

T2

6

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

49107

1

T1

348

T2

2

T3

25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	138889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

58453

1

T1

337

T2

1

T3

27

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15223

1

T1

111

T3

9

T7

10

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

560372

1

T1

1112

T2

5

T3

157

auto[1]

260815

1

T1

646

T2

23

T3

144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

210689

1

T1

561

T2

11

T3

122

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	571489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

249698

1

T1

532

T2

11

T3

107

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

66415

1

T1

162

T2

6

T3

43

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130889

1

T1

216

T2

4

T3

71

auto[1]

67117

1

T1

302

T2

2

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

48702

1

T1

182

T2

2

T3

26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	140004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

58002

1

T1

157

T2

2

T3

23

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15023

1

T1

65

T2

2

T3

6

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132471

1

T1

824

T2

5

T3

66

auto[1]

67307

1

T1

601

T2

7

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51014

1

T1

475

T2

3

T3

18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	138834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60944

1

T1

435

T2

3

T3

25

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16315

1

T1

133

T3

4

T7

11