Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7465989	0	0
GntImpliesValid_A	2147483647	7465989	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7465989	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	453064729	0	0
ReadyAndValidImplyGrant_A	2147483647	7465989	0	0
ReqAndReadyImplyGrant_A	2147483647	7465989	0	0
ReqImpliesValid_A	2147483647	33147850	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	43225	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7465989	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5038488	5037096	0	0
T2	4437288	4437048	0	0
T3	179952	179088	0	0
T4	238920	236856	0	0
T7	2146392	2144112	0	0
T8	80664	79896	0	0
T9	8834304	8834232	0	0
T10	151800	150240	0	0
T11	1279272	1278216	0	0
T12	272712	272448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465989	0	0
T1	3568929	13861	0	0
T2	4437288	307	0	0
T3	179952	2739	0	0
T4	238920	3194	0	0
T7	2146392	4505	0	0
T8	80664	771	0	0
T9	8834304	9357	0	0
T10	151800	2161	0	0
T11	1279272	4394	0	0
T12	272712	935	0	0
T13	328748	3007	0	0
T14	0	203	0	0
T15	0	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465989	0	0
T1	3568929	13861	0	0
T2	4437288	307	0	0
T3	179952	2739	0	0
T4	238920	3194	0	0
T7	2146392	4505	0	0
T8	80664	771	0	0
T9	8834304	9357	0	0
T10	151800	2161	0	0
T11	1279272	4394	0	0
T12	272712	935	0	0
T13	328748	3007	0	0
T14	0	203	0	0
T15	0	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5038488	5037096	0	0
T2	4437288	4437048	0	0
T3	179952	179088	0	0
T4	238920	236856	0	0
T7	2146392	2144112	0	0
T8	80664	79896	0	0
T9	8834304	8834232	0	0
T10	151800	150240	0	0
T11	1279272	1278216	0	0
T12	272712	272448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5038488	5037096	0	0
T2	4437288	4437048	0	0
T3	179952	179088	0	0
T4	238920	236856	0	0
T7	2146392	2144112	0	0
T8	80664	79896	0	0
T9	8834304	8834232	0	0
T10	151800	150240	0	0
T11	1279272	1278216	0	0
T12	272712	272448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465989	0	0
T1	3568929	13861	0	0
T2	4437288	307	0	0
T3	179952	2739	0	0
T4	238920	3194	0	0
T7	2146392	4505	0	0
T8	80664	771	0	0
T9	8834304	9357	0	0
T10	151800	2161	0	0
T11	1279272	4394	0	0
T12	272712	935	0	0
T13	328748	3007	0	0
T14	0	203	0	0
T15	0	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453064729	0	0
T1	4828551	234792	0	0
T2	4437288	155310	0	0
T3	179952	3347	0	0
T4	238920	5743	0	0
T7	2146392	116721	0	0
T8	80664	119	0	0
T9	8834304	337554	0	0
T10	151800	3211	0	0
T11	1279272	81418	0	0
T12	272712	15497	0	0
T13	46964	5528	0	0
T14	0	391	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465989	0	0
T1	3568929	13861	0	0
T2	4437288	307	0	0
T3	179952	2739	0	0
T4	238920	3194	0	0
T7	2146392	4505	0	0
T8	80664	771	0	0
T9	8834304	9357	0	0
T10	151800	2161	0	0
T11	1279272	4394	0	0
T12	272712	935	0	0
T13	328748	3007	0	0
T14	0	203	0	0
T15	0	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465989	0	0
T1	3568929	13861	0	0
T2	4437288	307	0	0
T3	179952	2739	0	0
T4	238920	3194	0	0
T7	2146392	4505	0	0
T8	80664	771	0	0
T9	8834304	9357	0	0
T10	151800	2161	0	0
T11	1279272	4394	0	0
T12	272712	935	0	0
T13	328748	3007	0	0
T14	0	203	0	0
T15	0	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33147850	0	0
T1	3568929	153877	0	0
T2	4437288	487	0	0
T3	179952	2817	0	0
T4	238920	4004	0	0
T7	2146392	8506	0	0
T8	80664	3371	0	0
T9	8834304	22371	0	0
T10	151800	2429	0	0
T11	1279272	10654	0	0
T12	272712	1922	0	0
T13	328748	4448	0	0
T14	0	273	0	0
T15	0	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43225	0	21600
T1	209937	9	0	1
T2	184887	0	0	1
T3	14996	7	0	2
T4	19910	6	0	2
T7	178866	0	0	2
T8	6722	0	0	2
T9	736192	0	0	2
T10	12650	6	0	2
T11	106606	0	0	2
T12	22726	0	0	2
T13	46964	0	0	1
T14	7558	0	0	1
T16	0	18	0	0
T17	0	479	0	0
T18	0	291	0	0
T19	0	27	0	0
T20	0	18	0	0
T21	0	1	0	0
T22	0	27	0	0
T23	0	2	0	0
T24	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5038488	5037096	0	0
T2	4437288	4437048	0	0
T3	179952	179088	0	0
T4	238920	236856	0	0
T7	2146392	2144112	0	0
T8	80664	79896	0	0
T9	8834304	8834232	0	0
T10	151800	150240	0	0
T11	1279272	1278216	0	0
T12	272712	272448	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465989	0	0
T1	3568929	13861	0	0
T2	4437288	307	0	0
T3	179952	2739	0	0
T4	238920	3194	0	0
T7	2146392	4505	0	0
T8	80664	771	0	0
T9	8834304	9357	0	0
T10	151800	2161	0	0
T11	1279272	4394	0	0
T12	272712	935	0	0
T13	328748	3007	0	0
T14	0	203	0	0
T15	0	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	827514	0	0
GntImpliesValid_A	417859558	827514	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	827514	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	11516451	0	0
ReadyAndValidImplyGrant_A	417859558	827514	0	0
ReqAndReadyImplyGrant_A	417859558	827514	0	0
ReqImpliesValid_A	417859558	2353224	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	827514	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	827514	0	0
T1	209937	1131	0	0
T2	184887	30	0	0
T3	7498	331	0	0
T4	9955	361	0	0
T7	89433	539	0	0
T8	3361	70	0	0
T9	368096	1483	0	0
T10	6325	185	0	0
T11	53303	467	0	0
T12	11363	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	827514	0	0
T1	209937	1131	0	0
T2	184887	30	0	0
T3	7498	331	0	0
T4	9955	361	0	0
T7	89433	539	0	0
T8	3361	70	0	0
T9	368096	1483	0	0
T10	6325	185	0	0
T11	53303	467	0	0
T12	11363	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	827514	0	0
T1	209937	1131	0	0
T2	184887	30	0	0
T3	7498	331	0	0
T4	9955	361	0	0
T7	89433	539	0	0
T8	3361	70	0	0
T9	368096	1483	0	0
T10	6325	185	0	0
T11	53303	467	0	0
T12	11363	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	11516451	0	0
T1	209937	8163	0	0
T2	184887	132	0	0
T3	7498	326	0	0
T4	9955	298	0	0
T7	89433	3803	0	0
T8	3361	50	0	0
T9	368096	5511	0	0
T10	6325	166	0	0
T11	53303	3464	0	0
T12	11363	840	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	827514	0	0
T1	209937	1131	0	0
T2	184887	30	0	0
T3	7498	331	0	0
T4	9955	361	0	0
T7	89433	539	0	0
T8	3361	70	0	0
T9	368096	1483	0	0
T10	6325	185	0	0
T11	53303	467	0	0
T12	11363	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	827514	0	0
T1	209937	1131	0	0
T2	184887	30	0	0
T3	7498	331	0	0
T4	9955	361	0	0
T7	89433	539	0	0
T8	3361	70	0	0
T9	368096	1483	0	0
T10	6325	185	0	0
T11	53303	467	0	0
T12	11363	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2353224	0	0
T1	209937	2043	0	0
T2	184887	38	0	0
T3	7498	337	0	0
T4	9955	425	0	0
T7	89433	654	0	0
T8	3361	91	0	0
T9	368096	2894	0	0
T10	6325	205	0	0
T11	53303	774	0	0
T12	11363	245	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	827514	0	0
T1	209937	1131	0	0
T2	184887	30	0	0
T3	7498	331	0	0
T4	9955	361	0	0
T7	89433	539	0	0
T8	3361	70	0	0
T9	368096	1483	0	0
T10	6325	185	0	0
T11	53303	467	0	0
T12	11363	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	834386	0	0
GntImpliesValid_A	417859558	834386	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	834386	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	11822509	0	0
ReadyAndValidImplyGrant_A	417859558	834386	0	0
ReqAndReadyImplyGrant_A	417859558	834386	0	0
ReqImpliesValid_A	417859558	2407588	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	834386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834386	0	0
T1	209937	1176	0	0
T2	184887	36	0	0
T3	7498	267	0	0
T4	9955	342	0	0
T7	89433	515	0	0
T8	3361	63	0	0
T9	368096	671	0	0
T10	6325	210	0	0
T11	53303	437	0	0
T12	11363	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834386	0	0
T1	209937	1176	0	0
T2	184887	36	0	0
T3	7498	267	0	0
T4	9955	342	0	0
T7	89433	515	0	0
T8	3361	63	0	0
T9	368096	671	0	0
T10	6325	210	0	0
T11	53303	437	0	0
T12	11363	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834386	0	0
T1	209937	1176	0	0
T2	184887	36	0	0
T3	7498	267	0	0
T4	9955	342	0	0
T7	89433	515	0	0
T8	3361	63	0	0
T9	368096	671	0	0
T10	6325	210	0	0
T11	53303	437	0	0
T12	11363	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	11822509	0	0
T1	209937	7935	0	0
T2	184887	148	0	0
T3	7498	264	0	0
T4	9955	290	0	0
T7	89433	3844	0	0
T8	3361	45	0	0
T9	368096	2820	0	0
T10	6325	178	0	0
T11	53303	2972	0	0
T12	11363	796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834386	0	0
T1	209937	1176	0	0
T2	184887	36	0	0
T3	7498	267	0	0
T4	9955	342	0	0
T7	89433	515	0	0
T8	3361	63	0	0
T9	368096	671	0	0
T10	6325	210	0	0
T11	53303	437	0	0
T12	11363	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834386	0	0
T1	209937	1176	0	0
T2	184887	36	0	0
T3	7498	267	0	0
T4	9955	342	0	0
T7	89433	515	0	0
T8	3361	63	0	0
T9	368096	671	0	0
T10	6325	210	0	0
T11	53303	437	0	0
T12	11363	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2407588	0	0
T1	209937	1940	0	0
T2	184887	64	0	0
T3	7498	271	0	0
T4	9955	395	0	0
T7	89433	575	0	0
T8	3361	82	0	0
T9	368096	920	0	0
T10	6325	243	0	0
T11	53303	678	0	0
T12	11363	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834386	0	0
T1	209937	1176	0	0
T2	184887	36	0	0
T3	7498	267	0	0
T4	9955	342	0	0
T7	89433	515	0	0
T8	3361	63	0	0
T9	368096	671	0	0
T10	6325	210	0	0
T11	53303	437	0	0
T12	11363	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T4,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T7,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	206651	0	0
GntImpliesValid_A	417859558	206651	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	206651	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2937562	0	0
ReadyAndValidImplyGrant_A	417859558	206651	0	0
ReqAndReadyImplyGrant_A	417859558	206651	0	0
ReqImpliesValid_A	417859558	533114	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	206651	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206651	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	76	0	0
T7	89433	135	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	126	0	0
T12	11363	29	0	0
T13	46964	139	0	0
T14	0	11	0	0
T15	0	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206651	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	76	0	0
T7	89433	135	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	126	0	0
T12	11363	29	0	0
T13	46964	139	0	0
T14	0	11	0	0
T15	0	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206651	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	76	0	0
T7	89433	135	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	126	0	0
T12	11363	29	0	0
T13	46964	139	0	0
T14	0	11	0	0
T15	0	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2937562	0	0
T1	209937	1	0	0
T2	184887	53	0	0
T3	7498	89	0	0
T4	9955	76	0	0
T7	89433	991	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	66	0	0
T11	53303	912	0	0
T12	11363	223	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206651	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	76	0	0
T7	89433	135	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	126	0	0
T12	11363	29	0	0
T13	46964	139	0	0
T14	0	11	0	0
T15	0	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206651	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	76	0	0
T7	89433	135	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	126	0	0
T12	11363	29	0	0
T13	46964	139	0	0
T14	0	11	0	0
T15	0	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	533114	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	77	0	0
T7	89433	143	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	69	0	0
T11	53303	186	0	0
T12	11363	30	0	0
T13	46964	177	0	0
T14	0	13	0	0
T15	0	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206651	0	0
T2	184887	12	0	0
T3	7498	88	0	0
T4	9955	76	0	0
T7	89433	135	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	126	0	0
T12	11363	29	0	0
T13	46964	139	0	0
T14	0	11	0	0
T15	0	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	217889	0	0
GntImpliesValid_A	417859558	217889	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	217889	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2933270	0	0
ReadyAndValidImplyGrant_A	417859558	217889	0	0
ReqAndReadyImplyGrant_A	417859558	217889	0	0
ReqImpliesValid_A	417859558	589215	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	217889	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	217889	0	0
T1	209937	502	0	0
T2	184887	6	0	0
T3	7498	73	0	0
T4	9955	85	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	64	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	129	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	217889	0	0
T1	209937	502	0	0
T2	184887	6	0	0
T3	7498	73	0	0
T4	9955	85	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	64	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	129	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	217889	0	0
T1	209937	502	0	0
T2	184887	6	0	0
T3	7498	73	0	0
T4	9955	85	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	64	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	129	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2933270	0	0
T1	209937	969	0	0
T2	184887	32	0	0
T3	7498	73	0	0
T4	9955	82	0	0
T7	89433	910	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	63	0	0
T11	53303	844	0	0
T12	11363	226	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	217889	0	0
T1	209937	502	0	0
T2	184887	6	0	0
T3	7498	73	0	0
T4	9955	85	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	64	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	129	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	217889	0	0
T1	209937	502	0	0
T2	184887	6	0	0
T3	7498	73	0	0
T4	9955	85	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	64	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	129	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	589215	0	0
T1	209937	2213	0	0
T2	184887	6	0	0
T3	7498	74	0	0
T4	9955	89	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	158	0	0
T12	11363	24	0	0
T13	0	186	0	0
T14	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	217889	0	0
T1	209937	502	0	0
T2	184887	6	0	0
T3	7498	73	0	0
T4	9955	85	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	64	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	129	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T3,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	210940	0	0
GntImpliesValid_A	417859558	210940	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	210940	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	5723699	0	0
ReadyAndValidImplyGrant_A	417859558	210940	0	0
ReqAndReadyImplyGrant_A	417859558	210940	0	0
ReqImpliesValid_A	417859558	1206901	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	210940	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210940	0	0
T2	184887	16	0	0
T3	7498	74	0	0
T4	9955	96	0	0
T7	89433	128	0	0
T8	3361	480	0	0
T9	368096	0	0	0
T10	6325	50	0	0
T11	53303	126	0	0
T12	11363	23	0	0
T13	46964	168	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210940	0	0
T2	184887	16	0	0
T3	7498	74	0	0
T4	9955	96	0	0
T7	89433	128	0	0
T8	3361	480	0	0
T9	368096	0	0	0
T10	6325	50	0	0
T11	53303	126	0	0
T12	11363	23	0	0
T13	46964	168	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210940	0	0
T2	184887	16	0	0
T3	7498	74	0	0
T4	9955	96	0	0
T7	89433	128	0	0
T8	3361	480	0	0
T9	368096	0	0	0
T10	6325	50	0	0
T11	53303	126	0	0
T12	11363	23	0	0
T13	46964	168	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	5723699	0	0
T2	184887	65	0	0
T3	7498	331	0	0
T4	9955	2290	0	0
T7	89433	2293	0	0
T8	3361	6	0	0
T9	368096	0	0	0
T10	6325	269	0	0
T11	53303	1764	0	0
T12	11363	126	0	0
T13	46964	1183	0	0
T14	0	103	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210940	0	0
T2	184887	16	0	0
T3	7498	74	0	0
T4	9955	96	0	0
T7	89433	128	0	0
T8	3361	480	0	0
T9	368096	0	0	0
T10	6325	50	0	0
T11	53303	126	0	0
T12	11363	23	0	0
T13	46964	168	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210940	0	0
T2	184887	16	0	0
T3	7498	74	0	0
T4	9955	96	0	0
T7	89433	128	0	0
T8	3361	480	0	0
T9	368096	0	0	0
T10	6325	50	0	0
T11	53303	126	0	0
T12	11363	23	0	0
T13	46964	168	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	1206901	0	0
T2	184887	16	0	0
T3	7498	79	0	0
T4	9955	551	0	0
T7	89433	128	0	0
T8	3361	3040	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	288	0	0
T12	11363	23	0	0
T13	46964	275	0	0
T14	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210940	0	0
T2	184887	16	0	0
T3	7498	74	0	0
T4	9955	96	0	0
T7	89433	128	0	0
T8	3361	480	0	0
T9	368096	0	0	0
T10	6325	50	0	0
T11	53303	126	0	0
T12	11363	23	0	0
T13	46964	168	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	213572	0	0
GntImpliesValid_A	417859558	213572	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	213572	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	4887263	0	0
ReadyAndValidImplyGrant_A	417859558	213572	0	0
ReqAndReadyImplyGrant_A	417859558	213572	0	0
ReqImpliesValid_A	417859558	1246297	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	213572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	213572	0	0
T1	209937	457	0	0
T2	184887	9	0	0
T3	7498	93	0	0
T4	9955	80	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	135	0	0
T12	11363	22	0	0
T13	0	150	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	213572	0	0
T1	209937	457	0	0
T2	184887	9	0	0
T3	7498	93	0	0
T4	9955	80	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	135	0	0
T12	11363	22	0	0
T13	0	150	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	213572	0	0
T1	209937	457	0	0
T2	184887	9	0	0
T3	7498	93	0	0
T4	9955	80	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	135	0	0
T12	11363	22	0	0
T13	0	150	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	4887263	0	0
T1	209937	1813	0	0
T2	184887	30	0	0
T3	7498	421	0	0
T4	9955	446	0	0
T7	89433	1826	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	627	0	0
T11	53303	5518	0	0
T12	11363	130	0	0
T13	0	2294	0	0
T14	0	118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	213572	0	0
T1	209937	457	0	0
T2	184887	9	0	0
T3	7498	93	0	0
T4	9955	80	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	135	0	0
T12	11363	22	0	0
T13	0	150	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	213572	0	0
T1	209937	457	0	0
T2	184887	9	0	0
T3	7498	93	0	0
T4	9955	80	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	135	0	0
T12	11363	22	0	0
T13	0	150	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	1246297	0	0
T1	209937	7915	0	0
T2	184887	15	0	0
T3	7498	119	0	0
T4	9955	101	0	0
T7	89433	153	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	135	0	0
T11	53303	717	0	0
T12	11363	22	0	0
T13	0	268	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	213572	0	0
T1	209937	457	0	0
T2	184887	9	0	0
T3	7498	93	0	0
T4	9955	80	0	0
T7	89433	131	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	135	0	0
T12	11363	22	0	0
T13	0	150	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	197466	0	0
GntImpliesValid_A	417859558	197466	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	197466	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	4855291	0	0
ReadyAndValidImplyGrant_A	417859558	197466	0	0
ReqAndReadyImplyGrant_A	417859558	197466	0	0
ReqImpliesValid_A	417859558	1056129	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	197466	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	197466	0	0
T1	209937	1003	0	0
T2	184887	8	0	0
T3	7498	82	0	0
T4	9955	67	0	0
T7	89433	137	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	121	0	0
T12	11363	23	0	0
T13	0	161	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	197466	0	0
T1	209937	1003	0	0
T2	184887	8	0	0
T3	7498	82	0	0
T4	9955	67	0	0
T7	89433	137	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	121	0	0
T12	11363	23	0	0
T13	0	161	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	197466	0	0
T1	209937	1003	0	0
T2	184887	8	0	0
T3	7498	82	0	0
T4	9955	67	0	0
T7	89433	137	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	121	0	0
T12	11363	23	0	0
T13	0	161	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	4855291	0	0
T1	209937	8693	0	0
T2	184887	61	0	0
T3	7498	510	0	0
T4	9955	381	0	0
T7	89433	6682	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	331	0	0
T11	53303	1284	0	0
T12	11363	147	0	0
T13	0	1125	0	0
T14	0	170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	197466	0	0
T1	209937	1003	0	0
T2	184887	8	0	0
T3	7498	82	0	0
T4	9955	67	0	0
T7	89433	137	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	121	0	0
T12	11363	23	0	0
T13	0	161	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	197466	0	0
T1	209937	1003	0	0
T2	184887	8	0	0
T3	7498	82	0	0
T4	9955	67	0	0
T7	89433	137	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	121	0	0
T12	11363	23	0	0
T13	0	161	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	1056129	0	0
T1	209937	38612	0	0
T2	184887	13	0	0
T3	7498	96	0	0
T4	9955	100	0	0
T7	89433	355	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	87	0	0
T11	53303	190	0	0
T12	11363	23	0	0
T13	0	229	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	197466	0	0
T1	209937	1003	0	0
T2	184887	8	0	0
T3	7498	82	0	0
T4	9955	67	0	0
T7	89433	137	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	62	0	0
T11	53303	121	0	0
T12	11363	23	0	0
T13	0	161	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	199864	0	0
GntImpliesValid_A	417859558	199864	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	199864	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	5271315	0	0
ReadyAndValidImplyGrant_A	417859558	199864	0	0
ReqAndReadyImplyGrant_A	417859558	199864	0	0
ReqImpliesValid_A	417859558	1109945	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	199864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	199864	0	0
T1	209937	1425	0	0
T2	184887	12	0	0
T3	7498	69	0	0
T4	9955	105	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	503	0	0
T10	6325	64	0	0
T11	53303	129	0	0
T12	11363	26	0	0
T13	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	199864	0	0
T1	209937	1425	0	0
T2	184887	12	0	0
T3	7498	69	0	0
T4	9955	105	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	503	0	0
T10	6325	64	0	0
T11	53303	129	0	0
T12	11363	26	0	0
T13	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	199864	0	0
T1	209937	1425	0	0
T2	184887	12	0	0
T3	7498	69	0	0
T4	9955	105	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	503	0	0
T10	6325	64	0	0
T11	53303	129	0	0
T12	11363	26	0	0
T13	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	5271315	0	0
T1	209937	10069	0	0
T2	184887	51	0	0
T3	7498	284	0	0
T4	9955	655	0	0
T7	89433	2831	0	0
T8	3361	0	0	0
T9	368096	2708	0	0
T10	6325	591	0	0
T11	53303	3864	0	0
T12	11363	149	0	0
T13	0	926	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	199864	0	0
T1	209937	1425	0	0
T2	184887	12	0	0
T3	7498	69	0	0
T4	9955	105	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	503	0	0
T10	6325	64	0	0
T11	53303	129	0	0
T12	11363	26	0	0
T13	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	199864	0	0
T1	209937	1425	0	0
T2	184887	12	0	0
T3	7498	69	0	0
T4	9955	105	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	503	0	0
T10	6325	64	0	0
T11	53303	129	0	0
T12	11363	26	0	0
T13	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	1109945	0	0
T1	209937	46915	0	0
T2	184887	15	0	0
T3	7498	83	0	0
T4	9955	210	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	1657	0	0
T10	6325	104	0	0
T11	53303	425	0	0
T12	11363	36	0	0
T13	0	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	199864	0	0
T1	209937	1425	0	0
T2	184887	12	0	0
T3	7498	69	0	0
T4	9955	105	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	503	0	0
T10	6325	64	0	0
T11	53303	129	0	0
T12	11363	26	0	0
T13	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	205816	0	0
GntImpliesValid_A	417859558	205816	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	205816	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2850820	0	0
ReadyAndValidImplyGrant_A	417859558	205816	0	0
ReqAndReadyImplyGrant_A	417859558	205816	0	0
ReqImpliesValid_A	417859558	524953	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	205816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	205816	0	0
T1	209937	493	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	148	0	0
T8	3361	0	0	0
T9	368096	1040	0	0
T10	6325	60	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	205816	0	0
T1	209937	493	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	148	0	0
T8	3361	0	0	0
T9	368096	1040	0	0
T10	6325	60	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	205816	0	0
T1	209937	493	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	148	0	0
T8	3361	0	0	0
T9	368096	1040	0	0
T10	6325	60	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2850820	0	0
T1	209937	1514	0	0
T2	184887	13	0	0
T3	7498	73	0	0
T4	9955	81	0	0
T7	89433	1116	0	0
T8	3361	1	0	0
T9	368096	3432	0	0
T10	6325	59	0	0
T11	53303	999	0	0
T12	11363	152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	205816	0	0
T1	209937	493	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	148	0	0
T8	3361	0	0	0
T9	368096	1040	0	0
T10	6325	60	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	205816	0	0
T1	209937	493	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	148	0	0
T8	3361	0	0	0
T9	368096	1040	0	0
T10	6325	60	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	524953	0	0
T1	209937	4012	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	86	0	0
T7	89433	159	0	0
T8	3361	0	0	0
T9	368096	2476	0	0
T10	6325	62	0	0
T11	53303	120	0	0
T12	11363	33	0	0
T13	0	187	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	205816	0	0
T1	209937	493	0	0
T2	184887	4	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	148	0	0
T8	3361	0	0	0
T9	368096	1040	0	0
T10	6325	60	0	0
T11	53303	119	0	0
T12	11363	24	0	0
T13	0	136	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	208841	0	0
GntImpliesValid_A	417859558	208841	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	208841	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2894925	0	0
ReadyAndValidImplyGrant_A	417859558	208841	0	0
ReqAndReadyImplyGrant_A	417859558	208841	0	0
ReqImpliesValid_A	417859558	557687	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	208841	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	208841	0	0
T1	209937	511	0	0
T2	184887	10	0	0
T3	7498	66	0	0
T4	9955	85	0	0
T7	89433	127	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	111	0	0
T12	11363	20	0	0
T13	0	133	0	0
T14	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	208841	0	0
T1	209937	511	0	0
T2	184887	10	0	0
T3	7498	66	0	0
T4	9955	85	0	0
T7	89433	127	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	111	0	0
T12	11363	20	0	0
T13	0	133	0	0
T14	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	208841	0	0
T1	209937	511	0	0
T2	184887	10	0	0
T3	7498	66	0	0
T4	9955	85	0	0
T7	89433	127	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	111	0	0
T12	11363	20	0	0
T13	0	133	0	0
T14	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2894925	0	0
T1	209937	1182	0	0
T2	184887	33	0	0
T3	7498	67	0	0
T4	9955	84	0	0
T7	89433	957	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	66	0	0
T11	53303	909	0	0
T12	11363	188	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	208841	0	0
T1	209937	511	0	0
T2	184887	10	0	0
T3	7498	66	0	0
T4	9955	85	0	0
T7	89433	127	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	111	0	0
T12	11363	20	0	0
T13	0	133	0	0
T14	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	208841	0	0
T1	209937	511	0	0
T2	184887	10	0	0
T3	7498	66	0	0
T4	9955	85	0	0
T7	89433	127	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	111	0	0
T12	11363	20	0	0
T13	0	133	0	0
T14	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	557687	0	0
T1	209937	2133	0	0
T2	184887	17	0	0
T3	7498	66	0	0
T4	9955	87	0	0
T7	89433	134	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	67	0	0
T11	53303	154	0	0
T12	11363	22	0	0
T13	0	200	0	0
T14	0	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	208841	0	0
T1	209937	511	0	0
T2	184887	10	0	0
T3	7498	66	0	0
T4	9955	85	0	0
T7	89433	127	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	111	0	0
T12	11363	20	0	0
T13	0	133	0	0
T14	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	202549	0	0
GntImpliesValid_A	417859558	202549	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	202549	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2913566	0	0
ReadyAndValidImplyGrant_A	417859558	202549	0	0
ReqAndReadyImplyGrant_A	417859558	202549	0	0
ReqImpliesValid_A	417859558	502177	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	202549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	202549	0	0
T2	184887	10	0	0
T3	7498	70	0	0
T4	9955	89	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	893	0	0
T10	6325	89	0	0
T11	53303	126	0	0
T12	11363	21	0	0
T13	46964	146	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	202549	0	0
T2	184887	10	0	0
T3	7498	70	0	0
T4	9955	89	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	893	0	0
T10	6325	89	0	0
T11	53303	126	0	0
T12	11363	21	0	0
T13	46964	146	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	202549	0	0
T2	184887	10	0	0
T3	7498	70	0	0
T4	9955	89	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	893	0	0
T10	6325	89	0	0
T11	53303	126	0	0
T12	11363	21	0	0
T13	46964	146	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2913566	0	0
T1	209937	1	0	0
T2	184887	49	0	0
T3	7498	71	0	0
T4	9955	83	0	0
T7	89433	765	0	0
T8	3361	1	0	0
T9	368096	2905	0	0
T10	6325	86	0	0
T11	53303	965	0	0
T12	11363	111	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	202549	0	0
T2	184887	10	0	0
T3	7498	70	0	0
T4	9955	89	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	893	0	0
T10	6325	89	0	0
T11	53303	126	0	0
T12	11363	21	0	0
T13	46964	146	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	202549	0	0
T2	184887	10	0	0
T3	7498	70	0	0
T4	9955	89	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	893	0	0
T10	6325	89	0	0
T11	53303	126	0	0
T12	11363	21	0	0
T13	46964	146	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	502177	0	0
T2	184887	14	0	0
T3	7498	70	0	0
T4	9955	96	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	2182	0	0
T10	6325	93	0	0
T11	53303	214	0	0
T12	11363	21	0	0
T13	46964	236	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	202549	0	0
T2	184887	10	0	0
T3	7498	70	0	0
T4	9955	89	0	0
T7	89433	107	0	0
T8	3361	0	0	0
T9	368096	893	0	0
T10	6325	89	0	0
T11	53303	126	0	0
T12	11363	21	0	0
T13	46964	146	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	203195	0	0
GntImpliesValid_A	417859558	203195	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	203195	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2875661	0	0
ReadyAndValidImplyGrant_A	417859558	203195	0	0
ReqAndReadyImplyGrant_A	417859558	203195	0	0
ReqImpliesValid_A	417859558	529593	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	203195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	203195	0	0
T1	209937	1441	0	0
T2	184887	5	0	0
T3	7498	78	0	0
T4	9955	83	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	499	0	0
T10	6325	59	0	0
T11	53303	99	0	0
T12	11363	17	0	0
T13	0	143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	203195	0	0
T1	209937	1441	0	0
T2	184887	5	0	0
T3	7498	78	0	0
T4	9955	83	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	499	0	0
T10	6325	59	0	0
T11	53303	99	0	0
T12	11363	17	0	0
T13	0	143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	203195	0	0
T1	209937	1441	0	0
T2	184887	5	0	0
T3	7498	78	0	0
T4	9955	83	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	499	0	0
T10	6325	59	0	0
T11	53303	99	0	0
T12	11363	17	0	0
T13	0	143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2875661	0	0
T1	209937	3754	0	0
T2	184887	20	0	0
T3	7498	78	0	0
T4	9955	82	0	0
T7	89433	933	0	0
T8	3361	1	0	0
T9	368096	1664	0	0
T10	6325	54	0	0
T11	53303	716	0	0
T12	11363	152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	203195	0	0
T1	209937	1441	0	0
T2	184887	5	0	0
T3	7498	78	0	0
T4	9955	83	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	499	0	0
T10	6325	59	0	0
T11	53303	99	0	0
T12	11363	17	0	0
T13	0	143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	203195	0	0
T1	209937	1441	0	0
T2	184887	5	0	0
T3	7498	78	0	0
T4	9955	83	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	499	0	0
T10	6325	59	0	0
T11	53303	99	0	0
T12	11363	17	0	0
T13	0	143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	529593	0	0
T1	209937	12608	0	0
T2	184887	5	0	0
T3	7498	79	0	0
T4	9955	85	0	0
T7	89433	141	0	0
T8	3361	0	0	0
T9	368096	1169	0	0
T10	6325	65	0	0
T11	53303	175	0	0
T12	11363	21	0	0
T13	0	222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	203195	0	0
T1	209937	1441	0	0
T2	184887	5	0	0
T3	7498	78	0	0
T4	9955	83	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	499	0	0
T10	6325	59	0	0
T11	53303	99	0	0
T12	11363	17	0	0
T13	0	143	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	210694	0	0
GntImpliesValid_A	417859558	210694	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	210694	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	3009068	0	0
ReadyAndValidImplyGrant_A	417859558	210694	0	0
ReqAndReadyImplyGrant_A	417859558	210694	0	0
ReqImpliesValid_A	417859558	563145	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	210694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210694	0	0
T1	209937	526	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	86	0	0
T7	89433	111	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	70	0	0
T11	53303	110	0	0
T12	11363	26	0	0
T13	0	162	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210694	0	0
T1	209937	526	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	86	0	0
T7	89433	111	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	70	0	0
T11	53303	110	0	0
T12	11363	26	0	0
T13	0	162	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210694	0	0
T1	209937	526	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	86	0	0
T7	89433	111	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	70	0	0
T11	53303	110	0	0
T12	11363	26	0	0
T13	0	162	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	3009068	0	0
T1	209937	1226	0	0
T2	184887	49	0	0
T3	7498	79	0	0
T4	9955	83	0	0
T7	89433	845	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	64	0	0
T11	53303	844	0	0
T12	11363	207	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210694	0	0
T1	209937	526	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	86	0	0
T7	89433	111	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	70	0	0
T11	53303	110	0	0
T12	11363	26	0	0
T13	0	162	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210694	0	0
T1	209937	526	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	86	0	0
T7	89433	111	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	70	0	0
T11	53303	110	0	0
T12	11363	26	0	0
T13	0	162	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	563145	0	0
T1	209937	1990	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	90	0	0
T7	89433	112	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	77	0	0
T11	53303	137	0	0
T12	11363	26	0	0
T13	0	234	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210694	0	0
T1	209937	526	0	0
T2	184887	12	0	0
T3	7498	78	0	0
T4	9955	86	0	0
T7	89433	111	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	70	0	0
T11	53303	110	0	0
T12	11363	26	0	0
T13	0	162	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	206134	0	0
GntImpliesValid_A	417859558	206134	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	206134	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2930256	0	0
ReadyAndValidImplyGrant_A	417859558	206134	0	0
ReqAndReadyImplyGrant_A	417859558	206134	0	0
ReqImpliesValid_A	417859558	540749	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	206134	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206134	0	0
T1	209937	431	0	0
T2	184887	10	0	0
T3	7498	76	0	0
T4	9955	88	0	0
T7	89433	122	0	0
T8	3361	0	0	0
T9	368096	496	0	0
T10	6325	61	0	0
T11	53303	145	0	0
T12	11363	24	0	0
T13	0	157	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206134	0	0
T1	209937	431	0	0
T2	184887	10	0	0
T3	7498	76	0	0
T4	9955	88	0	0
T7	89433	122	0	0
T8	3361	0	0	0
T9	368096	496	0	0
T10	6325	61	0	0
T11	53303	145	0	0
T12	11363	24	0	0
T13	0	157	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206134	0	0
T1	209937	431	0	0
T2	184887	10	0	0
T3	7498	76	0	0
T4	9955	88	0	0
T7	89433	122	0	0
T8	3361	0	0	0
T9	368096	496	0	0
T10	6325	61	0	0
T11	53303	145	0	0
T12	11363	24	0	0
T13	0	157	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2930256	0	0
T1	209937	1152	0	0
T2	184887	54	0	0
T3	7498	76	0	0
T4	9955	85	0	0
T7	89433	958	0	0
T8	3361	1	0	0
T9	368096	1656	0	0
T10	6325	58	0	0
T11	53303	1069	0	0
T12	11363	177	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206134	0	0
T1	209937	431	0	0
T2	184887	10	0	0
T3	7498	76	0	0
T4	9955	88	0	0
T7	89433	122	0	0
T8	3361	0	0	0
T9	368096	496	0	0
T10	6325	61	0	0
T11	53303	145	0	0
T12	11363	24	0	0
T13	0	157	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206134	0	0
T1	209937	431	0	0
T2	184887	10	0	0
T3	7498	76	0	0
T4	9955	88	0	0
T7	89433	122	0	0
T8	3361	0	0	0
T9	368096	496	0	0
T10	6325	61	0	0
T11	53303	145	0	0
T12	11363	24	0	0
T13	0	157	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	540749	0	0
T1	209937	3581	0	0
T2	184887	19	0	0
T3	7498	77	0	0
T4	9955	92	0	0
T7	89433	169	0	0
T8	3361	0	0	0
T9	368096	1228	0	0
T10	6325	65	0	0
T11	53303	219	0	0
T12	11363	30	0	0
T13	0	257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	206134	0	0
T1	209937	431	0	0
T2	184887	10	0	0
T3	7498	76	0	0
T4	9955	88	0	0
T7	89433	122	0	0
T8	3361	0	0	0
T9	368096	496	0	0
T10	6325	61	0	0
T11	53303	145	0	0
T12	11363	24	0	0
T13	0	157	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	204401	0	0
GntImpliesValid_A	417859558	204401	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	204401	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2979409	0	0
ReadyAndValidImplyGrant_A	417859558	204401	0	0
ReqAndReadyImplyGrant_A	417859558	204401	0	0
ReqImpliesValid_A	417859558	525516	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	204401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204401	0	0
T1	209937	528	0	0
T2	184887	14	0	0
T3	7498	88	0	0
T4	9955	74	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	68	0	0
T11	53303	137	0	0
T12	11363	29	0	0
T13	0	169	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204401	0	0
T1	209937	528	0	0
T2	184887	14	0	0
T3	7498	88	0	0
T4	9955	74	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	68	0	0
T11	53303	137	0	0
T12	11363	29	0	0
T13	0	169	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204401	0	0
T1	209937	528	0	0
T2	184887	14	0	0
T3	7498	88	0	0
T4	9955	74	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	68	0	0
T11	53303	137	0	0
T12	11363	29	0	0
T13	0	169	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2979409	0	0
T1	209937	1366	0	0
T2	184887	59	0	0
T3	7498	88	0	0
T4	9955	72	0	0
T7	89433	969	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	60	0	0
T11	53303	1027	0	0
T12	11363	212	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204401	0	0
T1	209937	528	0	0
T2	184887	14	0	0
T3	7498	88	0	0
T4	9955	74	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	68	0	0
T11	53303	137	0	0
T12	11363	29	0	0
T13	0	169	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204401	0	0
T1	209937	528	0	0
T2	184887	14	0	0
T3	7498	88	0	0
T4	9955	74	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	68	0	0
T11	53303	137	0	0
T12	11363	29	0	0
T13	0	169	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	525516	0	0
T1	209937	1819	0	0
T2	184887	18	0	0
T3	7498	89	0	0
T4	9955	77	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	77	0	0
T11	53303	206	0	0
T12	11363	40	0	0
T13	0	220	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204401	0	0
T1	209937	528	0	0
T2	184887	14	0	0
T3	7498	88	0	0
T4	9955	74	0	0
T7	89433	139	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	68	0	0
T11	53303	137	0	0
T12	11363	29	0	0
T13	0	169	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	207619	0	0
GntImpliesValid_A	417859558	207619	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	207619	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2945187	0	0
ReadyAndValidImplyGrant_A	417859558	207619	0	0
ReqAndReadyImplyGrant_A	417859558	207619	0	0
ReqImpliesValid_A	417859558	568818	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	207619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	207619	0	0
T1	209937	571	0	0
T2	184887	6	0	0
T3	7498	80	0	0
T4	9955	77	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	47	0	0
T11	53303	112	0	0
T12	11363	23	0	0
T13	0	157	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	207619	0	0
T1	209937	571	0	0
T2	184887	6	0	0
T3	7498	80	0	0
T4	9955	77	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	47	0	0
T11	53303	112	0	0
T12	11363	23	0	0
T13	0	157	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	207619	0	0
T1	209937	571	0	0
T2	184887	6	0	0
T3	7498	80	0	0
T4	9955	77	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	47	0	0
T11	53303	112	0	0
T12	11363	23	0	0
T13	0	157	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2945187	0	0
T1	209937	1285	0	0
T2	184887	19	0	0
T3	7498	81	0	0
T4	9955	75	0	0
T7	89433	883	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	47	0	0
T11	53303	803	0	0
T12	11363	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	207619	0	0
T1	209937	571	0	0
T2	184887	6	0	0
T3	7498	80	0	0
T4	9955	77	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	47	0	0
T11	53303	112	0	0
T12	11363	23	0	0
T13	0	157	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	207619	0	0
T1	209937	571	0	0
T2	184887	6	0	0
T3	7498	80	0	0
T4	9955	77	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	47	0	0
T11	53303	112	0	0
T12	11363	23	0	0
T13	0	157	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	568818	0	0
T1	209937	5341	0	0
T2	184887	8	0	0
T3	7498	80	0	0
T4	9955	80	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	48	0	0
T11	53303	132	0	0
T12	11363	27	0	0
T13	0	199	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	207619	0	0
T1	209937	571	0	0
T2	184887	6	0	0
T3	7498	80	0	0
T4	9955	77	0	0
T7	89433	108	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	47	0	0
T11	53303	112	0	0
T12	11363	23	0	0
T13	0	157	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	220450	0	0
GntImpliesValid_A	417859558	220450	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	220450	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	3005390	0	0
ReadyAndValidImplyGrant_A	417859558	220450	0	0
ReqAndReadyImplyGrant_A	417859558	220450	0	0
ReqImpliesValid_A	417859558	548811	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	220450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	220450	0	0
T2	184887	12	0	0
T3	7498	82	0	0
T4	9955	165	0	0
T7	89433	119	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	106	0	0
T11	53303	128	0	0
T12	11363	49	0	0
T13	46964	166	0	0
T14	0	22	0	0
T15	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	220450	0	0
T2	184887	12	0	0
T3	7498	82	0	0
T4	9955	165	0	0
T7	89433	119	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	106	0	0
T11	53303	128	0	0
T12	11363	49	0	0
T13	46964	166	0	0
T14	0	22	0	0
T15	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	220450	0	0
T2	184887	12	0	0
T3	7498	82	0	0
T4	9955	165	0	0
T7	89433	119	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	106	0	0
T11	53303	128	0	0
T12	11363	49	0	0
T13	46964	166	0	0
T14	0	22	0	0
T15	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	3005390	0	0
T1	209937	1	0	0
T2	184887	52	0	0
T3	7498	80	0	0
T4	9955	145	0	0
T7	89433	916	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	101	0	0
T11	53303	913	0	0
T12	11363	390	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	220450	0	0
T2	184887	12	0	0
T3	7498	82	0	0
T4	9955	165	0	0
T7	89433	119	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	106	0	0
T11	53303	128	0	0
T12	11363	49	0	0
T13	46964	166	0	0
T14	0	22	0	0
T15	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	220450	0	0
T2	184887	12	0	0
T3	7498	82	0	0
T4	9955	165	0	0
T7	89433	119	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	106	0	0
T11	53303	128	0	0
T12	11363	49	0	0
T13	46964	166	0	0
T14	0	22	0	0
T15	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	548811	0	0
T2	184887	19	0	0
T3	7498	85	0	0
T4	9955	186	0	0
T7	89433	129	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	112	0	0
T11	53303	172	0	0
T12	11363	52	0	0
T13	46964	263	0	0
T14	0	40	0	0
T15	0	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	220450	0	0
T2	184887	12	0	0
T3	7498	82	0	0
T4	9955	165	0	0
T7	89433	119	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	106	0	0
T11	53303	128	0	0
T12	11363	49	0	0
T13	46964	166	0	0
T14	0	22	0	0
T15	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	210012	0	0
GntImpliesValid_A	417859558	210012	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	210012	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2944109	0	0
ReadyAndValidImplyGrant_A	417859558	210012	0	0
ReqAndReadyImplyGrant_A	417859558	210012	0	0
ReqImpliesValid_A	417859558	555510	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	210012	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210012	0	0
T2	184887	10	0	0
T3	7498	64	0	0
T4	9955	93	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	996	0	0
T10	6325	67	0	0
T11	53303	124	0	0
T12	11363	29	0	0
T13	46964	133	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210012	0	0
T2	184887	10	0	0
T3	7498	64	0	0
T4	9955	93	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	996	0	0
T10	6325	67	0	0
T11	53303	124	0	0
T12	11363	29	0	0
T13	46964	133	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210012	0	0
T2	184887	10	0	0
T3	7498	64	0	0
T4	9955	93	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	996	0	0
T10	6325	67	0	0
T11	53303	124	0	0
T12	11363	29	0	0
T13	46964	133	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2944109	0	0
T1	209937	1	0	0
T2	184887	52	0	0
T3	7498	64	0	0
T4	9955	92	0	0
T7	89433	765	0	0
T8	3361	1	0	0
T9	368096	3237	0	0
T10	6325	68	0	0
T11	53303	874	0	0
T12	11363	219	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210012	0	0
T2	184887	10	0	0
T3	7498	64	0	0
T4	9955	93	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	996	0	0
T10	6325	67	0	0
T11	53303	124	0	0
T12	11363	29	0	0
T13	46964	133	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210012	0	0
T2	184887	10	0	0
T3	7498	64	0	0
T4	9955	93	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	996	0	0
T10	6325	67	0	0
T11	53303	124	0	0
T12	11363	29	0	0
T13	46964	133	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	555510	0	0
T2	184887	10	0	0
T3	7498	65	0	0
T4	9955	95	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	2383	0	0
T10	6325	67	0	0
T11	53303	182	0	0
T12	11363	53	0	0
T13	46964	208	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210012	0	0
T2	184887	10	0	0
T3	7498	64	0	0
T4	9955	93	0	0
T7	89433	103	0	0
T8	3361	0	0	0
T9	368096	996	0	0
T10	6325	67	0	0
T11	53303	124	0	0
T12	11363	29	0	0
T13	46964	133	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T4,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T9,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	209803	0	0
GntImpliesValid_A	417859558	209803	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	209803	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2964302	0	0
ReadyAndValidImplyGrant_A	417859558	209803	0	0
ReqAndReadyImplyGrant_A	417859558	209803	0	0
ReqImpliesValid_A	417859558	569199	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	209803	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	209803	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	100	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	528	0	0
T10	6325	67	0	0
T11	53303	144	0	0
T12	11363	27	0	0
T13	46964	163	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	209803	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	100	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	528	0	0
T10	6325	67	0	0
T11	53303	144	0	0
T12	11363	27	0	0
T13	46964	163	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	209803	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	100	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	528	0	0
T10	6325	67	0	0
T11	53303	144	0	0
T12	11363	27	0	0
T13	46964	163	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2964302	0	0
T1	209937	1	0	0
T2	184887	72	0	0
T3	7498	57	0	0
T4	9955	94	0	0
T7	89433	806	0	0
T8	3361	1	0	0
T9	368096	1771	0	0
T10	6325	64	0	0
T11	53303	1046	0	0
T12	11363	194	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	209803	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	100	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	528	0	0
T10	6325	67	0	0
T11	53303	144	0	0
T12	11363	27	0	0
T13	46964	163	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	209803	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	100	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	528	0	0
T10	6325	67	0	0
T11	53303	144	0	0
T12	11363	27	0	0
T13	46964	163	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	569199	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	107	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	1210	0	0
T10	6325	71	0	0
T11	53303	229	0	0
T12	11363	31	0	0
T13	46964	290	0	0
T14	0	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	209803	0	0
T2	184887	11	0	0
T3	7498	56	0	0
T4	9955	100	0	0
T7	89433	116	0	0
T8	3361	0	0	0
T9	368096	528	0	0
T10	6325	67	0	0
T11	53303	144	0	0
T12	11363	27	0	0
T13	46964	163	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T4,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T9,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	210326	0	0
GntImpliesValid_A	417859558	210326	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	210326	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2956974	0	0
ReadyAndValidImplyGrant_A	417859558	210326	0	0
ReqAndReadyImplyGrant_A	417859558	210326	0	0
ReqImpliesValid_A	417859558	567746	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	210326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210326	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	103	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	486	0	0
T10	6325	69	0	0
T11	53303	118	0	0
T12	11363	26	0	0
T13	46964	159	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210326	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	103	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	486	0	0
T10	6325	69	0	0
T11	53303	118	0	0
T12	11363	26	0	0
T13	46964	159	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210326	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	103	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	486	0	0
T10	6325	69	0	0
T11	53303	118	0	0
T12	11363	26	0	0
T13	46964	159	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2956974	0	0
T1	209937	1	0	0
T2	184887	30	0	0
T3	7498	83	0	0
T4	9955	103	0	0
T7	89433	852	0	0
T8	3361	1	0	0
T9	368096	1574	0	0
T10	6325	67	0	0
T11	53303	869	0	0
T12	11363	185	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210326	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	103	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	486	0	0
T10	6325	69	0	0
T11	53303	118	0	0
T12	11363	26	0	0
T13	46964	159	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210326	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	103	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	486	0	0
T10	6325	69	0	0
T11	53303	118	0	0
T12	11363	26	0	0
T13	46964	159	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	567746	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	104	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	1230	0	0
T10	6325	72	0	0
T11	53303	151	0	0
T12	11363	26	0	0
T13	46964	198	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	210326	0	0
T2	184887	6	0	0
T3	7498	82	0	0
T4	9955	103	0	0
T7	89433	126	0	0
T8	3361	0	0	0
T9	368096	486	0	0
T10	6325	69	0	0
T11	53303	118	0	0
T12	11363	26	0	0
T13	46964	159	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	198120	0	0
GntImpliesValid_A	417859558	198120	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	198120	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2931036	0	0
ReadyAndValidImplyGrant_A	417859558	198120	0	0
ReqAndReadyImplyGrant_A	417859558	198120	0	0
ReqImpliesValid_A	417859558	501591	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	198120	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	198120	0	0
T1	209937	518	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	124	0	0
T8	3361	0	0	0
T9	368096	465	0	0
T10	6325	71	0	0
T11	53303	125	0	0
T12	11363	30	0	0
T13	0	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	198120	0	0
T1	209937	518	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	124	0	0
T8	3361	0	0	0
T9	368096	465	0	0
T10	6325	71	0	0
T11	53303	125	0	0
T12	11363	30	0	0
T13	0	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	198120	0	0
T1	209937	518	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	124	0	0
T8	3361	0	0	0
T9	368096	465	0	0
T10	6325	71	0	0
T11	53303	125	0	0
T12	11363	30	0	0
T13	0	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2931036	0	0
T1	209937	1092	0	0
T2	184887	33	0	0
T3	7498	73	0	0
T4	9955	74	0	0
T7	89433	994	0	0
T8	3361	1	0	0
T9	368096	1608	0	0
T10	6325	69	0	0
T11	53303	845	0	0
T12	11363	210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	198120	0	0
T1	209937	518	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	124	0	0
T8	3361	0	0	0
T9	368096	465	0	0
T10	6325	71	0	0
T11	53303	125	0	0
T12	11363	30	0	0
T13	0	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	198120	0	0
T1	209937	518	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	124	0	0
T8	3361	0	0	0
T9	368096	465	0	0
T10	6325	71	0	0
T11	53303	125	0	0
T12	11363	30	0	0
T13	0	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	501591	0	0
T1	209937	2034	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	93	0	0
T7	89433	125	0	0
T8	3361	0	0	0
T9	368096	1139	0	0
T10	6325	74	0	0
T11	53303	184	0	0
T12	11363	30	0	0
T13	0	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	198120	0	0
T1	209937	518	0	0
T2	184887	6	0	0
T3	7498	72	0	0
T4	9955	83	0	0
T7	89433	124	0	0
T8	3361	0	0	0
T9	368096	465	0	0
T10	6325	71	0	0
T11	53303	125	0	0
T12	11363	30	0	0
T13	0	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	204005	0	0
GntImpliesValid_A	417859558	204005	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	204005	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	2890755	0	0
ReadyAndValidImplyGrant_A	417859558	204005	0	0
ReqAndReadyImplyGrant_A	417859558	204005	0	0
ReqImpliesValid_A	417859558	527892	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	0	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	204005	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204005	0	0
T1	209937	411	0	0
T2	184887	5	0	0
T3	7498	77	0	0
T4	9955	74	0	0
T7	89433	128	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	60	0	0
T11	53303	138	0	0
T12	11363	32	0	0
T13	0	149	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204005	0	0
T1	209937	411	0	0
T2	184887	5	0	0
T3	7498	77	0	0
T4	9955	74	0	0
T7	89433	128	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	60	0	0
T11	53303	138	0	0
T12	11363	32	0	0
T13	0	149	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204005	0	0
T1	209937	411	0	0
T2	184887	5	0	0
T3	7498	77	0	0
T4	9955	74	0	0
T7	89433	128	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	60	0	0
T11	53303	138	0	0
T12	11363	32	0	0
T13	0	149	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2890755	0	0
T1	209937	1068	0	0
T2	184887	27	0	0
T3	7498	77	0	0
T4	9955	70	0	0
T7	89433	1010	0	0
T8	3361	1	0	0
T9	368096	1	0	0
T10	6325	55	0	0
T11	53303	1084	0	0
T12	11363	299	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204005	0	0
T1	209937	411	0	0
T2	184887	5	0	0
T3	7498	77	0	0
T4	9955	74	0	0
T7	89433	128	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	60	0	0
T11	53303	138	0	0
T12	11363	32	0	0
T13	0	149	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204005	0	0
T1	209937	411	0	0
T2	184887	5	0	0
T3	7498	77	0	0
T4	9955	74	0	0
T7	89433	128	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	60	0	0
T11	53303	138	0	0
T12	11363	32	0	0
T13	0	149	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	527892	0	0
T1	209937	3667	0	0
T2	184887	6	0	0
T3	7498	78	0	0
T4	9955	79	0	0
T7	89433	142	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	66	0	0
T11	53303	175	0	0
T12	11363	51	0	0
T13	0	234	0	0
T14	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	204005	0	0
T1	209937	411	0	0
T2	184887	5	0	0
T3	7498	77	0	0
T4	9955	74	0	0
T7	89433	128	0	0
T8	3361	0	0	0
T9	368096	0	0	0
T10	6325	60	0	0
T11	53303	138	0	0
T12	11363	32	0	0
T13	0	149	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	834148	0	0
GntImpliesValid_A	417859558	834148	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	834148	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	11198154	0	0
ReadyAndValidImplyGrant_A	417859558	834148	0	0
ReqAndReadyImplyGrant_A	417859558	834148	0	0
ReqImpliesValid_A	417859558	2190317	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	20020	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	834148	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834148	0	0
T1	209937	979	0	0
T2	184887	29	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	482	0	0
T8	3361	77	0	0
T9	368096	629	0	0
T10	6325	207	0	0
T11	53303	494	0	0
T12	11363	99	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834148	0	0
T1	209937	979	0	0
T2	184887	29	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	482	0	0
T8	3361	77	0	0
T9	368096	629	0	0
T10	6325	207	0	0
T11	53303	494	0	0
T12	11363	99	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834148	0	0
T1	209937	979	0	0
T2	184887	29	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	482	0	0
T8	3361	77	0	0
T9	368096	629	0	0
T10	6325	207	0	0
T11	53303	494	0	0
T12	11363	99	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	11198154	0	0
T1	209937	6531	0	0
T2	184887	71	0	0
T3	7498	1	0	0
T4	9955	1	0	0
T7	89433	2906	0	0
T8	3361	1	0	0
T9	368096	2134	0	0
T10	6325	1	0	0
T11	53303	2935	0	0
T12	11363	651	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834148	0	0
T1	209937	979	0	0
T2	184887	29	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	482	0	0
T8	3361	77	0	0
T9	368096	629	0	0
T10	6325	207	0	0
T11	53303	494	0	0
T12	11363	99	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834148	0	0
T1	209937	979	0	0
T2	184887	29	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	482	0	0
T8	3361	77	0	0
T9	368096	629	0	0
T10	6325	207	0	0
T11	53303	494	0	0
T12	11363	99	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	2190317	0	0
T1	209937	1438	0	0
T2	184887	30	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	558	0	0
T8	3361	77	0	0
T9	368096	811	0	0
T10	6325	207	0	0
T11	53303	781	0	0
T12	11363	111	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	20020	0	900
T3	7498	5	0	1
T4	9955	6	0	1
T7	89433	0	0	1
T8	3361	0	0	1
T9	368096	0	0	1
T10	6325	3	0	1
T11	53303	0	0	1
T12	11363	0	0	1
T13	46964	0	0	1
T14	7558	0	0	1
T16	0	9	0	0
T17	0	171	0	0
T18	0	291	0	0
T19	0	16	0	0
T20	0	9	0	0
T22	0	10	0	0
T24	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	834148	0	0
T1	209937	979	0	0
T2	184887	29	0	0
T3	7498	320	0	0
T4	9955	352	0	0
T7	89433	482	0	0
T8	3361	77	0	0
T9	368096	629	0	0
T10	6325	207	0	0
T11	53303	494	0	0
T12	11363	99	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417859558	417741372	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417859558	821594	0	0
GntImpliesValid_A	417859558	821594	0	0
GrantKnown_A	417859558	417741372	0	0
IdxKnown_A	417859558	417741372	0	0
IndexIsCorrect_A	417859558	821594	0	0
LockArbDecision_A	417859558	0	0	0
NoReadyValidNoGrant_A	417859558	350827757	0	0
ReadyAndValidImplyGrant_A	417859558	821594	0	0
ReqAndReadyImplyGrant_A	417859558	821594	0	0
ReqImpliesValid_A	417859558	12871733	0	0
ReqStaysHighUntilGranted0_M	417859558	0	0	0
RoundRobin_A	417859558	23205	0	900
ValidKnown_A	417859558	417741372	0	0
gen_data_port_assertion.DataFlow_A	417859558	821594	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	821594	0	0
T1	209937	1758	0	0
T2	184887	28	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	475	0	0
T8	3361	81	0	0
T9	368096	668	0	0
T10	6325	230	0	0
T11	53303	504	0	0
T12	11363	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	821594	0	0
T1	209937	1758	0	0
T2	184887	28	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	475	0	0
T8	3361	81	0	0
T9	368096	668	0	0
T10	6325	230	0	0
T11	53303	504	0	0
T12	11363	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	821594	0	0
T1	209937	1758	0	0
T2	184887	28	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	475	0	0
T8	3361	81	0	0
T9	368096	668	0	0
T10	6325	230	0	0
T11	53303	504	0	0
T12	11363	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	350827757	0	0
T1	209937	176974	0	0
T2	184887	154105	0	0
T3	7498	1	0	0
T4	9955	1	0	0
T7	89433	77866	0	0
T8	3361	1	0	0
T9	368096	306526	0	0
T10	6325	1	0	0
T11	53303	44898	0	0
T12	11363	9351	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	821594	0	0
T1	209937	1758	0	0
T2	184887	28	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	475	0	0
T8	3361	81	0	0
T9	368096	668	0	0
T10	6325	230	0	0
T11	53303	504	0	0
T12	11363	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	821594	0	0
T1	209937	1758	0	0
T2	184887	28	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	475	0	0
T8	3361	81	0	0
T9	368096	668	0	0
T10	6325	230	0	0
T11	53303	504	0	0
T12	11363	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	12871733	0	0
T1	209937	15616	0	0
T2	184887	123	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	3874	0	0
T8	3361	81	0	0
T9	368096	3072	0	0
T10	6325	230	0	0
T11	53303	4007	0	0
T12	11363	745	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	23205	0	900
T1	209937	9	0	1
T2	184887	0	0	1
T3	7498	2	0	1
T4	9955	0	0	1
T7	89433	0	0	1
T8	3361	0	0	1
T9	368096	0	0	1
T10	6325	3	0	1
T11	53303	0	0	1
T12	11363	0	0	1
T16	0	9	0	0
T17	0	308	0	0
T19	0	11	0	0
T20	0	9	0	0
T21	0	1	0	0
T22	0	17	0	0
T23	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	417741372	0	0
T1	209937	209879	0	0
T2	184887	184877	0	0
T3	7498	7462	0	0
T4	9955	9869	0	0
T7	89433	89338	0	0
T8	3361	3329	0	0
T9	368096	368093	0	0
T10	6325	6260	0	0
T11	53303	53259	0	0
T12	11363	11352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417859558	821594	0	0
T1	209937	1758	0	0
T2	184887	28	0	0
T3	7498	301	0	0
T4	9955	347	0	0
T7	89433	475	0	0
T8	3361	81	0	0
T9	368096	668	0	0
T10	6325	230	0	0
T11	53303	504	0	0
T12	11363	96	0	0