Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.70 100.00 100.00 98.80 100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 99.70 100.00 100.00 98.80 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.70 100.00 100.00 98.80 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.42 99.26 88.89 98.80 95.88 99.26


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tlul_assert_device_aes 100.00 100.00 100.00 100.00
tlul_assert_device_csrng 100.00 100.00 100.00 100.00
tlul_assert_device_edn0 100.00 100.00 100.00 100.00
tlul_assert_device_edn1 100.00 100.00 100.00 100.00
tlul_assert_device_entropy_src 100.00 100.00 100.00 100.00
tlul_assert_device_flash_ctrl__core 100.00 100.00 100.00 100.00
tlul_assert_device_flash_ctrl__mem 100.00 100.00 100.00 100.00
tlul_assert_device_flash_ctrl__prim 100.00 100.00 100.00 100.00
tlul_assert_device_hmac 100.00 100.00 100.00 100.00
tlul_assert_device_keymgr 100.00 100.00 100.00 100.00
tlul_assert_device_kmac 100.00 100.00 100.00 100.00
tlul_assert_device_otbn 100.00 100.00 100.00 100.00
tlul_assert_device_peri 100.00 100.00 100.00 100.00
tlul_assert_device_rom_ctrl__regs 100.00 100.00 100.00 100.00
tlul_assert_device_rom_ctrl__rom 100.00 100.00 100.00 100.00
tlul_assert_device_rv_core_ibex__cfg 100.00 100.00 100.00 100.00
tlul_assert_device_rv_dm__mem 100.00 100.00 100.00 100.00
tlul_assert_device_rv_dm__regs 100.00 100.00 100.00 100.00
tlul_assert_device_rv_plic 100.00 100.00 100.00 100.00
tlul_assert_device_spi_host0 100.00 100.00 100.00 100.00
tlul_assert_device_spi_host1 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_main__ram 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_main__regs 100.00 100.00 100.00 100.00
tlul_assert_device_usbdev 100.00 100.00 100.00 100.00
tlul_assert_host_rv_core_ibex__cored 100.00 100.00 100.00 100.00
tlul_assert_host_rv_core_ibex__corei 100.00 100.00 100.00 100.00
tlul_assert_host_rv_dm__sba 100.00 100.00 100.00 100.00
u_asf_35 99.11 100.00 96.43 100.00 100.00
u_asf_37 99.11 100.00 96.43 100.00 100.00
u_asf_39 99.11 100.00 96.43 100.00 100.00
u_asf_41 99.11 100.00 96.43 100.00 100.00
u_s1n_27 99.75 100.00 99.02 100.00 100.00
u_s1n_32 99.05 100.00 96.21 100.00 100.00
u_s1n_57 97.34 99.68 91.70 97.97 100.00
u_sm1_28 93.51 98.68 85.92 92.73 96.72
u_sm1_29 92.86 98.68 85.07 92.59 95.08
u_sm1_30 98.78 100.00 98.39 100.00 96.72
u_sm1_31 92.86 98.68 85.07 92.59 95.08
u_sm1_33 92.43 98.54 84.87 92.31 94.00
u_sm1_34 92.43 98.54 84.87 92.31 94.00
u_sm1_36 96.90 100.00 93.62 100.00 94.00
u_sm1_38 96.90 100.00 93.62 100.00 94.00
u_sm1_40 96.90 100.00 93.62 100.00 94.00
u_sm1_42 96.90 100.00 93.62 100.00 94.00
u_sm1_43 92.43 98.54 84.87 92.31 94.00
u_sm1_44 92.43 98.54 84.87 92.31 94.00
u_sm1_45 92.43 98.54 84.87 92.31 94.00
u_sm1_46 92.43 98.54 84.87 92.31 94.00
u_sm1_47 92.43 98.54 84.87 92.31 94.00
u_sm1_48 92.43 98.54 84.87 92.31 94.00
u_sm1_49 92.43 98.54 84.87 92.31 94.00
u_sm1_50 92.43 98.54 84.87 92.31 94.00
u_sm1_51 92.43 98.54 84.87 92.31 94.00
u_sm1_52 92.43 98.54 84.87 92.31 94.00
u_sm1_53 92.43 98.54 84.87 92.31 94.00
u_sm1_54 92.43 98.54 84.87 92.31 94.00
u_sm1_55 92.43 98.54 84.87 92.31 94.00
u_sm1_56 92.43 98.54 84.87 92.31 94.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : xbar_main
Line No.TotalCoveredPercent
TOTAL273273100.00
CONT_ASSIGN20700
CONT_ASSIGN42911100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN43511100.00
CONT_ASSIGN43611100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44111100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN44811100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN46511100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN46811100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47811100.00
CONT_ASSIGN48011100.00
CONT_ASSIGN48111100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN48411100.00
CONT_ASSIGN48611100.00
CONT_ASSIGN48711100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN49011100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49511100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49811100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50811100.00
CONT_ASSIGN51011100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51411100.00
CONT_ASSIGN51611100.00
CONT_ASSIGN51711100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52211100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN52811100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53411100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN54011100.00
CONT_ASSIGN54111100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN54411100.00
CONT_ASSIGN54611100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56211100.00
CONT_ASSIGN56411100.00
CONT_ASSIGN56511100.00
CONT_ASSIGN56711100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN57011100.00
CONT_ASSIGN57111100.00
CONT_ASSIGN57311100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58011100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58811100.00
CONT_ASSIGN58911100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59211100.00
CONT_ASSIGN59411100.00
CONT_ASSIGN59511100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
CONT_ASSIGN60011100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN60411100.00
CONT_ASSIGN60611100.00
CONT_ASSIGN60711100.00
CONT_ASSIGN60911100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN61311100.00
CONT_ASSIGN61511100.00
CONT_ASSIGN61611100.00
CONT_ASSIGN61811100.00
CONT_ASSIGN61911100.00
CONT_ASSIGN62111100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63011100.00
CONT_ASSIGN63111100.00
CONT_ASSIGN63311100.00
CONT_ASSIGN63411100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN63711100.00
CONT_ASSIGN63911100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN64311100.00
CONT_ASSIGN64511100.00
CONT_ASSIGN64611100.00
CONT_ASSIGN64811100.00
CONT_ASSIGN64911100.00
CONT_ASSIGN65111100.00
CONT_ASSIGN65211100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65511100.00
CONT_ASSIGN65711100.00
CONT_ASSIGN65811100.00
CONT_ASSIGN66011100.00
CONT_ASSIGN66111100.00
CONT_ASSIGN66311100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66611100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66911100.00
CONT_ASSIGN67011100.00
CONT_ASSIGN67211100.00
CONT_ASSIGN67311100.00
CONT_ASSIGN67511100.00
CONT_ASSIGN67611100.00
ALWAYS68099100.00
ALWAYS7014949100.00
ALWAYS8044949100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv' or '../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
207 excluded
429 1 1
430 1 1
432 1 1
433 1 1
435 1 1
436 1 1
438 1 1
439 1 1
441 1 1
442 1 1
444 1 1
445 1 1
447 1 1
448 1 1
450 1 1
451 1 1
453 1 1
454 1 1
456 1 1
457 1 1
459 1 1
460 1 1
462 1 1
463 1 1
465 1 1
466 1 1
468 1 1
469 1 1
471 1 1
472 1 1
474 1 1
475 1 1
477 1 1
478 1 1
480 1 1
481 1 1
483 1 1
484 1 1
486 1 1
487 1 1
489 1 1
490 1 1
492 1 1
493 1 1
495 1 1
496 1 1
498 1 1
499 1 1
501 1 1
502 1 1
504 1 1
505 1 1
507 1 1
508 1 1
510 1 1
511 1 1
513 1 1
514 1 1
516 1 1
517 1 1
519 1 1
520 1 1
522 1 1
523 1 1
525 1 1
526 1 1
528 1 1
529 1 1
531 1 1
532 1 1
534 1 1
535 1 1
537 1 1
538 1 1
540 1 1
541 1 1
543 1 1
544 1 1
546 1 1
547 1 1
549 1 1
550 1 1
552 1 1
553 1 1
555 1 1
556 1 1
558 1 1
559 1 1
561 1 1
562 1 1
564 1 1
565 1 1
567 1 1
568 1 1
570 1 1
571 1 1
573 1 1
574 1 1
576 1 1
577 1 1
579 1 1
580 1 1
582 1 1
583 1 1
585 1 1
586 1 1
588 1 1
589 1 1
591 1 1
592 1 1
594 1 1
595 1 1
597 1 1
598 1 1
600 1 1
601 1 1
603 1 1
604 1 1
606 1 1
607 1 1
609 1 1
610 1 1
612 1 1
613 1 1
615 1 1
616 1 1
618 1 1
619 1 1
621 1 1
622 1 1
624 1 1
625 1 1
627 1 1
628 1 1
630 1 1
631 1 1
633 1 1
634 1 1
636 1 1
637 1 1
639 1 1
640 1 1
642 1 1
643 1 1
645 1 1
646 1 1
648 1 1
649 1 1
651 1 1
652 1 1
654 1 1
655 1 1
657 1 1
658 1 1
660 1 1
661 1 1
663 1 1
664 1 1
666 1 1
667 1 1
669 1 1
670 1 1
672 1 1
673 1 1
675 1 1
676 1 1
680 1 1
681 1 1
683 1 1
685 1 1
687 1 1
689 1 1
691 1 1
693 1 1
695 1 1
MISSING_ELSE
701 1 1
702 1 1
704 1 1
706 1 1
708 1 1
710 1 1
712 1 1
714 1 1
716 1 1
718 1 1
720 1 1
722 1 1
726 1 1
728 1 1
730 1 1
732 1 1
734 1 1
736 1 1
738 1 1
740 1 1
742 1 1
744 1 1
746 1 1
748 1 1
750 1 1
752 1 1
754 1 1
756 1 1
758 1 1
760 1 1
762 1 1
764 1 1
766 1 1
768 1 1
770 1 1
772 1 1
774 1 1
776 1 1
778 1 1
780 1 1
782 1 1
784 1 1
786 1 1
788 1 1
790 1 1
792 1 1
794 1 1
796 1 1
798 1 1
MISSING_ELSE
804 1 1
805 1 1
807 1 1
809 1 1
811 1 1
813 1 1
815 1 1
817 1 1
819 1 1
821 1 1
823 1 1
825 1 1
829 1 1
831 1 1
833 1 1
835 1 1
837 1 1
839 1 1
841 1 1
843 1 1
845 1 1
847 1 1
849 1 1
851 1 1
853 1 1
855 1 1
857 1 1
859 1 1
861 1 1
863 1 1
865 1 1
867 1 1
869 1 1
871 1 1
873 1 1
875 1 1
877 1 1
879 1 1
881 1 1
883 1 1
885 1 1
887 1 1
889 1 1
891 1 1
893 1 1
895 1 1
897 1 1
899 1 1
901 1 1
MISSING_ELSE


Cond Coverage for Module : xbar_main
TotalCoveredPercent
Conditions114114100.00
Logical114114100.00
Non-Logical00
Event00

 LINE       681
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       685
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       689
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)
            --------------------------------------------------------------1--------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       693
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       702
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T4

 LINE       706
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__REGS)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__REGS)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       710
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       714
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__REGS)) == tl_main_pkg::ADDR_SPACE_RV_DM__REGS)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       718
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)
            --------------------------------------------------------------1--------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       722
 EXPRESSION 
 Number  Term
      1  ((tl_s1n_32_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000) || 
      2  ((tl_s1n_32_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T7
10CoveredT2,T3,T7

 LINE       722
 SUB-EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       722
 SUB-EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       728
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST0)) == tl_main_pkg::ADDR_SPACE_SPI_HOST0)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       732
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST1)) == tl_main_pkg::ADDR_SPACE_SPI_HOST1)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       736
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_USBDEV)) == tl_main_pkg::ADDR_SPACE_USBDEV)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       740
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__CORE)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__CORE)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       744
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__PRIM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__PRIM)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       748
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       752
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_AES)) == tl_main_pkg::ADDR_SPACE_AES)
            ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       756
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ENTROPY_SRC)) == tl_main_pkg::ADDR_SPACE_ENTROPY_SRC)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       760
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_CSRNG)) == tl_main_pkg::ADDR_SPACE_CSRNG)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       764
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN0)) == tl_main_pkg::ADDR_SPACE_EDN0)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       768
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN1)) == tl_main_pkg::ADDR_SPACE_EDN1)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       772
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_HMAC)) == tl_main_pkg::ADDR_SPACE_HMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       776
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_PLIC)) == tl_main_pkg::ADDR_SPACE_RV_PLIC)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       780
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_OTBN)) == tl_main_pkg::ADDR_SPACE_OTBN)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       784
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KEYMGR)) == tl_main_pkg::ADDR_SPACE_KEYMGR)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       788
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KMAC)) == tl_main_pkg::ADDR_SPACE_KMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       792
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__REGS)
            ---------------------------------------------------------------1---------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       796
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_CORE_IBEX__CFG)) == tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX__CFG)
            ------------------------------------------------------------1------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       805
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T4

 LINE       809
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__REGS)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__REGS)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       813
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       817
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__REGS)) == tl_main_pkg::ADDR_SPACE_RV_DM__REGS)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       821
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)
            --------------------------------------------------------------1--------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       825
 EXPRESSION 
 Number  Term
      1  ((tl_s1n_57_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000) || 
      2  ((tl_s1n_57_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T7
10CoveredT2,T3,T7

 LINE       825
 SUB-EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       825
 SUB-EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       831
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST0)) == tl_main_pkg::ADDR_SPACE_SPI_HOST0)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       835
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST1)) == tl_main_pkg::ADDR_SPACE_SPI_HOST1)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       839
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_USBDEV)) == tl_main_pkg::ADDR_SPACE_USBDEV)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       843
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__CORE)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__CORE)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       847
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__PRIM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__PRIM)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       851
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       855
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_AES)) == tl_main_pkg::ADDR_SPACE_AES)
            ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       859
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ENTROPY_SRC)) == tl_main_pkg::ADDR_SPACE_ENTROPY_SRC)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       863
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_CSRNG)) == tl_main_pkg::ADDR_SPACE_CSRNG)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       867
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN0)) == tl_main_pkg::ADDR_SPACE_EDN0)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       871
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN1)) == tl_main_pkg::ADDR_SPACE_EDN1)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       875
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_HMAC)) == tl_main_pkg::ADDR_SPACE_HMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       879
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_PLIC)) == tl_main_pkg::ADDR_SPACE_RV_PLIC)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       883
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_OTBN)) == tl_main_pkg::ADDR_SPACE_OTBN)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       887
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KEYMGR)) == tl_main_pkg::ADDR_SPACE_KEYMGR)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       891
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KMAC)) == tl_main_pkg::ADDR_SPACE_KMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       895
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__REGS)
            ---------------------------------------------------------------1---------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       899
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_CORE_IBEX__CFG)) == tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX__CFG)
            ------------------------------------------------------------1------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 604 580 96.03
Total Bits 7984 7888 98.80
Total Bits 0->1 3992 3944 98.80
Total Bits 1->0 3992 3944 98.80

Ports 604 580 96.03
Port Bits 7984 7888 98.80
Port Bits 0->1 3992 3944 98.80
Port Bits 1->0 3992 3944 98.80

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_fixed_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host0_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host1_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T17,T26,T23 Yes T1,T2,T3 INPUT
rst_fixed_ni Yes Yes T17,T26,T23 Yes T1,T2,T3 INPUT
rst_usb_ni Yes Yes T17,T26,T23 Yes T1,T2,T3 INPUT
rst_spi_host0_ni Yes Yes T17,T26,T23 Yes T1,T2,T3 INPUT
rst_spi_host1_ni Yes Yes T17,T26,T23 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.d_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] Yes Yes T3,T10,T11 Yes T3,T10,T11 INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Yes Yes T3,T10,T11 Yes T3,T10,T11 INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T3,T9,T4 Yes T3,T9,T4 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Yes Yes T3,T9,T4 Yes T3,T9,T4 INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0] Yes Yes T2,T3,T8 Yes T2,T3,T8 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Yes Yes T2,T3,T8 Yes T2,T3,T9 INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_dm__regs_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[3:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_rv_dm__regs_o.a_address[20:4] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_address[21] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[23:22] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_error Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_sink Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_address[15:12] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_address[31:17] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[15:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:16] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0] Yes Yes T3,T7,T4 Yes T3,T7,T4 OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[5:0] Yes Yes T3,T7,T9 Yes T3,T7,T9 INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_address[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_address[16:7] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_address[20:17] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_address[24] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_error Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_sink Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T2,T3,T7 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_o.d_ready Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_peri_o.a_user.rsvd[4:3] No No No OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_address[22:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[2:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_peri_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_peri_i.d_error Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_sink Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_source[5:0] Yes Yes T3,T7,T8 Yes T2,T3,T7 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_spi_host0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:3] No No No OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[19:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_address[21:20] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[29:22] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_error Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:3] No No No OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_spi_host1_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[19:17] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_address[21:20] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[29:22] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_usbdev_o.a_user.rsvd[4:3] No No No OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[16:12] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_address[21:20] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[29:22] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:3] No No No OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[8:0] Yes Yes T1,*T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[23:9] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[1:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 INPUT
tl_flash_ctrl__core_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[1:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T1,*T3,*T7 Yes T1,T3,T7 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:3] No No No OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[14:7] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_address[15] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[23:16] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:3] No No No OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[19:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[28:20] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_address[29] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:30] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[5:0] Yes Yes T1,*T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_hmac_o.a_user.rsvd[4:3] No No No OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[12:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[15:13] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[19:17] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[1:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_hmac_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_o.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_kmac_o.a_user.rsvd[4:3] No No No OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_address[11:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_address[16:12] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[17] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[20] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[24] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[2:0] Yes Yes T3,T7,T9 Yes T3,T7,T9 OUTPUT
tl_kmac_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_kmac_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_kmac_i.d_error Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_kmac_i.d_user.rsp_intg[6:0] Yes Yes T3,T7,T9 Yes T2,T3,T7 INPUT
tl_kmac_i.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_kmac_i.d_sink Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_kmac_i.d_source[5:0] Yes Yes T3,T7,T9 Yes T2,T3,T7 INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_o.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_aes_o.a_user.rsvd[4:3] No No No OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_address[7:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_address[19:8] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_address[20] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_address[24] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[2:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_aes_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_aes_i.d_error Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_sink Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_source[5:0] Yes Yes T3,T7,T9 Yes T2,T3,T7 INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_entropy_src_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:3] No No No OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[16:8] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_csrng_o.a_user.rsvd[4:3] No No No OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_csrng_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_edn0_o.a_user.rsvd[4:3] No No No OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_edn0_i.d_error Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_edn1_o.a_user.rsvd[4:3] No No No OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[18:7] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_address[20:19] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_edn1_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_o.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_address[27:0] Yes Yes T3,T7,T4 Yes T3,T7,T4 OUTPUT
tl_rv_plic_o.a_address[29:28] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[2:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_error Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_plic_i.d_sink Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_source[5:0] Yes Yes T3,T7,T4 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_o.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_otbn_o.a_user.rsvd[4:3] No No No OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_address[17:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_address[20] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_address[24] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[2:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_otbn_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_otbn_i.d_error Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_i.d_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_i.d_sink Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_i.d_source[5:0] Yes Yes T3,T7,T9 Yes T2,T3,T7 INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T3,T7,T9 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_keymgr_o.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_keymgr_o.a_user.rsvd[4:3] No No No OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_address[7:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_address[17:8] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[18] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[20] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[24] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[30] Yes Yes *T2,*T3,*T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[5:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[1:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[2:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_o.a_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_keymgr_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_error Yes Yes T3,T7,T9 Yes T3,T7,T9 INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_keymgr_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T2,T3,T7 INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T2,T3,T7 INPUT
tl_keymgr_i.d_sink Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_keymgr_i.d_source[5:0] Yes Yes T3,T7,T9 Yes T2,T3,T7 INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[1:0] Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[15:8] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_address[20:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_sink Yes Yes T1,T2,T3 Yes T1,T3,T7 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:3] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[17:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0] Yes Yes T1,*T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[2:0] Yes Yes T10,T11,T15 Yes T10,T11,T15 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:3] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[16:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[27:17] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:29] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T1,T2,T7 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0] Yes Yes T1,*T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : xbar_main
Line No.TotalCoveredPercent
Branches 55 55 100.00
IF 681 5 5 100.00
IF 702 25 25 100.00
IF 805 25 25 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv' or '../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 681 if (((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)) -2-: 685 if (((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)) -3-: 689 if (((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)) -4-: 693 if (((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 702 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)) -2-: 706 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__REGS)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__REGS)) -3-: 710 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)) -4-: 714 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__REGS)) == tl_main_pkg::ADDR_SPACE_RV_DM__REGS)) -5-: 718 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)) -6-: 722 if ((((tl_s1n_32_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000) || ((tl_s1n_32_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000))) -7-: 728 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST0)) == tl_main_pkg::ADDR_SPACE_SPI_HOST0)) -8-: 732 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST1)) == tl_main_pkg::ADDR_SPACE_SPI_HOST1)) -9-: 736 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_USBDEV)) == tl_main_pkg::ADDR_SPACE_USBDEV)) -10-: 740 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__CORE)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__CORE)) -11-: 744 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__PRIM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__PRIM)) -12-: 748 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)) -13-: 752 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_AES)) == tl_main_pkg::ADDR_SPACE_AES)) -14-: 756 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ENTROPY_SRC)) == tl_main_pkg::ADDR_SPACE_ENTROPY_SRC)) -15-: 760 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_CSRNG)) == tl_main_pkg::ADDR_SPACE_CSRNG)) -16-: 764 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN0)) == tl_main_pkg::ADDR_SPACE_EDN0)) -17-: 768 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN1)) == tl_main_pkg::ADDR_SPACE_EDN1)) -18-: 772 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_HMAC)) == tl_main_pkg::ADDR_SPACE_HMAC)) -19-: 776 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_PLIC)) == tl_main_pkg::ADDR_SPACE_RV_PLIC)) -20-: 780 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_OTBN)) == tl_main_pkg::ADDR_SPACE_OTBN)) -21-: 784 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KEYMGR)) == tl_main_pkg::ADDR_SPACE_KEYMGR)) -22-: 788 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KMAC)) == tl_main_pkg::ADDR_SPACE_KMAC)) -23-: 792 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__REGS)) -24-: 796 if (((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_CORE_IBEX__CFG)) == tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX__CFG))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24-StatusTests
1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 805 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)) -2-: 809 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__REGS)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__REGS)) -3-: 813 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)) -4-: 817 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__REGS)) == tl_main_pkg::ADDR_SPACE_RV_DM__REGS)) -5-: 821 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)) -6-: 825 if ((((tl_s1n_57_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000) || ((tl_s1n_57_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000))) -7-: 831 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST0)) == tl_main_pkg::ADDR_SPACE_SPI_HOST0)) -8-: 835 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST1)) == tl_main_pkg::ADDR_SPACE_SPI_HOST1)) -9-: 839 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_USBDEV)) == tl_main_pkg::ADDR_SPACE_USBDEV)) -10-: 843 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__CORE)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__CORE)) -11-: 847 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__PRIM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__PRIM)) -12-: 851 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)) -13-: 855 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_AES)) == tl_main_pkg::ADDR_SPACE_AES)) -14-: 859 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ENTROPY_SRC)) == tl_main_pkg::ADDR_SPACE_ENTROPY_SRC)) -15-: 863 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_CSRNG)) == tl_main_pkg::ADDR_SPACE_CSRNG)) -16-: 867 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN0)) == tl_main_pkg::ADDR_SPACE_EDN0)) -17-: 871 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN1)) == tl_main_pkg::ADDR_SPACE_EDN1)) -18-: 875 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_HMAC)) == tl_main_pkg::ADDR_SPACE_HMAC)) -19-: 879 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_PLIC)) == tl_main_pkg::ADDR_SPACE_RV_PLIC)) -20-: 883 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_OTBN)) == tl_main_pkg::ADDR_SPACE_OTBN)) -21-: 887 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KEYMGR)) == tl_main_pkg::ADDR_SPACE_KEYMGR)) -22-: 891 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KMAC)) == tl_main_pkg::ADDR_SPACE_KMAC)) -23-: 895 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__REGS)) -24-: 899 if (((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_CORE_IBEX__CFG)) == tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX__CFG))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24-StatusTests
1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T3,T7
0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Covered T1,T2,T3

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