Unified Coverage Report :: Module :: tlul_socket_m1

Module : tlul_socket_m1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45				100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28	95.96	100.00	87.88				100.00
tb.dut.u_sm1_29	95.96	100.00	87.88				100.00
tb.dut.u_sm1_31	95.96	100.00	87.88				100.00
tb.dut.u_sm1_33	96.97	100.00	90.91				100.00
tb.dut.u_sm1_34	96.97	100.00	90.91				100.00
tb.dut.u_sm1_36	96.97	100.00	90.91				100.00
tb.dut.u_sm1_38	96.97	100.00	90.91				100.00
tb.dut.u_sm1_40	96.97	100.00	90.91				100.00
tb.dut.u_sm1_42	96.97	100.00	90.91				100.00
tb.dut.u_sm1_43	96.97	100.00	90.91				100.00
tb.dut.u_sm1_44	96.97	100.00	90.91				100.00
tb.dut.u_sm1_45	96.97	100.00	90.91				100.00
tb.dut.u_sm1_46	96.97	100.00	90.91				100.00
tb.dut.u_sm1_47	96.97	100.00	90.91				100.00
tb.dut.u_sm1_48	96.97	100.00	90.91				100.00
tb.dut.u_sm1_49	96.97	100.00	90.91				100.00
tb.dut.u_sm1_50	96.97	100.00	90.91				100.00
tb.dut.u_sm1_51	96.97	100.00	90.91				100.00
tb.dut.u_sm1_52	96.97	100.00	90.91				100.00
tb.dut.u_sm1_53	96.97	100.00	90.91				100.00
tb.dut.u_sm1_54	96.97	100.00	90.91				100.00
tb.dut.u_sm1_55	96.97	100.00	90.91				100.00
tb.dut.u_sm1_56	96.97	100.00	90.91				100.00
tb.dut.u_sm1_30	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sm1_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.51	98.68	85.92			92.73	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	92.21	97.50	82.14			89.19	100.00

---

Module Instance : tb.dut.u_sm1_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78	100.00	98.39			100.00	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_28

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_29

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	3	3
105	3	3
108	3	3
163	3	3
166	1	1
212	1	1
213	1	1
231	1	1
236	3	3
238	3	3
242	3	3

---

Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_33

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_34

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_36

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_38

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_40

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_42

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_43

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_44

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_45

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_46

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_47

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_48

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_49

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_50

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_51

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_52

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_53

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_54

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_55

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
95.96	87.88

tb.dut.u_sm1_28

SCORE	COND
95.96	87.88

tb.dut.u_sm1_29

SCORE	COND
95.96	87.88

tb.dut.u_sm1_31

SCORE	COND
100.00	100.00

tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.97	90.91

tb.dut.u_sm1_33

SCORE	COND
96.97	90.91

tb.dut.u_sm1_34

SCORE	COND
96.97	90.91

tb.dut.u_sm1_43

SCORE	COND
96.97	90.91

tb.dut.u_sm1_44

SCORE	COND
96.97	90.91

tb.dut.u_sm1_45

SCORE	COND
96.97	90.91

tb.dut.u_sm1_46

SCORE	COND
96.97	90.91

tb.dut.u_sm1_47

SCORE	COND
96.97	90.91

tb.dut.u_sm1_48

SCORE	COND
96.97	90.91

tb.dut.u_sm1_49

SCORE	COND
96.97	90.91

tb.dut.u_sm1_50

SCORE	COND
96.97	90.91

tb.dut.u_sm1_51

SCORE	COND
96.97	90.91

tb.dut.u_sm1_52

SCORE	COND
96.97	90.91

tb.dut.u_sm1_53

SCORE	COND
96.97	90.91

tb.dut.u_sm1_54

SCORE	COND
96.97	90.91

tb.dut.u_sm1_55

SCORE	COND
96.97	90.91

tb.dut.u_sm1_56

SCORE	COND
96.97	90.91

tb.dut.u_sm1_36

SCORE	COND
96.97	90.91

tb.dut.u_sm1_38

SCORE	COND
96.97	90.91

tb.dut.u_sm1_40

SCORE	COND
96.97	90.91

tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_m1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	2147483647	21699012	0	0
gen_host_fifo[1].idInRange	2147483647	12468991	0	0
gen_host_fifo[2].idInRange	1587624096	3623563	0	0
maxM	21600	21600	0	0
rspIdInRange	2147483647	154362447	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21699012	0	0
T1	738552	4483	0	0
T2	6073848	354	0	0
T3	4098768	18648	0	0
T7	14301456	115511	0	0
T8	10728360	411	0	0
T9	224040	2287	0	0
T10	19132320	3613	0	0
T11	184464	4736	0	0
T12	229176	3818	0	0
T13	21979536	79742	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12468991	0	0
T1	738552	2031	0	0
T2	6073848	167	0	0
T3	4098768	6795	0	0
T7	14301456	87634	0	0
T8	10728360	339	0	0
T9	224040	1391	0	0
T10	19132320	1579	0	0
T11	184464	2573	0	0
T12	229176	2147	0	0
T13	21979536	26906	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587624096	3623563	0	0
T1	123092	556	0	0
T2	1012308	61	0	0
T3	683128	4205	0	0
T7	2383576	32837	0	0
T8	1788060	43	0	0
T9	37340	184	0	0
T10	3188720	360	0	0
T11	30744	137	0	0
T12	38196	312	0	0
T13	3663256	14747	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	154362447	0	0
T1	738552	16785	0	0
T2	6073848	90035	0	0
T3	4098768	32482	0	0
T7	14301456	295649	0	0
T8	10728360	126002	0	0
T9	224040	3285	0	0
T10	19132320	200907	0	0
T11	184464	5317	0	0
T12	229176	5131	0	0
T13	21979536	304021	0	0

Line Coverage for Instance : tb.dut.u_sm1_28

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	3	3
105	3	3
108	3	3
163	3	3
166	1	1
212	1	1
213	1	1
231	1	1
236	3	3
238	3	3
242	3	3

---

Cond Coverage for Instance : tb.dut.u_sm1_28

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	1635308	0	0
gen_host_fifo[1].idInRange	396906024	449305	0	0
gen_host_fifo[2].idInRange	396906024	574727	0	0
maxM	900	900	0	0
rspIdInRange	396906024	19578737	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1635308	0	0
T1	30773	378	0	0
T2	253077	51	0	0
T3	170782	1029	0	0
T7	595894	10806	0	0
T8	447015	32	0	0
T9	9335	272	0	0
T10	797180	409	0	0
T11	7686	490	0	0
T12	9549	416	0	0
T13	915814	4161	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	449305	0	0
T1	30773	58	0	0
T2	253077	6	0	0
T3	170782	859	0	0
T7	595894	2938	0	0
T8	447015	6	0	0
T9	9335	40	0	0
T10	797180	50	0	0
T11	7686	51	0	0
T12	9549	72	0	0
T13	915814	764	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	574727	0	0
T1	30773	61	0	0
T2	253077	8	0	0
T3	170782	982	0	0
T7	595894	6682	0	0
T8	447015	8	0	0
T9	9335	56	0	0
T10	797180	74	0	0
T11	7686	38	0	0
T12	9549	78	0	0
T13	915814	1046	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	19578737	0	0
T1	30773	2069	0	0
T2	253077	15652	0	0
T3	170782	3748	0	0
T7	595894	44752	0	0
T8	447015	12087	0	0
T9	9335	364	0	0
T10	797180	9745	0	0
T11	7686	569	0	0
T12	9549	557	0	0
T13	915814	58509	0	0

Line Coverage for Instance : tb.dut.u_sm1_29

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	3	3
105	3	3
108	3	3
163	3	3
166	1	1
212	1	1
213	1	1
231	1	1
236	3	3
238	3	3
242	3	3

---

Cond Coverage for Instance : tb.dut.u_sm1_29

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	1775240	0	0
gen_host_fifo[1].idInRange	396906024	516929	0	0
gen_host_fifo[2].idInRange	396906024	652224	0	0
maxM	900	900	0	0
rspIdInRange	396906024	17800032	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1775240	0	0
T1	30773	464	0	0
T2	253077	32	0	0
T3	170782	1573	0	0
T7	595894	10192	0	0
T8	447015	40	0	0
T9	9335	315	0	0
T10	797180	452	0	0
T11	7686	598	0	0
T12	9549	620	0	0
T13	915814	4778	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	516929	0	0
T1	30773	101	0	0
T2	253077	2	0	0
T3	170782	91	0	0
T7	595894	4453	0	0
T8	447015	8	0	0
T9	9335	45	0	0
T10	797180	67	0	0
T11	7686	35	0	0
T12	9549	98	0	0
T13	915814	561	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	652224	0	0
T1	30773	80	0	0
T2	253077	9	0	0
T3	170782	430	0	0
T7	595894	5031	0	0
T8	447015	4	0	0
T9	9335	55	0	0
T10	797180	54	0	0
T11	7686	30	0	0
T12	9549	87	0	0
T13	915814	1523	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	17800032	0	0
T1	30773	2036	0	0
T2	253077	10285	0	0
T3	170782	3825	0	0
T7	595894	44999	0	0
T8	447015	12647	0	0
T9	9335	354	0	0
T10	797180	7071	0	0
T11	7686	549	0	0
T12	9549	603	0	0
T13	915814	64151	0	0

Line Coverage for Instance : tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	3	3
105	3	3
108	3	3
163	3	3
166	1	1
212	1	1
213	1	1
231	1	1
236	3	3
238	3	3
242	3	3

---

Cond Coverage for Instance : tb.dut.u_sm1_31

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	1741246	0	0
gen_host_fifo[1].idInRange	396906024	480511	0	0
gen_host_fifo[2].idInRange	396906024	611280	0	0
maxM	900	900	0	0
rspIdInRange	396906024	18315887	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1741246	0	0
T1	30773	427	0	0
T2	253077	48	0	0
T3	170782	1120	0	0
T7	595894	15623	0	0
T8	447015	72	0	0
T9	9335	291	0	0
T10	797180	351	0	0
T11	7686	616	0	0
T12	9549	498	0	0
T13	915814	3181	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	480511	0	0
T1	30773	52	0	0
T2	253077	5	0	0
T3	170782	608	0	0
T7	595894	10790	0	0
T8	447015	7	0	0
T9	9335	62	0	0
T10	797180	42	0	0
T11	7686	56	0	0
T12	9549	81	0	0
T13	915814	13	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	611280	0	0
T1	30773	65	0	0
T2	253077	3	0	0
T3	170782	1102	0	0
T7	595894	14056	0	0
T8	447015	9	0	0
T9	9335	34	0	0
T10	797180	51	0	0
T11	7686	38	0	0
T12	9549	73	0	0
T13	915814	3010	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	18315887	0	0
T1	30773	2141	0	0
T2	253077	17471	0	0
T3	170782	4069	0	0
T7	595894	42113	0	0
T8	447015	16419	0	0
T9	9335	337	0	0
T10	797180	9869	0	0
T11	7686	577	0	0
T12	9549	522	0	0
T13	915814	63670	0	0

Line Coverage for Instance : tb.dut.u_sm1_33

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_33

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	307558	0	0
gen_host_fifo[1].idInRange	396906024	383698	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3819235	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	307558	0	0
T1	30773	48	0	0
T2	253077	11	0	0
T3	170782	965	0	0
T7	595894	2467	0	0
T8	447015	6	0	0
T9	9335	60	0	0
T10	797180	60	0	0
T11	7686	861	0	0
T12	9549	70	0	0
T13	915814	61	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	383698	0	0
T1	30773	77	0	0
T2	253077	4	0	0
T3	170782	8	0	0
T7	595894	2742	0	0
T8	447015	8	0	0
T9	9335	60	0	0
T10	797180	71	0	0
T11	7686	723	0	0
T12	9549	78	0	0
T13	915814	606	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3819235	0	0
T1	30773	440	0	0
T2	253077	1849	0	0
T3	170782	1989	0	0
T7	595894	5498	0	0
T8	447015	3049	0	0
T9	9335	112	0	0
T10	797180	12319	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	2520	0	0

Line Coverage for Instance : tb.dut.u_sm1_34

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_34

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	304485	0	0
gen_host_fifo[1].idInRange	396906024	389636	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3684870	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	304485	0	0
T1	30773	80	0	0
T2	253077	10	0	0
T3	170782	11	0	0
T7	595894	2198	0	0
T8	447015	8	0	0
T9	9335	37	0	0
T10	797180	53	0	0
T11	7686	507	0	0
T12	9549	74	0	0
T13	915814	489	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	389636	0	0
T1	30773	67	0	0
T2	253077	8	0	0
T3	170782	1086	0	0
T7	595894	3252	0	0
T8	447015	15	0	0
T9	9335	46	0	0
T10	797180	63	0	0
T11	7686	458	0	0
T12	9549	85	0	0
T13	915814	1189	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3684870	0	0
T1	30773	485	0	0
T2	253077	4439	0	0
T3	170782	658	0	0
T7	595894	5499	0	0
T8	447015	4829	0	0
T9	9335	80	0	0
T10	797180	7983	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	4433	0	0

Line Coverage for Instance : tb.dut.u_sm1_36

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_36

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	708637	0	0
gen_host_fifo[1].idInRange	396906024	832422	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3769867	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	708637	0	0
T1	30773	85	0	0
T2	253077	27	0	0
T3	170782	67	0	0
T7	595894	406	0	0
T8	447015	27	0	0
T9	9335	79	0	0
T10	797180	52	0	0
T11	7686	110	0	0
T12	9549	139	0	0
T13	915814	562	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	832422	0	0
T1	30773	164	0	0
T2	253077	32	0	0
T3	170782	7	0	0
T7	595894	453	0	0
T8	447015	125	0	0
T9	9335	61	0	0
T10	797180	51	0	0
T11	7686	106	0	0
T12	9549	113	0	0
T13	915814	2996	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3769867	0	0
T1	30773	427	0	0
T2	253077	3504	0	0
T3	170782	1293	0	0
T7	595894	3114	0	0
T8	447015	3413	0	0
T9	9335	86	0	0
T10	797180	2999	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	4627	0	0

Line Coverage for Instance : tb.dut.u_sm1_38

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_38

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	778708	0	0
gen_host_fifo[1].idInRange	396906024	853436	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4267662	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	778708	0	0
T1	30773	45	0	0
T2	253077	4	0	0
T3	170782	4	0	0
T7	595894	418	0	0
T8	447015	9	0	0
T9	9335	60	0	0
T10	797180	65	0	0
T11	7686	46	0	0
T12	9549	204	0	0
T13	915814	15	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853436	0	0
T1	30773	49	0	0
T2	253077	2	0	0
T3	170782	2	0	0
T7	595894	484	0	0
T8	447015	3	0	0
T9	9335	125	0	0
T10	797180	87	0	0
T11	7686	38	0	0
T12	9549	141	0	0
T13	915814	2277	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4267662	0	0
T1	30773	487	0	0
T2	253077	1263	0	0
T3	170782	6	0	0
T7	595894	3340	0	0
T8	447015	2483	0	0
T9	9335	96	0	0
T10	797180	16070	0	0
T11	7686	73	0	0
T12	9549	149	0	0
T13	915814	885	0	0

Line Coverage for Instance : tb.dut.u_sm1_40

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_40

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	700121	0	0
gen_host_fifo[1].idInRange	396906024	805858	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4547612	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	700121	0	0
T1	30773	68	0	0
T2	253077	1	0	0
T3	170782	4	0	0
T7	595894	1557	0	0
T8	447015	7	0	0
T9	9335	134	0	0
T10	797180	60	0	0
T11	7686	35	0	0
T12	9549	142	0	0
T13	915814	2393	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	805858	0	0
T1	30773	40	0	0
T2	253077	3	0	0
T3	170782	457	0	0
T7	595894	1821	0	0
T8	447015	7	0	0
T9	9335	161	0	0
T10	797180	73	0	0
T11	7686	29	0	0
T12	9549	121	0	0
T13	915814	183	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4547612	0	0
T1	30773	496	0	0
T2	253077	767	0	0
T3	170782	501	0	0
T7	595894	9180	0	0
T8	447015	3076	0	0
T9	9335	106	0	0
T10	797180	16020	0	0
T11	7686	62	0	0
T12	9549	132	0	0
T13	915814	1385	0	0

Line Coverage for Instance : tb.dut.u_sm1_42

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	670103	0	0
gen_host_fifo[1].idInRange	396906024	787215	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4490268	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	670103	0	0
T1	30773	53	0	0
T2	253077	5	0	0
T3	170782	6	0	0
T7	595894	4724	0	0
T8	447015	5	0	0
T9	9335	81	0	0
T10	797180	59	0	0
T11	7686	35	0	0
T12	9549	190	0	0
T13	915814	413	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	787215	0	0
T1	30773	115	0	0
T2	253077	3	0	0
T3	170782	5	0	0
T7	595894	6120	0	0
T8	447015	4	0	0
T9	9335	63	0	0
T10	797180	68	0	0
T11	7686	37	0	0
T12	9549	215	0	0
T13	915814	4797	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4490268	0	0
T1	30773	347	0	0
T2	253077	2672	0	0
T3	170782	405	0	0
T7	595894	5992	0	0
T8	447015	2491	0	0
T9	9335	86	0	0
T10	797180	16739	0	0
T11	7686	64	0	0
T12	9549	179	0	0
T13	915814	2909	0	0

Line Coverage for Instance : tb.dut.u_sm1_43

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_43

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	315467	0	0
gen_host_fifo[1].idInRange	396906024	398960	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4288237	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	315467	0	0
T1	30773	50	0	0
T2	253077	4	0	0
T3	170782	660	0	0
T7	595894	4886	0	0
T8	447015	8	0	0
T9	9335	54	0	0
T10	797180	74	0	0
T11	7686	29	0	0
T12	9549	88	0	0
T13	915814	50	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	398960	0	0
T1	30773	96	0	0
T2	253077	5	0	0
T3	170782	6	0	0
T7	595894	6869	0	0
T8	447015	12	0	0
T9	9335	50	0	0
T10	797180	80	0	0
T11	7686	27	0	0
T12	9549	79	0	0
T13	915814	62	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4288237	0	0
T1	30773	402	0	0
T2	253077	2103	0	0
T3	170782	818	0	0
T7	595894	7825	0	0
T8	447015	4770	0	0
T9	9335	99	0	0
T10	797180	14390	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	1563	0	0

Line Coverage for Instance : tb.dut.u_sm1_44

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_44

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	335155	0	0
gen_host_fifo[1].idInRange	396906024	439123	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4438786	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	335155	0	0
T1	30773	46	0	0
T2	253077	6	0	0
T3	170782	12	0	0
T7	595894	2642	0	0
T8	447015	7	0	0
T9	9335	49	0	0
T10	797180	51	0	0
T11	7686	61	0	0
T12	9549	67	0	0
T13	915814	336	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	439123	0	0
T1	30773	71	0	0
T2	253077	15	0	0
T3	170782	264	0	0
T7	595894	3968	0	0
T8	447015	26	0	0
T9	9335	59	0	0
T10	797180	47	0	0
T11	7686	33	0	0
T12	9549	77	0	0
T13	915814	753	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4438786	0	0
T1	30773	394	0	0
T2	253077	1561	0	0
T3	170782	504	0	0
T7	595894	7988	0	0
T8	447015	4369	0	0
T9	9335	105	0	0
T10	797180	5958	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	3388	0	0

Line Coverage for Instance : tb.dut.u_sm1_45

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_45

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	278587	0	0
gen_host_fifo[1].idInRange	396906024	354349	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3961089	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	278587	0	0
T1	30773	73	0	0
T2	253077	6	0	0
T3	170782	168	0	0
T7	595894	501	0	0
T8	447015	3	0	0
T9	9335	48	0	0
T10	797180	39	0	0
T11	7686	44	0	0
T12	9549	69	0	0
T13	915814	185	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	354349	0	0
T1	30773	82	0	0
T2	253077	4	0	0
T3	170782	4	0	0
T7	595894	453	0	0
T8	447015	5	0	0
T9	9335	45	0	0
T10	797180	62	0	0
T11	7686	29	0	0
T12	9549	70	0	0
T13	915814	385	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3961089	0	0
T1	30773	402	0	0
T2	253077	3110	0	0
T3	170782	828	0	0
T7	595894	3605	0	0
T8	447015	2436	0	0
T9	9335	90	0	0
T10	797180	5892	0	0
T11	7686	71	0	0
T12	9549	134	0	0
T13	915814	3234	0	0

Line Coverage for Instance : tb.dut.u_sm1_46

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_46

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	317829	0	0
gen_host_fifo[1].idInRange	396906024	413625	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4014728	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	317829	0	0
T1	30773	33	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	4538	0	0
T8	447015	2	0	0
T9	9335	45	0	0
T10	797180	63	0	0
T11	7686	35	0	0
T12	9549	67	0	0
T13	915814	20	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	413625	0	0
T1	30773	28	0	0
T2	253077	11	0	0
T3	170782	7	0	0
T7	595894	7006	0	0
T8	447015	7	0	0
T9	9335	43	0	0
T10	797180	38	0	0
T11	7686	29	0	0
T12	9549	68	0	0
T13	915814	1176	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4014728	0	0
T1	30773	283	0	0
T2	253077	1676	0	0
T3	170782	390	0	0
T7	595894	8739	0	0
T8	447015	1873	0	0
T9	9335	85	0	0
T10	797180	6043	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	2150	0	0

Line Coverage for Instance : tb.dut.u_sm1_47

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_47

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	271264	0	0
gen_host_fifo[1].idInRange	396906024	354968	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3689660	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	271264	0	0
T1	30773	45	0	0
T2	253077	2	0	0
T3	170782	9	0	0
T7	595894	4540	0	0
T8	447015	5	0	0
T9	9335	37	0	0
T10	797180	43	0	0
T11	7686	270	0	0
T12	9549	84	0	0
T13	915814	1016	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	354968	0	0
T1	30773	61	0	0
T2	253077	6	0	0
T3	170782	5	0	0
T7	595894	5717	0	0
T8	447015	4	0	0
T9	9335	46	0	0
T10	797180	53	0	0
T11	7686	413	0	0
T12	9549	72	0	0
T13	915814	522	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3689660	0	0
T1	30773	321	0	0
T2	253077	550	0	0
T3	170782	437	0	0
T7	595894	5583	0	0
T8	447015	3902	0	0
T9	9335	81	0	0
T10	797180	7369	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	4961	0	0

Line Coverage for Instance : tb.dut.u_sm1_48

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_48

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	289416	0	0
gen_host_fifo[1].idInRange	396906024	388062	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3420003	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	289416	0	0
T1	30773	66	0	0
T2	253077	5	0	0
T3	170782	11	0	0
T7	595894	931	0	0
T8	447015	8	0	0
T9	9335	47	0	0
T10	797180	67	0	0
T11	7686	49	0	0
T12	9549	84	0	0
T13	915814	209	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	388062	0	0
T1	30773	57	0	0
T2	253077	4	0	0
T3	170782	10	0	0
T7	595894	1331	0	0
T8	447015	15	0	0
T9	9335	44	0	0
T10	797180	68	0	0
T11	7686	43	0	0
T12	9549	71	0	0
T13	915814	20	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3420003	0	0
T1	30773	433	0	0
T2	253077	1876	0	0
T3	170782	1094	0	0
T7	595894	5011	0	0
T8	447015	3289	0	0
T9	9335	88	0	0
T10	797180	8556	0	0
T11	7686	89	0	0
T12	9549	144	0	0
T13	915814	3812	0	0

Line Coverage for Instance : tb.dut.u_sm1_49

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_49

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	290361	0	0
gen_host_fifo[1].idInRange	396906024	375338	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3626445	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	290361	0	0
T1	30773	65	0	0
T2	253077	8	0	0
T3	170782	8	0	0
T7	595894	3876	0	0
T8	447015	6	0	0
T9	9335	47	0	0
T10	797180	45	0	0
T11	7686	43	0	0
T12	9549	88	0	0
T13	915814	22	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	375338	0	0
T1	30773	70	0	0
T2	253077	5	0	0
T3	170782	53	0	0
T7	595894	4955	0	0
T8	447015	6	0	0
T9	9335	44	0	0
T10	797180	49	0	0
T11	7686	36	0	0
T12	9549	102	0	0
T13	915814	449	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3626445	0	0
T1	30773	434	0	0
T2	253077	1622	0	0
T3	170782	494	0	0
T7	595894	9272	0	0
T8	447015	4251	0	0
T9	9335	90	0	0
T10	797180	5016	0	0
T11	7686	75	0	0
T12	9549	178	0	0
T13	915814	4201	0	0

Line Coverage for Instance : tb.dut.u_sm1_50

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_50

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	323451	0	0
gen_host_fifo[1].idInRange	396906024	411576	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4080374	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	323451	0	0
T1	30773	61	0	0
T2	253077	4	0	0
T3	170782	4	0	0
T7	595894	421	0	0
T8	447015	9	0	0
T9	9335	49	0	0
T10	797180	77	0	0
T11	7686	40	0	0
T12	9549	61	0	0
T13	915814	543	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	411576	0	0
T1	30773	61	0	0
T2	253077	5	0	0
T3	170782	5	0	0
T7	595894	515	0	0
T8	447015	5	0	0
T9	9335	42	0	0
T10	797180	53	0	0
T11	7686	40	0	0
T12	9549	67	0	0
T13	915814	737	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4080374	0	0
T1	30773	357	0	0
T2	253077	1538	0	0
T3	170782	353	0	0
T7	595894	3501	0	0
T8	447015	3756	0	0
T9	9335	89	0	0
T10	797180	8119	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	2931	0	0

Line Coverage for Instance : tb.dut.u_sm1_51

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_51

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	304535	0	0
gen_host_fifo[1].idInRange	396906024	389789	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3781954	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	304535	0	0
T1	30773	66	0	0
T2	253077	3	0	0
T3	170782	11	0	0
T7	595894	1601	0	0
T8	447015	8	0	0
T9	9335	85	0	0
T10	797180	58	0	0
T11	7686	54	0	0
T12	9549	83	0	0
T13	915814	568	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	389789	0	0
T1	30773	55	0	0
T2	253077	6	0	0
T3	170782	5	0	0
T7	595894	1953	0	0
T8	447015	3	0	0
T9	9335	79	0	0
T10	797180	60	0	0
T11	7686	57	0	0
T12	9549	81	0	0
T13	915814	429	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3781954	0	0
T1	30773	436	0	0
T2	253077	579	0	0
T3	170782	2047	0	0
T7	595894	8083	0	0
T8	447015	1539	0	0
T9	9335	157	0	0
T10	797180	5580	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	3043	0	0

Line Coverage for Instance : tb.dut.u_sm1_52

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_52

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	279982	0	0
gen_host_fifo[1].idInRange	396906024	386999	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3565116	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	279982	0	0
T1	30773	65	0	0
T2	253077	8	0	0
T3	170782	7	0	0
T7	595894	1158	0	0
T8	447015	11	0	0
T9	9335	45	0	0
T10	797180	54	0	0
T11	7686	38	0	0
T12	9549	83	0	0
T13	915814	577	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	386999	0	0
T1	30773	36	0	0
T2	253077	5	0	0
T3	170782	9	0	0
T7	595894	3022	0	0
T8	447015	11	0	0
T9	9335	53	0	0
T10	797180	41	0	0
T11	7686	35	0	0
T12	9549	72	0	0
T13	915814	1497	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3565116	0	0
T1	30773	331	0	0
T2	253077	3232	0	0
T3	170782	100	0	0
T7	595894	5931	0	0
T8	447015	7393	0	0
T9	9335	92	0	0
T10	797180	6114	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	4830	0	0

Line Coverage for Instance : tb.dut.u_sm1_53

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_53

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	249159	0	0
gen_host_fifo[1].idInRange	396906024	332503	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3627622	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	249159	0	0
T1	30773	79	0	0
T2	253077	6	0	0
T3	170782	6	0	0
T7	595894	3814	0	0
T8	447015	7	0	0
T9	9335	45	0	0
T10	797180	53	0	0
T11	7686	42	0	0
T12	9549	76	0	0
T13	915814	27	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	332503	0	0
T1	30773	54	0	0
T2	253077	9	0	0
T3	170782	8	0	0
T7	595894	4966	0	0
T8	447015	6	0	0
T9	9335	43	0	0
T10	797180	44	0	0
T11	7686	38	0	0
T12	9549	78	0	0
T13	915814	1804	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3627622	0	0
T1	30773	514	0	0
T2	253077	1273	0	0
T3	170782	500	0	0
T7	595894	5377	0	0
T8	447015	3485	0	0
T9	9335	84	0	0
T10	797180	4929	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	2253	0	0

Line Coverage for Instance : tb.dut.u_sm1_54

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_54

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	247600	0	0
gen_host_fifo[1].idInRange	396906024	329528	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3366632	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	247600	0	0
T1	30773	57	0	0
T2	253077	5	0	0
T3	170782	648	0	0
T7	595894	3324	0	0
T8	447015	10	0	0
T9	9335	49	0	0
T10	797180	59	0	0
T11	7686	135	0	0
T12	9549	75	0	0
T13	915814	116	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	329528	0	0
T1	30773	96	0	0
T2	253077	3	0	0
T3	170782	167	0	0
T7	595894	3801	0	0
T8	447015	6	0	0
T9	9335	43	0	0
T10	797180	63	0	0
T11	7686	145	0	0
T12	9549	81	0	0
T13	915814	144	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3366632	0	0
T1	30773	385	0	0
T2	253077	1141	0	0
T3	170782	233	0	0
T7	595894	5251	0	0
T8	447015	4670	0	0
T9	9335	90	0	0
T10	797180	5424	0	0
T11	7686	186	0	0
T12	9549	142	0	0
T13	915814	2214	0	0

Line Coverage for Instance : tb.dut.u_sm1_55

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_55

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	246572	0	0
gen_host_fifo[1].idInRange	396906024	331733	0	0
maxM	900	900	0	0
rspIdInRange	396906024	4614334	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	246572	0	0
T1	30773	73	0	0
T2	253077	4	0	0
T3	170782	3	0	0
T7	595894	930	0	0
T8	447015	4	0	0
T9	9335	46	0	0
T10	797180	47	0	0
T11	7686	49	0	0
T12	9549	63	0	0
T13	915814	625	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	331733	0	0
T1	30773	62	0	0
T2	253077	4	0	0
T3	170782	735	0	0
T7	595894	1684	0	0
T8	447015	9	0	0
T9	9335	45	0	0
T10	797180	57	0	0
T11	7686	41	0	0
T12	9549	61	0	0
T13	915814	938	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4614334	0	0
T1	30773	476	0	0
T2	253077	1363	0	0
T3	170782	9	0	0
T7	595894	5561	0	0
T8	447015	2580	0	0
T9	9335	84	0	0
T10	797180	5589	0	0
T11	7686	84	0	0
T12	9549	121	0	0
T13	915814	3046	0	0

Line Coverage for Instance : tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	2	2
105	2	2
108	2	2
163	2	2
166	1	1
212	1	1
213	1	1
231	1	1
236	2	2
238	2	2
242	2	2

---

Cond Coverage for Instance : tb.dut.u_sm1_56

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	297987	0	0
gen_host_fifo[1].idInRange	396906024	384984	0	0
maxM	900	900	0	0
rspIdInRange	396906024	3661462	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	297987	0	0
T1	30773	62	0	0
T2	253077	6	0	0
T3	170782	8	0	0
T7	595894	925	0	0
T8	447015	12	0	0
T9	9335	64	0	0
T10	797180	49	0	0
T11	7686	42	0	0
T12	9549	87	0	0
T13	915814	317	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	384984	0	0
T1	30773	40	0	0
T2	253077	2	0	0
T3	170782	8	0	0
T7	595894	1656	0	0
T8	447015	10	0	0
T9	9335	50	0	0
T10	797180	70	0	0
T11	7686	38	0	0
T12	9549	84	0	0
T13	915814	161	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3661462	0	0
T1	30773	524	0	0
T2	253077	3129	0	0
T3	170782	1388	0	0
T7	595894	5367	0	0
T8	447015	6003	0	0
T9	9335	104	0	0
T10	797180	5819	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	1891	0	0

Line Coverage for Instance : tb.dut.u_sm1_30

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	3	3
105	3	3
108	3	3
163	3	3
166	1	1
212	1	1
213	1	1
231	1	1
236	3	3
238	3	3
242	3	3

---

Cond Coverage for Instance : tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T10
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	396906024	9030241	0	0
gen_host_fifo[1].idInRange	396906024	1678444	0	0
gen_host_fifo[2].idInRange	396906024	1785332	0	0
maxM	900	900	0	0
rspIdInRange	396906024	19951835	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	9030241	0	0
T1	30773	1994	0	0
T2	253077	90	0	0
T3	170782	12305	0	0
T7	595894	33033	0	0
T8	447015	105	0	0
T9	9335	248	0	0
T10	797180	1273	0	0
T11	7686	507	0	0
T12	9549	390	0	0
T13	915814	59078	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1678444	0	0
T1	30773	439	0	0
T2	253077	18	0	0
T3	170782	2386	0	0
T7	595894	6685	0	0
T8	447015	31	0	0
T9	9335	42	0	0
T10	797180	222	0	0
T11	7686	36	0	0
T12	9549	80	0	0
T13	915814	4443	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1785332	0	0
T1	30773	350	0	0
T2	253077	41	0	0
T3	170782	1691	0	0
T7	595894	7068	0	0
T8	447015	22	0	0
T9	9335	39	0	0
T10	797180	181	0	0
T11	7686	31	0	0
T12	9549	74	0	0
T13	915814	9168	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	19951835	0	0
T1	30773	2165	0	0
T2	253077	7380	0	0
T3	170782	6793	0	0
T7	595894	44068	0	0
T8	447015	11192	0	0
T9	9335	326	0	0
T10	797180	7294	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	57415	0	0