Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7679503	0	0
GntImpliesValid_A	2147483647	7679503	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7679503	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	426104400	0	0
ReadyAndValidImplyGrant_A	2147483647	7679503	0	0
ReqAndReadyImplyGrant_A	2147483647	7679503	0	0
ReqImpliesValid_A	2147483647	32345508	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	47010	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7679503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	738552	738072	0	0
T2	6073848	6072840	0	0
T3	4098768	4097712	0	0
T7	14301456	14300904	0	0
T8	10728360	10727208	0	0
T9	224040	222432	0	0
T10	19132320	19132056	0	0
T11	184464	176784	0	0
T12	229176	228168	0	0
T13	21979536	21977664	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679503	0	0
T1	738552	2940	0	0
T2	6073848	364	0	0
T3	4098768	518	0	0
T7	14301456	54545	0	0
T8	10728360	441	0	0
T9	224040	3285	0	0
T10	19132320	3536	0	0
T11	184464	5334	0	0
T12	229176	5131	0	0
T13	21979536	1865	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679503	0	0
T1	738552	2940	0	0
T2	6073848	364	0	0
T3	4098768	518	0	0
T7	14301456	54545	0	0
T8	10728360	441	0	0
T9	224040	3285	0	0
T10	19132320	3536	0	0
T11	184464	5334	0	0
T12	229176	5131	0	0
T13	21979536	1865	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	738552	738072	0	0
T2	6073848	6072840	0	0
T3	4098768	4097712	0	0
T7	14301456	14300904	0	0
T8	10728360	10727208	0	0
T9	224040	222432	0	0
T10	19132320	19132056	0	0
T11	184464	176784	0	0
T12	229176	228168	0	0
T13	21979536	21977664	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	738552	738072	0	0
T2	6073848	6072840	0	0
T3	4098768	4097712	0	0
T7	14301456	14300904	0	0
T8	10728360	10727208	0	0
T9	224040	222432	0	0
T10	19132320	19132056	0	0
T11	184464	176784	0	0
T12	229176	228168	0	0
T13	21979536	21977664	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679503	0	0
T1	738552	2940	0	0
T2	6073848	364	0	0
T3	4098768	518	0	0
T7	14301456	54545	0	0
T8	10728360	441	0	0
T9	224040	3285	0	0
T10	19132320	3536	0	0
T11	184464	5334	0	0
T12	229176	5131	0	0
T13	21979536	1865	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	426104400	0	0
T1	738552	46025	0	0
T2	6073848	212203	0	0
T3	4098768	295507	0	0
T7	14301456	772088	0	0
T8	10728360	375555	0	0
T9	224040	5441	0	0
T10	19132320	676545	0	0
T11	184464	4073	0	0
T12	229176	6997	0	0
T13	21979536	1460748	0	0
T14	0	155340	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679503	0	0
T1	738552	2940	0	0
T2	6073848	364	0	0
T3	4098768	518	0	0
T7	14301456	54545	0	0
T8	10728360	441	0	0
T9	224040	3285	0	0
T10	19132320	3536	0	0
T11	184464	5334	0	0
T12	229176	5131	0	0
T13	21979536	1865	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679503	0	0
T1	738552	2940	0	0
T2	6073848	364	0	0
T3	4098768	518	0	0
T7	14301456	54545	0	0
T8	10728360	441	0	0
T9	224040	3285	0	0
T10	19132320	3536	0	0
T11	184464	5334	0	0
T12	229176	5131	0	0
T13	21979536	1865	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32345508	0	0
T1	738552	6951	0	0
T2	6073848	582	0	0
T3	4098768	29093	0	0
T7	14301456	183368	0	0
T8	10728360	793	0	0
T9	224040	3843	0	0
T10	19132320	5552	0	0
T11	184464	6479	0	0
T12	229176	6189	0	0
T13	21979536	120001	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47010	0	21600
T7	1191788	102	0	2
T8	894030	0	0	2
T9	18670	11	0	2
T10	1594360	0	0	2
T11	15372	12	0	2
T12	19098	16	0	2
T13	1831628	0	0	2
T14	369124	7	0	2
T15	392024	1	0	2
T16	0	25	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	13	0	0
T20	0	2	0	0
T21	0	10	0	0
T22	0	3	0	0
T23	0	4	0	0
T24	0	12	0	0
T25	16566	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	738552	738072	0	0
T2	6073848	6072840	0	0
T3	4098768	4097712	0	0
T7	14301456	14300904	0	0
T8	10728360	10727208	0	0
T9	224040	222432	0	0
T10	19132320	19132056	0	0
T11	184464	176784	0	0
T12	229176	228168	0	0
T13	21979536	21977664	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679503	0	0
T1	738552	2940	0	0
T2	6073848	364	0	0
T3	4098768	518	0	0
T7	14301456	54545	0	0
T8	10728360	441	0	0
T9	224040	3285	0	0
T10	19132320	3536	0	0
T11	184464	5334	0	0
T12	229176	5131	0	0
T13	21979536	1865	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	853004	0	0
GntImpliesValid_A	396906024	853004	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	853004	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	10782737	0	0
ReadyAndValidImplyGrant_A	396906024	853004	0	0
ReqAndReadyImplyGrant_A	396906024	853004	0	0
ReqImpliesValid_A	396906024	2383333	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	853004	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853004	0	0
T1	30773	290	0	0
T2	253077	36	0	0
T3	170782	52	0	0
T7	595894	6509	0	0
T8	447015	35	0	0
T9	9335	354	0	0
T10	797180	404	0	0
T11	7686	550	0	0
T12	9549	603	0	0
T13	915814	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853004	0	0
T1	30773	290	0	0
T2	253077	36	0	0
T3	170782	52	0	0
T7	595894	6509	0	0
T8	447015	35	0	0
T9	9335	354	0	0
T10	797180	404	0	0
T11	7686	550	0	0
T12	9549	603	0	0
T13	915814	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853004	0	0
T1	30773	290	0	0
T2	253077	36	0	0
T3	170782	52	0	0
T7	595894	6509	0	0
T8	447015	35	0	0
T9	9335	354	0	0
T10	797180	404	0	0
T11	7686	550	0	0
T12	9549	603	0	0
T13	915814	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	10782737	0	0
T1	30773	2055	0	0
T2	253077	159	0	0
T3	170782	17509	0	0
T7	595894	38050	0	0
T8	447015	141	0	0
T9	9335	296	0	0
T10	797180	1749	0	0
T11	7686	450	0	0
T12	9549	430	0	0
T13	915814	68126	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853004	0	0
T1	30773	290	0	0
T2	253077	36	0	0
T3	170782	52	0	0
T7	595894	6509	0	0
T8	447015	35	0	0
T9	9335	354	0	0
T10	797180	404	0	0
T11	7686	550	0	0
T12	9549	603	0	0
T13	915814	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853004	0	0
T1	30773	290	0	0
T2	253077	36	0	0
T3	170782	52	0	0
T7	595894	6509	0	0
T8	447015	35	0	0
T9	9335	354	0	0
T10	797180	404	0	0
T11	7686	550	0	0
T12	9549	603	0	0
T13	915814	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2383333	0	0
T1	30773	627	0	0
T2	253077	43	0	0
T3	170782	2094	0	0
T7	595894	14405	0	0
T8	447015	52	0	0
T9	9335	413	0	0
T10	797180	573	0	0
T11	7686	660	0	0
T12	9549	777	0	0
T13	915814	6862	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853004	0	0
T1	30773	290	0	0
T2	253077	36	0	0
T3	170782	52	0	0
T7	595894	6509	0	0
T8	447015	35	0	0
T9	9335	354	0	0
T10	797180	404	0	0
T11	7686	550	0	0
T12	9549	603	0	0
T13	915814	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	850404	0	0
GntImpliesValid_A	396906024	850404	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	850404	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	10753615	0	0
ReadyAndValidImplyGrant_A	396906024	850404	0	0
ReqAndReadyImplyGrant_A	396906024	850404	0	0
ReqImpliesValid_A	396906024	2322127	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	850404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	850404	0	0
T1	30773	306	0	0
T2	253077	44	0	0
T3	170782	55	0	0
T7	595894	6214	0	0
T8	447015	50	0	0
T9	9335	337	0	0
T10	797180	346	0	0
T11	7686	581	0	0
T12	9549	522	0	0
T13	915814	223	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	850404	0	0
T1	30773	306	0	0
T2	253077	44	0	0
T3	170782	55	0	0
T7	595894	6214	0	0
T8	447015	50	0	0
T9	9335	337	0	0
T10	797180	346	0	0
T11	7686	581	0	0
T12	9549	522	0	0
T13	915814	223	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	850404	0	0
T1	30773	306	0	0
T2	253077	44	0	0
T3	170782	55	0	0
T7	595894	6214	0	0
T8	447015	50	0	0
T9	9335	337	0	0
T10	797180	346	0	0
T11	7686	581	0	0
T12	9549	522	0	0
T13	915814	223	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	10753615	0	0
T1	30773	2151	0	0
T2	253077	193	0	0
T3	170782	17999	0	0
T7	595894	37250	0	0
T8	447015	228	0	0
T9	9335	292	0	0
T10	797180	1446	0	0
T11	7686	470	0	0
T12	9549	401	0	0
T13	915814	71989	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	850404	0	0
T1	30773	306	0	0
T2	253077	44	0	0
T3	170782	55	0	0
T7	595894	6214	0	0
T8	447015	50	0	0
T9	9335	337	0	0
T10	797180	346	0	0
T11	7686	581	0	0
T12	9549	522	0	0
T13	915814	223	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	850404	0	0
T1	30773	306	0	0
T2	253077	44	0	0
T3	170782	55	0	0
T7	595894	6214	0	0
T8	447015	50	0	0
T9	9335	337	0	0
T10	797180	346	0	0
T11	7686	581	0	0
T12	9549	522	0	0
T13	915814	223	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2322127	0	0
T1	30773	544	0	0
T2	253077	56	0	0
T3	170782	2830	0	0
T7	595894	22330	0	0
T8	447015	88	0	0
T9	9335	383	0	0
T10	797180	444	0	0
T11	7686	702	0	0
T12	9549	644	0	0
T13	915814	6204	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	850404	0	0
T1	30773	306	0	0
T2	253077	44	0	0
T3	170782	55	0	0
T7	595894	6214	0	0
T8	447015	50	0	0
T9	9335	337	0	0
T10	797180	346	0	0
T11	7686	581	0	0
T12	9549	522	0	0
T13	915814	223	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	215789	0	0
GntImpliesValid_A	396906024	215789	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	215789	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2600967	0	0
ReadyAndValidImplyGrant_A	396906024	215789	0	0
ReqAndReadyImplyGrant_A	396906024	215789	0	0
ReqImpliesValid_A	396906024	568525	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	215789	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215789	0	0
T1	30773	97	0	0
T2	253077	9	0	0
T3	170782	18	0	0
T7	595894	1282	0	0
T8	447015	14	0	0
T9	9335	112	0	0
T10	797180	107	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215789	0	0
T1	30773	97	0	0
T2	253077	9	0	0
T3	170782	18	0	0
T7	595894	1282	0	0
T8	447015	14	0	0
T9	9335	112	0	0
T10	797180	107	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215789	0	0
T1	30773	97	0	0
T2	253077	9	0	0
T3	170782	18	0	0
T7	595894	1282	0	0
T8	447015	14	0	0
T9	9335	112	0	0
T10	797180	107	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2600967	0	0
T1	30773	659	0	0
T2	253077	42	0	0
T3	170782	5710	0	0
T7	595894	7778	0	0
T8	447015	73	0	0
T9	9335	105	0	0
T10	797180	495	0	0
T11	7686	142	0	0
T12	9549	134	0	0
T13	915814	14988	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215789	0	0
T1	30773	97	0	0
T2	253077	9	0	0
T3	170782	18	0	0
T7	595894	1282	0	0
T8	447015	14	0	0
T9	9335	112	0	0
T10	797180	107	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215789	0	0
T1	30773	97	0	0
T2	253077	9	0	0
T3	170782	18	0	0
T7	595894	1282	0	0
T8	447015	14	0	0
T9	9335	112	0	0
T10	797180	107	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	568525	0	0
T1	30773	125	0	0
T2	253077	15	0	0
T3	170782	973	0	0
T7	595894	3955	0	0
T8	447015	14	0	0
T9	9335	120	0	0
T10	797180	131	0	0
T11	7686	970	0	0
T12	9549	147	0	0
T13	915814	667	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215789	0	0
T1	30773	97	0	0
T2	253077	9	0	0
T3	170782	18	0	0
T7	595894	1282	0	0
T8	447015	14	0	0
T9	9335	112	0	0
T10	797180	107	0	0
T11	7686	551	0	0
T12	9549	140	0	0
T13	915814	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	222161	0	0
GntImpliesValid_A	396906024	222161	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	222161	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2636964	0	0
ReadyAndValidImplyGrant_A	396906024	222161	0	0
ReqAndReadyImplyGrant_A	396906024	222161	0	0
ReqImpliesValid_A	396906024	571461	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	222161	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	222161	0	0
T1	30773	92	0	0
T2	253077	18	0	0
T3	170782	24	0	0
T7	595894	1339	0	0
T8	447015	17	0	0
T9	9335	80	0	0
T10	797180	101	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	222161	0	0
T1	30773	92	0	0
T2	253077	18	0	0
T3	170782	24	0	0
T7	595894	1339	0	0
T8	447015	17	0	0
T9	9335	80	0	0
T10	797180	101	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	222161	0	0
T1	30773	92	0	0
T2	253077	18	0	0
T3	170782	24	0	0
T7	595894	1339	0	0
T8	447015	17	0	0
T9	9335	80	0	0
T10	797180	101	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2636964	0	0
T1	30773	719	0	0
T2	253077	87	0	0
T3	170782	7865	0	0
T7	595894	7875	0	0
T8	447015	63	0	0
T9	9335	79	0	0
T10	797180	399	0	0
T11	7686	364	0	0
T12	9549	146	0	0
T13	915814	19025	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	222161	0	0
T1	30773	92	0	0
T2	253077	18	0	0
T3	170782	24	0	0
T7	595894	1339	0	0
T8	447015	17	0	0
T9	9335	80	0	0
T10	797180	101	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	222161	0	0
T1	30773	92	0	0
T2	253077	18	0	0
T3	170782	24	0	0
T7	595894	1339	0	0
T8	447015	17	0	0
T9	9335	80	0	0
T10	797180	101	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	571461	0	0
T1	30773	147	0	0
T2	253077	18	0	0
T3	170782	1097	0	0
T7	595894	4649	0	0
T8	447015	23	0	0
T9	9335	82	0	0
T10	797180	116	0	0
T11	7686	820	0	0
T12	9549	159	0	0
T13	915814	1678	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	222161	0	0
T1	30773	92	0	0
T2	253077	18	0	0
T3	170782	24	0	0
T7	595894	1339	0	0
T8	447015	17	0	0
T9	9335	80	0	0
T10	797180	101	0	0
T11	7686	587	0	0
T12	9549	152	0	0
T13	915814	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	208920	0	0
GntImpliesValid_A	396906024	208920	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	208920	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	5190570	0	0
ReadyAndValidImplyGrant_A	396906024	208920	0	0
ReqAndReadyImplyGrant_A	396906024	208920	0	0
ReqImpliesValid_A	396906024	1214392	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	208920	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	208920	0	0
T1	30773	78	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	811	0	0
T8	447015	17	0	0
T9	9335	86	0	0
T10	797180	77	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	208920	0	0
T1	30773	78	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	811	0	0
T8	447015	17	0	0
T9	9335	86	0	0
T10	797180	77	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	208920	0	0
T1	30773	78	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	811	0	0
T8	447015	17	0	0
T9	9335	86	0	0
T10	797180	77	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	5190570	0	0
T1	30773	1499	0	0
T2	253077	155	0	0
T3	170782	4235	0	0
T7	595894	3520	0	0
T8	447015	704	0	0
T9	9335	542	0	0
T10	797180	1103	0	0
T11	7686	248	0	0
T12	9549	686	0	0
T13	915814	50024	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	208920	0	0
T1	30773	78	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	811	0	0
T8	447015	17	0	0
T9	9335	86	0	0
T10	797180	77	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	208920	0	0
T1	30773	78	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	811	0	0
T8	447015	17	0	0
T9	9335	86	0	0
T10	797180	77	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1214392	0	0
T1	30773	236	0	0
T2	253077	59	0	0
T3	170782	74	0	0
T7	595894	858	0	0
T8	447015	152	0	0
T9	9335	140	0	0
T10	797180	103	0	0
T11	7686	154	0	0
T12	9549	245	0	0
T13	915814	3558	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	208920	0	0
T1	30773	78	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	811	0	0
T8	447015	17	0	0
T9	9335	86	0	0
T10	797180	77	0	0
T11	7686	88	0	0
T12	9549	154	0	0
T13	915814	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	209676	0	0
GntImpliesValid_A	396906024	209676	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	209676	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	5147803	0	0
ReadyAndValidImplyGrant_A	396906024	209676	0	0
ReqAndReadyImplyGrant_A	396906024	209676	0	0
ReqImpliesValid_A	396906024	1225502	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	209676	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	209676	0	0
T1	30773	78	0	0
T2	253077	4	0	0
T3	170782	6	0	0
T7	595894	840	0	0
T8	447015	9	0	0
T9	9335	96	0	0
T10	797180	117	0	0
T11	7686	74	0	0
T12	9549	149	0	0
T13	915814	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	209676	0	0
T1	30773	78	0	0
T2	253077	4	0	0
T3	170782	6	0	0
T7	595894	840	0	0
T8	447015	9	0	0
T9	9335	96	0	0
T10	797180	117	0	0
T11	7686	74	0	0
T12	9549	149	0	0
T13	915814	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	209676	0	0
T1	30773	78	0	0
T2	253077	4	0	0
T3	170782	6	0	0
T7	595894	840	0	0
T8	447015	9	0	0
T9	9335	96	0	0
T10	797180	117	0	0
T11	7686	74	0	0
T12	9549	149	0	0
T13	915814	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	5147803	0	0
T1	30773	449	0	0
T2	253077	48	0	0
T3	170782	4034	0	0
T7	595894	3727	0	0
T8	447015	61	0	0
T9	9335	493	0	0
T10	797180	753	0	0
T11	7686	253	0	0
T12	9549	1138	0	0
T13	915814	39059	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	209676	0	0
T1	30773	78	0	0
T2	253077	4	0	0
T3	170782	6	0	0
T7	595894	840	0	0
T8	447015	9	0	0
T9	9335	96	0	0
T10	797180	117	0	0
T11	7686	74	0	0
T12	9549	149	0	0
T13	915814	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	209676	0	0
T1	30773	78	0	0
T2	253077	4	0	0
T3	170782	6	0	0
T7	595894	840	0	0
T8	447015	9	0	0
T9	9335	96	0	0
T10	797180	117	0	0
T11	7686	74	0	0
T12	9549	149	0	0
T13	915814	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1225502	0	0
T1	30773	94	0	0
T2	253077	6	0	0
T3	170782	6	0	0
T7	595894	902	0	0
T8	447015	12	0	0
T9	9335	185	0	0
T10	797180	152	0	0
T11	7686	83	0	0
T12	9549	345	0	0
T13	915814	2292	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	209676	0	0
T1	30773	78	0	0
T2	253077	4	0	0
T3	170782	6	0	0
T7	595894	840	0	0
T8	447015	9	0	0
T9	9335	96	0	0
T10	797180	117	0	0
T11	7686	74	0	0
T12	9549	149	0	0
T13	915814	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	211180	0	0
GntImpliesValid_A	396906024	211180	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	211180	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	4667719	0	0
ReadyAndValidImplyGrant_A	396906024	211180	0	0
ReqAndReadyImplyGrant_A	396906024	211180	0	0
ReqImpliesValid_A	396906024	1174792	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	211180	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211180	0	0
T1	30773	84	0	0
T2	253077	4	0	0
T3	170782	9	0	0
T7	595894	2261	0	0
T8	447015	14	0	0
T9	9335	106	0	0
T10	797180	105	0	0
T11	7686	64	0	0
T12	9549	132	0	0
T13	915814	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211180	0	0
T1	30773	84	0	0
T2	253077	4	0	0
T3	170782	9	0	0
T7	595894	2261	0	0
T8	447015	14	0	0
T9	9335	106	0	0
T10	797180	105	0	0
T11	7686	64	0	0
T12	9549	132	0	0
T13	915814	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211180	0	0
T1	30773	84	0	0
T2	253077	4	0	0
T3	170782	9	0	0
T7	595894	2261	0	0
T8	447015	14	0	0
T9	9335	106	0	0
T10	797180	105	0	0
T11	7686	64	0	0
T12	9549	132	0	0
T13	915814	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4667719	0	0
T1	30773	767	0	0
T2	253077	36	0	0
T3	170782	1478	0	0
T7	595894	8304	0	0
T8	447015	567	0	0
T9	9335	1557	0	0
T10	797180	499	0	0
T11	7686	223	0	0
T12	9549	834	0	0
T13	915814	35137	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211180	0	0
T1	30773	84	0	0
T2	253077	4	0	0
T3	170782	9	0	0
T7	595894	2261	0	0
T8	447015	14	0	0
T9	9335	106	0	0
T10	797180	105	0	0
T11	7686	64	0	0
T12	9549	132	0	0
T13	915814	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211180	0	0
T1	30773	84	0	0
T2	253077	4	0	0
T3	170782	9	0	0
T7	595894	2261	0	0
T8	447015	14	0	0
T9	9335	106	0	0
T10	797180	105	0	0
T11	7686	64	0	0
T12	9549	132	0	0
T13	915814	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1174792	0	0
T1	30773	108	0	0
T2	253077	4	0	0
T3	170782	461	0	0
T7	595894	3260	0	0
T8	447015	14	0	0
T9	9335	295	0	0
T10	797180	133	0	0
T11	7686	64	0	0
T12	9549	257	0	0
T13	915814	2576	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211180	0	0
T1	30773	84	0	0
T2	253077	4	0	0
T3	170782	9	0	0
T7	595894	2261	0	0
T8	447015	14	0	0
T9	9335	106	0	0
T10	797180	105	0	0
T11	7686	64	0	0
T12	9549	132	0	0
T13	915814	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	210358	0	0
GntImpliesValid_A	396906024	210358	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	210358	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	4326088	0	0
ReadyAndValidImplyGrant_A	396906024	210358	0	0
ReqAndReadyImplyGrant_A	396906024	210358	0	0
ReqImpliesValid_A	396906024	1090802	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	210358	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210358	0	0
T1	30773	89	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	1433	0	0
T8	447015	9	0	0
T9	9335	86	0	0
T10	797180	106	0	0
T11	7686	65	0	0
T12	9549	179	0	0
T13	915814	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210358	0	0
T1	30773	89	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	1433	0	0
T8	447015	9	0	0
T9	9335	86	0	0
T10	797180	106	0	0
T11	7686	65	0	0
T12	9549	179	0	0
T13	915814	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210358	0	0
T1	30773	89	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	1433	0	0
T8	447015	9	0	0
T9	9335	86	0	0
T10	797180	106	0	0
T11	7686	65	0	0
T12	9549	179	0	0
T13	915814	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4326088	0	0
T1	30773	1237	0	0
T2	253077	62	0	0
T3	170782	3758	0	0
T7	595894	10264	0	0
T8	447015	502	0	0
T9	9335	776	0	0
T10	797180	522	0	0
T11	7686	322	0	0
T12	9549	1316	0	0
T13	915814	25676	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210358	0	0
T1	30773	89	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	1433	0	0
T8	447015	9	0	0
T9	9335	86	0	0
T10	797180	106	0	0
T11	7686	65	0	0
T12	9549	179	0	0
T13	915814	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210358	0	0
T1	30773	89	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	1433	0	0
T8	447015	9	0	0
T9	9335	86	0	0
T10	797180	106	0	0
T11	7686	65	0	0
T12	9549	179	0	0
T13	915814	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1090802	0	0
T1	30773	168	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	7405	0	0
T8	447015	9	0	0
T9	9335	144	0	0
T10	797180	127	0	0
T11	7686	72	0	0
T12	9549	400	0	0
T13	915814	5210	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210358	0	0
T1	30773	89	0	0
T2	253077	8	0	0
T3	170782	11	0	0
T7	595894	1433	0	0
T8	447015	9	0	0
T9	9335	86	0	0
T10	797180	106	0	0
T11	7686	65	0	0
T12	9549	179	0	0
T13	915814	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	218753	0	0
GntImpliesValid_A	396906024	218753	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	218753	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2631486	0	0
ReadyAndValidImplyGrant_A	396906024	218753	0	0
ReqAndReadyImplyGrant_A	396906024	218753	0	0
ReqImpliesValid_A	396906024	580144	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	218753	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	218753	0	0
T1	30773	93	0	0
T2	253077	9	0	0
T3	170782	14	0	0
T7	595894	1944	0	0
T8	447015	16	0	0
T9	9335	99	0	0
T10	797180	131	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	218753	0	0
T1	30773	93	0	0
T2	253077	9	0	0
T3	170782	14	0	0
T7	595894	1944	0	0
T8	447015	16	0	0
T9	9335	99	0	0
T10	797180	131	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	218753	0	0
T1	30773	93	0	0
T2	253077	9	0	0
T3	170782	14	0	0
T7	595894	1944	0	0
T8	447015	16	0	0
T9	9335	99	0	0
T10	797180	131	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2631486	0	0
T1	30773	687	0	0
T2	253077	41	0	0
T3	170782	4013	0	0
T7	595894	10870	0	0
T8	447015	55	0	0
T9	9335	96	0	0
T10	797180	555	0	0
T11	7686	60	0	0
T12	9549	141	0	0
T13	915814	13092	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	218753	0	0
T1	30773	93	0	0
T2	253077	9	0	0
T3	170782	14	0	0
T7	595894	1944	0	0
T8	447015	16	0	0
T9	9335	99	0	0
T10	797180	131	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	218753	0	0
T1	30773	93	0	0
T2	253077	9	0	0
T3	170782	14	0	0
T7	595894	1944	0	0
T8	447015	16	0	0
T9	9335	99	0	0
T10	797180	131	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	580144	0	0
T1	30773	146	0	0
T2	253077	9	0	0
T3	170782	666	0	0
T7	595894	8682	0	0
T8	447015	20	0	0
T9	9335	103	0	0
T10	797180	154	0	0
T11	7686	56	0	0
T12	9549	164	0	0
T13	915814	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	218753	0	0
T1	30773	93	0	0
T2	253077	9	0	0
T3	170782	14	0	0
T7	595894	1944	0	0
T8	447015	16	0	0
T9	9335	99	0	0
T10	797180	131	0	0
T11	7686	53	0	0
T12	9549	152	0	0
T13	915814	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	214753	0	0
GntImpliesValid_A	396906024	214753	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	214753	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2667420	0	0
ReadyAndValidImplyGrant_A	396906024	214753	0	0
ReqAndReadyImplyGrant_A	396906024	214753	0	0
ReqImpliesValid_A	396906024	621893	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	214753	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214753	0	0
T1	30773	90	0	0
T2	253077	12	0	0
T3	170782	18	0	0
T7	595894	1893	0	0
T8	447015	21	0	0
T9	9335	105	0	0
T10	797180	96	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214753	0	0
T1	30773	90	0	0
T2	253077	12	0	0
T3	170782	18	0	0
T7	595894	1893	0	0
T8	447015	21	0	0
T9	9335	105	0	0
T10	797180	96	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214753	0	0
T1	30773	90	0	0
T2	253077	12	0	0
T3	170782	18	0	0
T7	595894	1893	0	0
T8	447015	21	0	0
T9	9335	105	0	0
T10	797180	96	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2667420	0	0
T1	30773	691	0	0
T2	253077	39	0	0
T3	170782	6048	0	0
T7	595894	12561	0	0
T8	447015	73	0	0
T9	9335	103	0	0
T10	797180	424	0	0
T11	7686	91	0	0
T12	9549	133	0	0
T13	915814	12546	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214753	0	0
T1	30773	90	0	0
T2	253077	12	0	0
T3	170782	18	0	0
T7	595894	1893	0	0
T8	447015	21	0	0
T9	9335	105	0	0
T10	797180	96	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214753	0	0
T1	30773	90	0	0
T2	253077	12	0	0
T3	170782	18	0	0
T7	595894	1893	0	0
T8	447015	21	0	0
T9	9335	105	0	0
T10	797180	96	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	621893	0	0
T1	30773	117	0	0
T2	253077	21	0	0
T3	170782	276	0	0
T7	595894	5589	0	0
T8	447015	33	0	0
T9	9335	108	0	0
T10	797180	98	0	0
T11	7686	93	0	0
T12	9549	144	0	0
T13	915814	1089	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214753	0	0
T1	30773	90	0	0
T2	253077	12	0	0
T3	170782	18	0	0
T7	595894	1893	0	0
T8	447015	21	0	0
T9	9335	105	0	0
T10	797180	96	0	0
T11	7686	87	0	0
T12	9549	138	0	0
T13	915814	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	211898	0	0
GntImpliesValid_A	396906024	211898	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	211898	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2604096	0	0
ReadyAndValidImplyGrant_A	396906024	211898	0	0
ReqAndReadyImplyGrant_A	396906024	211898	0	0
ReqImpliesValid_A	396906024	529097	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	211898	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211898	0	0
T1	30773	95	0	0
T2	253077	10	0	0
T3	170782	14	0	0
T7	595894	838	0	0
T8	447015	8	0	0
T9	9335	90	0	0
T10	797180	90	0	0
T11	7686	73	0	0
T12	9549	134	0	0
T13	915814	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211898	0	0
T1	30773	95	0	0
T2	253077	10	0	0
T3	170782	14	0	0
T7	595894	838	0	0
T8	447015	8	0	0
T9	9335	90	0	0
T10	797180	90	0	0
T11	7686	73	0	0
T12	9549	134	0	0
T13	915814	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211898	0	0
T1	30773	95	0	0
T2	253077	10	0	0
T3	170782	14	0	0
T7	595894	838	0	0
T8	447015	8	0	0
T9	9335	90	0	0
T10	797180	90	0	0
T11	7686	73	0	0
T12	9549	134	0	0
T13	915814	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2604096	0	0
T1	30773	745	0	0
T2	253077	41	0	0
T3	170782	4838	0	0
T7	595894	6476	0	0
T8	447015	30	0	0
T9	9335	88	0	0
T10	797180	342	0	0
T11	7686	82	0	0
T12	9549	130	0	0
T13	915814	21531	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211898	0	0
T1	30773	95	0	0
T2	253077	10	0	0
T3	170782	14	0	0
T7	595894	838	0	0
T8	447015	8	0	0
T9	9335	90	0	0
T10	797180	90	0	0
T11	7686	73	0	0
T12	9549	134	0	0
T13	915814	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211898	0	0
T1	30773	95	0	0
T2	253077	10	0	0
T3	170782	14	0	0
T7	595894	838	0	0
T8	447015	8	0	0
T9	9335	90	0	0
T10	797180	90	0	0
T11	7686	73	0	0
T12	9549	134	0	0
T13	915814	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	529097	0	0
T1	30773	155	0	0
T2	253077	10	0	0
T3	170782	172	0	0
T7	595894	954	0	0
T8	447015	8	0	0
T9	9335	93	0	0
T10	797180	101	0	0
T11	7686	73	0	0
T12	9549	139	0	0
T13	915814	570	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	211898	0	0
T1	30773	95	0	0
T2	253077	10	0	0
T3	170782	14	0	0
T7	595894	838	0	0
T8	447015	8	0	0
T9	9335	90	0	0
T10	797180	90	0	0
T11	7686	73	0	0
T12	9549	134	0	0
T13	915814	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	217087	0	0
GntImpliesValid_A	396906024	217087	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	217087	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2646619	0	0
ReadyAndValidImplyGrant_A	396906024	217087	0	0
ReqAndReadyImplyGrant_A	396906024	217087	0	0
ReqImpliesValid_A	396906024	598335	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	217087	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	217087	0	0
T1	30773	60	0	0
T2	253077	16	0	0
T3	170782	16	0	0
T7	595894	2126	0	0
T8	447015	9	0	0
T9	9335	85	0	0
T10	797180	91	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	217087	0	0
T1	30773	60	0	0
T2	253077	16	0	0
T3	170782	16	0	0
T7	595894	2126	0	0
T8	447015	9	0	0
T9	9335	85	0	0
T10	797180	91	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	217087	0	0
T1	30773	60	0	0
T2	253077	16	0	0
T3	170782	16	0	0
T7	595894	2126	0	0
T8	447015	9	0	0
T9	9335	85	0	0
T10	797180	91	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2646619	0	0
T1	30773	493	0	0
T2	253077	95	0	0
T3	170782	7330	0	0
T7	595894	11986	0	0
T8	447015	46	0	0
T9	9335	83	0	0
T10	797180	413	0	0
T11	7686	74	0	0
T12	9549	117	0	0
T13	915814	13523	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	217087	0	0
T1	30773	60	0	0
T2	253077	16	0	0
T3	170782	16	0	0
T7	595894	2126	0	0
T8	447015	9	0	0
T9	9335	85	0	0
T10	797180	91	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	217087	0	0
T1	30773	60	0	0
T2	253077	16	0	0
T3	170782	16	0	0
T7	595894	2126	0	0
T8	447015	9	0	0
T9	9335	85	0	0
T10	797180	91	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	598335	0	0
T1	30773	61	0	0
T2	253077	19	0	0
T3	170782	16	0	0
T7	595894	8678	0	0
T8	447015	9	0	0
T9	9335	88	0	0
T10	797180	101	0	0
T11	7686	64	0	0
T12	9549	134	0	0
T13	915814	1196	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	217087	0	0
T1	30773	60	0	0
T2	253077	16	0	0
T3	170782	16	0	0
T7	595894	2126	0	0
T8	447015	9	0	0
T9	9335	85	0	0
T10	797180	91	0	0
T11	7686	64	0	0
T12	9549	125	0	0
T13	915814	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	201845	0	0
GntImpliesValid_A	396906024	201845	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	201845	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2602927	0	0
ReadyAndValidImplyGrant_A	396906024	201845	0	0
ReqAndReadyImplyGrant_A	396906024	201845	0	0
ReqImpliesValid_A	396906024	520415	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	201845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	201845	0	0
T1	30773	78	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	1421	0	0
T8	447015	9	0	0
T9	9335	81	0	0
T10	797180	87	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	201845	0	0
T1	30773	78	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	1421	0	0
T8	447015	9	0	0
T9	9335	81	0	0
T10	797180	87	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	201845	0	0
T1	30773	78	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	1421	0	0
T8	447015	9	0	0
T9	9335	81	0	0
T10	797180	87	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	66	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2602927	0	0
T1	30773	543	0	0
T2	253077	29	0	0
T3	170782	4186	0	0
T7	595894	6986	0	0
T8	447015	48	0	0
T9	9335	80	0	0
T10	797180	356	0	0
T11	7686	426	0	0
T12	9549	128	0	0
T13	915814	22404	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	201845	0	0
T1	30773	78	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	1421	0	0
T8	447015	9	0	0
T9	9335	81	0	0
T10	797180	87	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	201845	0	0
T1	30773	78	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	1421	0	0
T8	447015	9	0	0
T9	9335	81	0	0
T10	797180	87	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	520415	0	0
T1	30773	106	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	6895	0	0
T8	447015	9	0	0
T9	9335	83	0	0
T10	797180	96	0	0
T11	7686	606	0	0
T12	9549	153	0	0
T13	915814	1364	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	201845	0	0
T1	30773	78	0	0
T2	253077	8	0	0
T3	170782	14	0	0
T7	595894	1421	0	0
T8	447015	9	0	0
T9	9335	81	0	0
T10	797180	87	0	0
T11	7686	511	0	0
T12	9549	140	0	0
T13	915814	66	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	212993	0	0
GntImpliesValid_A	396906024	212993	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	212993	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2631547	0	0
ReadyAndValidImplyGrant_A	396906024	212993	0	0
ReqAndReadyImplyGrant_A	396906024	212993	0	0
ReqImpliesValid_A	396906024	564224	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	212993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212993	0	0
T1	30773	84	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	1278	0	0
T8	447015	20	0	0
T9	9335	88	0	0
T10	797180	103	0	0
T11	7686	90	0	0
T12	9549	144	0	0
T13	915814	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212993	0	0
T1	30773	84	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	1278	0	0
T8	447015	20	0	0
T9	9335	88	0	0
T10	797180	103	0	0
T11	7686	90	0	0
T12	9549	144	0	0
T13	915814	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212993	0	0
T1	30773	84	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	1278	0	0
T8	447015	20	0	0
T9	9335	88	0	0
T10	797180	103	0	0
T11	7686	90	0	0
T12	9549	144	0	0
T13	915814	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2631547	0	0
T1	30773	662	0	0
T2	253077	40	0	0
T3	170782	8716	0	0
T7	595894	9340	0	0
T8	447015	76	0	0
T9	9335	86	0	0
T10	797180	426	0	0
T11	7686	98	0	0
T12	9549	135	0	0
T13	915814	15666	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212993	0	0
T1	30773	84	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	1278	0	0
T8	447015	20	0	0
T9	9335	88	0	0
T10	797180	103	0	0
T11	7686	90	0	0
T12	9549	144	0	0
T13	915814	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212993	0	0
T1	30773	84	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	1278	0	0
T8	447015	20	0	0
T9	9335	88	0	0
T10	797180	103	0	0
T11	7686	90	0	0
T12	9549	144	0	0
T13	915814	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	564224	0	0
T1	30773	123	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	2171	0	0
T8	447015	23	0	0
T9	9335	91	0	0
T10	797180	135	0	0
T11	7686	92	0	0
T12	9549	154	0	0
T13	915814	229	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212993	0	0
T1	30773	84	0	0
T2	253077	9	0	0
T3	170782	21	0	0
T7	595894	1278	0	0
T8	447015	20	0	0
T9	9335	88	0	0
T10	797180	103	0	0
T11	7686	90	0	0
T12	9549	144	0	0
T13	915814	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	215790	0	0
GntImpliesValid_A	396906024	215790	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	215790	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2707733	0	0
ReadyAndValidImplyGrant_A	396906024	215790	0	0
ReqAndReadyImplyGrant_A	396906024	215790	0	0
ReqImpliesValid_A	396906024	556571	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	215790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215790	0	0
T1	30773	93	0	0
T2	253077	10	0	0
T3	170782	16	0	0
T7	595894	2302	0	0
T8	447015	12	0	0
T9	9335	90	0	0
T10	797180	94	0	0
T11	7686	77	0	0
T12	9549	178	0	0
T13	915814	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215790	0	0
T1	30773	93	0	0
T2	253077	10	0	0
T3	170782	16	0	0
T7	595894	2302	0	0
T8	447015	12	0	0
T9	9335	90	0	0
T10	797180	94	0	0
T11	7686	77	0	0
T12	9549	178	0	0
T13	915814	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215790	0	0
T1	30773	93	0	0
T2	253077	10	0	0
T3	170782	16	0	0
T7	595894	2302	0	0
T8	447015	12	0	0
T9	9335	90	0	0
T10	797180	94	0	0
T11	7686	77	0	0
T12	9549	178	0	0
T13	915814	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2707733	0	0
T1	30773	681	0	0
T2	253077	47	0	0
T3	170782	4871	0	0
T7	595894	14715	0	0
T8	447015	57	0	0
T9	9335	90	0	0
T10	797180	422	0	0
T11	7686	85	0	0
T12	9549	167	0	0
T13	915814	14564	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215790	0	0
T1	30773	93	0	0
T2	253077	10	0	0
T3	170782	16	0	0
T7	595894	2302	0	0
T8	447015	12	0	0
T9	9335	90	0	0
T10	797180	94	0	0
T11	7686	77	0	0
T12	9549	178	0	0
T13	915814	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215790	0	0
T1	30773	93	0	0
T2	253077	10	0	0
T3	170782	16	0	0
T7	595894	2302	0	0
T8	447015	12	0	0
T9	9335	90	0	0
T10	797180	94	0	0
T11	7686	77	0	0
T12	9549	178	0	0
T13	915814	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	556571	0	0
T1	30773	135	0	0
T2	253077	13	0	0
T3	170782	61	0	0
T7	595894	7484	0	0
T8	447015	12	0	0
T9	9335	91	0	0
T10	797180	94	0	0
T11	7686	78	0	0
T12	9549	190	0	0
T13	915814	471	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	215790	0	0
T1	30773	93	0	0
T2	253077	10	0	0
T3	170782	16	0	0
T7	595894	2302	0	0
T8	447015	12	0	0
T9	9335	90	0	0
T10	797180	94	0	0
T11	7686	77	0	0
T12	9549	178	0	0
T13	915814	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	214005	0	0
GntImpliesValid_A	396906024	214005	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	214005	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2636357	0	0
ReadyAndValidImplyGrant_A	396906024	214005	0	0
ReqAndReadyImplyGrant_A	396906024	214005	0	0
ReqImpliesValid_A	396906024	596912	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	214005	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214005	0	0
T1	30773	86	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	798	0	0
T8	447015	14	0	0
T9	9335	89	0	0
T10	797180	109	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214005	0	0
T1	30773	86	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	798	0	0
T8	447015	14	0	0
T9	9335	89	0	0
T10	797180	109	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214005	0	0
T1	30773	86	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	798	0	0
T8	447015	14	0	0
T9	9335	89	0	0
T10	797180	109	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2636357	0	0
T1	30773	596	0	0
T2	253077	32	0	0
T3	170782	2314	0	0
T7	595894	5959	0	0
T8	447015	69	0	0
T9	9335	88	0	0
T10	797180	381	0	0
T11	7686	86	0	0
T12	9549	125	0	0
T13	915814	16306	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214005	0	0
T1	30773	86	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	798	0	0
T8	447015	14	0	0
T9	9335	89	0	0
T10	797180	109	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214005	0	0
T1	30773	86	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	798	0	0
T8	447015	14	0	0
T9	9335	89	0	0
T10	797180	109	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	596912	0	0
T1	30773	122	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	936	0	0
T8	447015	14	0	0
T9	9335	91	0	0
T10	797180	130	0	0
T11	7686	80	0	0
T12	9549	128	0	0
T13	915814	1280	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	214005	0	0
T1	30773	86	0	0
T2	253077	9	0	0
T3	170782	9	0	0
T7	595894	798	0	0
T8	447015	14	0	0
T9	9335	89	0	0
T10	797180	109	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	228375	0	0
GntImpliesValid_A	396906024	228375	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	228375	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2661611	0	0
ReadyAndValidImplyGrant_A	396906024	228375	0	0
ReqAndReadyImplyGrant_A	396906024	228375	0	0
ReqImpliesValid_A	396906024	570326	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	228375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	228375	0	0
T1	30773	92	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	1936	0	0
T8	447015	8	0	0
T9	9335	157	0	0
T10	797180	107	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	228375	0	0
T1	30773	92	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	1936	0	0
T8	447015	8	0	0
T9	9335	157	0	0
T10	797180	107	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	228375	0	0
T1	30773	92	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	1936	0	0
T8	447015	8	0	0
T9	9335	157	0	0
T10	797180	107	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2661611	0	0
T1	30773	776	0	0
T2	253077	42	0	0
T3	170782	3197	0	0
T7	595894	12146	0	0
T8	447015	33	0	0
T9	9335	151	0	0
T10	797180	474	0	0
T11	7686	109	0	0
T12	9549	149	0	0
T13	915814	17069	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	228375	0	0
T1	30773	92	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	1936	0	0
T8	447015	8	0	0
T9	9335	157	0	0
T10	797180	107	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	228375	0	0
T1	30773	92	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	1936	0	0
T8	447015	8	0	0
T9	9335	157	0	0
T10	797180	107	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	570326	0	0
T1	30773	121	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	3482	0	0
T8	447015	11	0	0
T9	9335	164	0	0
T10	797180	118	0	0
T11	7686	109	0	0
T12	9549	164	0	0
T13	915814	997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	228375	0	0
T1	30773	92	0	0
T2	253077	9	0	0
T3	170782	16	0	0
T7	595894	1936	0	0
T8	447015	8	0	0
T9	9335	157	0	0
T10	797180	107	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	212274	0	0
GntImpliesValid_A	396906024	212274	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	212274	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2627506	0	0
ReadyAndValidImplyGrant_A	396906024	212274	0	0
ReqAndReadyImplyGrant_A	396906024	212274	0	0
ReqImpliesValid_A	396906024	558095	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	212274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212274	0	0
T1	30773	63	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	1445	0	0
T8	447015	20	0	0
T9	9335	92	0	0
T10	797180	91	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212274	0	0
T1	30773	63	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	1445	0	0
T8	447015	20	0	0
T9	9335	92	0	0
T10	797180	91	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212274	0	0
T1	30773	63	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	1445	0	0
T8	447015	20	0	0
T9	9335	92	0	0
T10	797180	91	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2627506	0	0
T1	30773	495	0	0
T2	253077	65	0	0
T3	170782	5106	0	0
T7	595894	9484	0	0
T8	447015	80	0	0
T9	9335	87	0	0
T10	797180	371	0	0
T11	7686	73	0	0
T12	9549	138	0	0
T13	915814	17973	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212274	0	0
T1	30773	63	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	1445	0	0
T8	447015	20	0	0
T9	9335	92	0	0
T10	797180	91	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212274	0	0
T1	30773	63	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	1445	0	0
T8	447015	20	0	0
T9	9335	92	0	0
T10	797180	91	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	558095	0	0
T1	30773	101	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	3838	0	0
T8	447015	22	0	0
T9	9335	98	0	0
T10	797180	95	0	0
T11	7686	73	0	0
T12	9549	155	0	0
T13	915814	2074	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	212274	0	0
T1	30773	63	0	0
T2	253077	13	0	0
T3	170782	16	0	0
T7	595894	1445	0	0
T8	447015	20	0	0
T9	9335	92	0	0
T10	797180	91	0	0
T11	7686	68	0	0
T12	9549	146	0	0
T13	915814	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	204695	0	0
GntImpliesValid_A	396906024	204695	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	204695	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2646044	0	0
ReadyAndValidImplyGrant_A	396906024	204695	0	0
ReqAndReadyImplyGrant_A	396906024	204695	0	0
ReqImpliesValid_A	396906024	493156	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	204695	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	204695	0	0
T1	30773	99	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	1343	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	87	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	204695	0	0
T1	30773	99	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	1343	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	87	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	204695	0	0
T1	30773	99	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	1343	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	87	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2646044	0	0
T1	30773	713	0	0
T2	253077	60	0	0
T3	170782	3527	0	0
T7	595894	7127	0	0
T8	447015	50	0	0
T9	9335	81	0	0
T10	797180	395	0	0
T11	7686	86	0	0
T12	9549	141	0	0
T13	915814	20269	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	204695	0	0
T1	30773	99	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	1343	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	87	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	204695	0	0
T1	30773	99	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	1343	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	87	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	493156	0	0
T1	30773	133	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	6022	0	0
T8	447015	13	0	0
T9	9335	88	0	0
T10	797180	97	0	0
T11	7686	80	0	0
T12	9549	154	0	0
T13	915814	1831	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	204695	0	0
T1	30773	99	0	0
T2	253077	15	0	0
T3	170782	14	0	0
T7	595894	1343	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	87	0	0
T11	7686	78	0	0
T12	9549	147	0	0
T13	915814	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	210569	0	0
GntImpliesValid_A	396906024	210569	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	210569	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2669834	0	0
ReadyAndValidImplyGrant_A	396906024	210569	0	0
ReqAndReadyImplyGrant_A	396906024	210569	0	0
ReqImpliesValid_A	396906024	493002	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	210569	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210569	0	0
T1	30773	94	0	0
T2	253077	8	0	0
T3	170782	15	0	0
T7	595894	1242	0	0
T8	447015	16	0	0
T9	9335	90	0	0
T10	797180	109	0	0
T11	7686	187	0	0
T12	9549	142	0	0
T13	915814	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210569	0	0
T1	30773	94	0	0
T2	253077	8	0	0
T3	170782	15	0	0
T7	595894	1242	0	0
T8	447015	16	0	0
T9	9335	90	0	0
T10	797180	109	0	0
T11	7686	187	0	0
T12	9549	142	0	0
T13	915814	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210569	0	0
T1	30773	94	0	0
T2	253077	8	0	0
T3	170782	15	0	0
T7	595894	1242	0	0
T8	447015	16	0	0
T9	9335	90	0	0
T10	797180	109	0	0
T11	7686	187	0	0
T12	9549	142	0	0
T13	915814	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2669834	0	0
T1	30773	656	0	0
T2	253077	34	0	0
T3	170782	3610	0	0
T7	595894	7054	0	0
T8	447015	65	0	0
T9	9335	89	0	0
T10	797180	483	0	0
T11	7686	144	0	0
T12	9549	133	0	0
T13	915814	11668	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210569	0	0
T1	30773	94	0	0
T2	253077	8	0	0
T3	170782	15	0	0
T7	595894	1242	0	0
T8	447015	16	0	0
T9	9335	90	0	0
T10	797180	109	0	0
T11	7686	187	0	0
T12	9549	142	0	0
T13	915814	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210569	0	0
T1	30773	94	0	0
T2	253077	8	0	0
T3	170782	15	0	0
T7	595894	1242	0	0
T8	447015	16	0	0
T9	9335	90	0	0
T10	797180	109	0	0
T11	7686	187	0	0
T12	9549	142	0	0
T13	915814	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	493002	0	0
T1	30773	153	0	0
T2	253077	8	0	0
T3	170782	815	0	0
T7	595894	5001	0	0
T8	447015	16	0	0
T9	9335	92	0	0
T10	797180	122	0	0
T11	7686	240	0	0
T12	9549	152	0	0
T13	915814	260	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	210569	0	0
T1	30773	94	0	0
T2	253077	8	0	0
T3	170782	15	0	0
T7	595894	1242	0	0
T8	447015	16	0	0
T9	9335	90	0	0
T10	797180	109	0	0
T11	7686	187	0	0
T12	9549	142	0	0
T13	915814	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	202036	0	0
GntImpliesValid_A	396906024	202036	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	202036	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2679883	0	0
ReadyAndValidImplyGrant_A	396906024	202036	0	0
ReqAndReadyImplyGrant_A	396906024	202036	0	0
ReqImpliesValid_A	396906024	490506	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	202036	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	202036	0	0
T1	30773	86	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	1281	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	96	0	0
T11	7686	85	0	0
T12	9549	121	0	0
T13	915814	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	202036	0	0
T1	30773	86	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	1281	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	96	0	0
T11	7686	85	0	0
T12	9549	121	0	0
T13	915814	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	202036	0	0
T1	30773	86	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	1281	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	96	0	0
T11	7686	85	0	0
T12	9549	121	0	0
T13	915814	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2679883	0	0
T1	30773	652	0	0
T2	253077	31	0	0
T3	170782	4019	0	0
T7	595894	9400	0	0
T8	447015	52	0	0
T9	9335	81	0	0
T10	797180	393	0	0
T11	7686	91	0	0
T12	9549	119	0	0
T13	915814	16933	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	202036	0	0
T1	30773	86	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	1281	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	96	0	0
T11	7686	85	0	0
T12	9549	121	0	0
T13	915814	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	202036	0	0
T1	30773	86	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	1281	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	96	0	0
T11	7686	85	0	0
T12	9549	121	0	0
T13	915814	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	490506	0	0
T1	30773	135	0	0
T2	253077	8	0	0
T3	170782	738	0	0
T7	595894	2500	0	0
T8	447015	13	0	0
T9	9335	88	0	0
T10	797180	104	0	0
T11	7686	89	0	0
T12	9549	124	0	0
T13	915814	1563	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	202036	0	0
T1	30773	86	0	0
T2	253077	8	0	0
T3	170782	9	0	0
T7	595894	1281	0	0
T8	447015	13	0	0
T9	9335	84	0	0
T10	797180	96	0	0
T11	7686	85	0	0
T12	9549	121	0	0
T13	915814	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	213977	0	0
GntImpliesValid_A	396906024	213977	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	213977	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	2643377	0	0
ReadyAndValidImplyGrant_A	396906024	213977	0	0
ReqAndReadyImplyGrant_A	396906024	213977	0	0
ReqImpliesValid_A	396906024	562789	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	0	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	213977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	213977	0	0
T1	30773	87	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	1308	0	0
T8	447015	20	0	0
T9	9335	104	0	0
T10	797180	97	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	213977	0	0
T1	30773	87	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	1308	0	0
T8	447015	20	0	0
T9	9335	104	0	0
T10	797180	97	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	213977	0	0
T1	30773	87	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	1308	0	0
T8	447015	20	0	0
T9	9335	104	0	0
T10	797180	97	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2643377	0	0
T1	30773	617	0	0
T2	253077	41	0	0
T3	170782	5234	0	0
T7	595894	9343	0	0
T8	447015	79	0	0
T9	9335	96	0	0
T10	797180	372	0	0
T11	7686	86	0	0
T12	9549	154	0	0
T13	915814	13923	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	213977	0	0
T1	30773	87	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	1308	0	0
T8	447015	20	0	0
T9	9335	104	0	0
T10	797180	97	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	213977	0	0
T1	30773	87	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	1308	0	0
T8	447015	20	0	0
T9	9335	104	0	0
T10	797180	97	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	562789	0	0
T1	30773	102	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	2447	0	0
T8	447015	22	0	0
T9	9335	113	0	0
T10	797180	119	0	0
T11	7686	80	0	0
T12	9549	171	0	0
T13	915814	478	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	213977	0	0
T1	30773	87	0	0
T2	253077	8	0	0
T3	170782	16	0	0
T7	595894	1308	0	0
T8	447015	20	0	0
T9	9335	104	0	0
T10	797180	97	0	0
T11	7686	78	0	0
T12	9549	162	0	0
T13	915814	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	859186	0	0
GntImpliesValid_A	396906024	859186	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	859186	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	10197050	0	0
ReadyAndValidImplyGrant_A	396906024	859186	0	0
ReqAndReadyImplyGrant_A	396906024	859186	0	0
ReqImpliesValid_A	396906024	2219849	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	16865	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	859186	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859186	0	0
T1	30773	305	0	0
T2	253077	48	0	0
T3	170782	63	0	0
T7	595894	6425	0	0
T8	447015	41	0	0
T9	9335	364	0	0
T10	797180	403	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859186	0	0
T1	30773	305	0	0
T2	253077	48	0	0
T3	170782	63	0	0
T7	595894	6425	0	0
T8	447015	41	0	0
T9	9335	364	0	0
T10	797180	403	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859186	0	0
T1	30773	305	0	0
T2	253077	48	0	0
T3	170782	63	0	0
T7	595894	6425	0	0
T8	447015	41	0	0
T9	9335	364	0	0
T10	797180	403	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	10197050	0	0
T1	30773	1967	0	0
T2	253077	138	0	0
T3	170782	16797	0	0
T7	595894	38007	0	0
T8	447015	124	0	0
T9	9335	1	0	0
T10	797180	1261	0	0
T11	7686	10	0	0
T12	9549	1	0	0
T13	915814	66762	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859186	0	0
T1	30773	305	0	0
T2	253077	48	0	0
T3	170782	63	0	0
T7	595894	6425	0	0
T8	447015	41	0	0
T9	9335	364	0	0
T10	797180	403	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859186	0	0
T1	30773	305	0	0
T2	253077	48	0	0
T3	170782	63	0	0
T7	595894	6425	0	0
T8	447015	41	0	0
T9	9335	364	0	0
T10	797180	403	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2219849	0	0
T1	30773	488	0	0
T2	253077	65	0	0
T3	170782	2542	0	0
T7	595894	16799	0	0
T8	447015	46	0	0
T9	9335	364	0	0
T10	797180	533	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	5844	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	16865	0	900
T7	595894	12	0	1
T8	447015	0	0	1
T9	9335	8	0	1
T10	797180	0	0	1
T11	7686	7	0	1
T12	9549	8	0	1
T13	915814	0	0	1
T14	184562	4	0	1
T15	196012	0	0	1
T17	0	1	0	0
T19	0	13	0	0
T22	0	3	0	0
T23	0	4	0	0
T24	0	12	0	0
T25	8283	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859186	0	0
T1	30773	305	0	0
T2	253077	48	0	0
T3	170782	63	0	0
T7	595894	6425	0	0
T8	447015	41	0	0
T9	9335	364	0	0
T10	797180	403	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	207	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396906024	396790949	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	396906024	859775	0	0
GntImpliesValid_A	396906024	859775	0	0
GrantKnown_A	396906024	396790949	0	0
IdxKnown_A	396906024	396790949	0	0
IndexIsCorrect_A	396906024	859775	0	0
LockArbDecision_A	396906024	0	0	0
NoReadyValidNoGrant_A	396906024	332744447	0	0
ReadyAndValidImplyGrant_A	396906024	859775	0	0
ReqAndReadyImplyGrant_A	396906024	859775	0	0
ReqImpliesValid_A	396906024	11839260	0	0
ReqStaysHighUntilGranted0_M	396906024	0	0	0
RoundRobin_A	396906024	30145	0	900
ValidKnown_A	396906024	396790949	0	0
gen_data_port_assertion.DataFlow_A	396906024	859775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859775	0	0
T1	30773	321	0	0
T2	253077	30	0	0
T3	170782	56	0	0
T7	595894	6276	0	0
T8	447015	36	0	0
T9	9335	326	0	0
T10	797180	382	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859775	0	0
T1	30773	321	0	0
T2	253077	30	0	0
T3	170782	56	0	0
T7	595894	6276	0	0
T8	447015	36	0	0
T9	9335	326	0	0
T10	797180	382	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859775	0	0
T1	30773	321	0	0
T2	253077	30	0	0
T3	170782	56	0	0
T7	595894	6276	0	0
T8	447015	36	0	0
T9	9335	326	0	0
T10	797180	382	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	198	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	332744447	0	0
T1	30773	25515	0	0
T2	253077	210646	0	0
T3	170782	149113	0	0
T7	595894	483866	0	0
T8	447015	372279	0	0
T9	9335	1	0	0
T10	797180	662511	0	0
T11	7686	0	0	0
T12	9549	1	0	0
T13	915814	842495	0	0
T14	0	155340	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859775	0	0
T1	30773	321	0	0
T2	253077	30	0	0
T3	170782	56	0	0
T7	595894	6276	0	0
T8	447015	36	0	0
T9	9335	326	0	0
T10	797180	382	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859775	0	0
T1	30773	321	0	0
T2	253077	30	0	0
T3	170782	56	0	0
T7	595894	6276	0	0
T8	447015	36	0	0
T9	9335	326	0	0
T10	797180	382	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	11839260	0	0
T1	30773	2704	0	0
T2	253077	149	0	0
T3	170782	16155	0	0
T7	595894	44126	0	0
T8	447015	158	0	0
T9	9335	326	0	0
T10	797180	1676	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	71596	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	30145	0	900
T7	595894	90	0	1
T8	447015	0	0	1
T9	9335	3	0	1
T10	797180	0	0	1
T11	7686	5	0	1
T12	9549	8	0	1
T13	915814	0	0	1
T14	184562	3	0	1
T15	196012	1	0	1
T16	0	25	0	0
T18	0	1	0	0
T20	0	2	0	0
T21	0	10	0	0
T25	8283	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	859775	0	0
T1	30773	321	0	0
T2	253077	30	0	0
T3	170782	56	0	0
T7	595894	6276	0	0
T8	447015	36	0	0
T9	9335	326	0	0
T10	797180	382	0	0
T11	7686	571	0	0
T12	9549	532	0	0
T13	915814	198	0	0