Unified Coverage Report :: Module :: tlul_socket_m1

Module : tlul_socket_m1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28	95.96	100.00	87.88				100.00
tb.dut.u_sm1_29	95.96	100.00	87.88				100.00
tb.dut.u_sm1_31	95.96	100.00	87.88				100.00
tb.dut.u_sm1_33	96.97	100.00	90.91				100.00
tb.dut.u_sm1_34	96.97	100.00	90.91				100.00
tb.dut.u_sm1_36	96.97	100.00	90.91				100.00
tb.dut.u_sm1_38	96.97	100.00	90.91				100.00
tb.dut.u_sm1_40	96.97	100.00	90.91				100.00
tb.dut.u_sm1_42	96.97	100.00	90.91				100.00
tb.dut.u_sm1_43	96.97	100.00	90.91				100.00
tb.dut.u_sm1_44	96.97	100.00	90.91				100.00
tb.dut.u_sm1_45	96.97	100.00	90.91				100.00
tb.dut.u_sm1_46	96.97	100.00	90.91				100.00
tb.dut.u_sm1_47	96.97	100.00	90.91				100.00
tb.dut.u_sm1_48	96.97	100.00	90.91				100.00
tb.dut.u_sm1_49	96.97	100.00	90.91				100.00
tb.dut.u_sm1_50	96.97	100.00	90.91				100.00
tb.dut.u_sm1_51	96.97	100.00	90.91				100.00
tb.dut.u_sm1_52	96.97	100.00	90.91				100.00
tb.dut.u_sm1_53	96.97	100.00	90.91				100.00
tb.dut.u_sm1_54	96.97	100.00	90.91				100.00
tb.dut.u_sm1_55	96.97	100.00	90.91				100.00
tb.dut.u_sm1_56	96.97	100.00	90.91				100.00
tb.dut.u_sm1_30	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sm1_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.51	98.68	85.92			92.73	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	92.21	97.50	82.14			89.19	100.00

---

Module Instance : tb.dut.u_sm1_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78	100.00	98.39			100.00	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_28

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_29

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_33

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_34

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_36

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_38

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_40

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_42

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_43

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_44

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_45

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_46

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_47

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_48

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_49

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_50

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_51

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_52

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_53

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_54

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_55

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
95.96	87.88

tb.dut.u_sm1_28

SCORE	COND
95.96	87.88

tb.dut.u_sm1_29

SCORE	COND
95.96	87.88

tb.dut.u_sm1_31

SCORE	COND
100.00	100.00

tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.97	90.91

tb.dut.u_sm1_33

SCORE	COND
96.97	90.91

tb.dut.u_sm1_34

SCORE	COND
96.97	90.91

tb.dut.u_sm1_43

SCORE	COND
96.97	90.91

tb.dut.u_sm1_44

SCORE	COND
96.97	90.91

tb.dut.u_sm1_45

SCORE	COND
96.97	90.91

tb.dut.u_sm1_46

SCORE	COND
96.97	90.91

tb.dut.u_sm1_47

SCORE	COND
96.97	90.91

tb.dut.u_sm1_48

SCORE	COND
96.97	90.91

tb.dut.u_sm1_49

SCORE	COND
96.97	90.91

tb.dut.u_sm1_50

SCORE	COND
96.97	90.91

tb.dut.u_sm1_51

SCORE	COND
96.97	90.91

tb.dut.u_sm1_52

SCORE	COND
96.97	90.91

tb.dut.u_sm1_53

SCORE	COND
96.97	90.91

tb.dut.u_sm1_54

SCORE	COND
96.97	90.91

tb.dut.u_sm1_55

SCORE	COND
96.97	90.91

tb.dut.u_sm1_56

SCORE	COND
96.97	90.91

tb.dut.u_sm1_36

SCORE	COND
96.97	90.91

tb.dut.u_sm1_38

SCORE	COND
96.97	90.91

tb.dut.u_sm1_40

SCORE	COND
96.97	90.91

tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_m1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	2147483647	23788169	0	0
gen_host_fifo[1].idInRange	2147483647	13202983	0	0
gen_host_fifo[2].idInRange	1620837348	3768182	0	0
maxM	21600	21600	0	0
rspIdInRange	2147483647	157691664	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23788169	0	0
T1	175214	584	0	0
T2	40608	361	0	0
T3	183696	3879	0	0
T7	9683568	15139	0	0
T8	2123544	11655	0	0
T9	7735224	462	0	0
T10	94800	468	0	0
T11	253176	1690	0	0
T12	1177872	3420	0	0
T13	673224	30966	0	0
T14	39063	611	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13202983	0	0
T1	182832	181	0	0
T2	40608	133	0	0
T3	183696	1821	0	0
T7	9683568	8681	0	0
T8	2123544	5518	0	0
T9	7735224	177	0	0
T10	94800	141	0	0
T11	253176	629	0	0
T12	1177872	1236	0	0
T13	673224	22278	0	0
T14	0	841	0	0
T26	0	15	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620837348	3768182	0	0
T1	30472	57	0	0
T2	6768	19	0	0
T3	30616	290	0	0
T7	1613928	166	0	0
T8	353924	1544	0	0
T9	1289204	44	0	0
T10	15800	20	0	0
T11	42196	273	0	0
T12	196312	438	0	0
T13	112204	2645	0	0
T14	0	483	0	0
T26	0	1008	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	157691664	0	0
T1	182832	898	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	48155	0	0
T8	2123544	44276	0	0
T9	7735224	100778	0	0
T10	94800	1383	0	0
T11	253176	4036	0	0
T12	1177872	15479	0	0
T13	673224	12875	0	0
T14	0	1379	0	0

Line Coverage for Instance : tb.dut.u_sm1_28

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T18,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	1724046	0	0
gen_host_fifo[1].idInRange	405209337	428664	0	0
gen_host_fifo[2].idInRange	405209337	555592	0	0
maxM	900	900	0	0
rspIdInRange	405209337	18431418	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1724046	0	0
T1	7618	63	0	0
T2	1692	30	0	0
T3	7654	409	0	0
T7	403482	2500	0	0
T8	88481	1144	0	0
T9	322301	44	0	0
T10	3950	14	0	0
T11	10549	165	0	0
T12	49078	246	0	0
T13	28051	948	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	428664	0	0
T1	7618	4	0	0
T2	1692	2	0	0
T3	7654	67	0	0
T7	403482	3	0	0
T8	88481	195	0	0
T9	322301	7	0	0
T10	3950	4	0	0
T11	10549	26	0	0
T12	49078	33	0	0
T13	28051	0	0	0
T14	0	70	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	555592	0	0
T1	7618	4	0	0
T2	1692	4	0	0
T3	7654	65	0	0
T7	403482	0	0	0
T8	88481	145	0	0
T9	322301	5	0	0
T10	3950	7	0	0
T11	10549	36	0	0
T12	49078	41	0	0
T13	28051	0	0	0
T14	0	74	0	0
T26	0	1008	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	18431418	0	0
T1	7618	135	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	3955	0	0
T8	88481	6254	0	0
T9	322301	11094	0	0
T10	3950	152	0	0
T11	10549	369	0	0
T12	49078	2044	0	0
T13	28051	948	0	0

Line Coverage for Instance : tb.dut.u_sm1_29

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_29

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T11,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	1878092	0	0
gen_host_fifo[1].idInRange	405209337	476099	0	0
gen_host_fifo[2].idInRange	405209337	583511	0	0
maxM	900	900	0	0
rspIdInRange	405209337	19259226	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1878092	0	0
T1	7618	35	0	0
T2	1692	64	0	0
T3	7654	655	0	0
T7	403482	405	0	0
T8	88481	1177	0	0
T9	322301	24	0	0
T10	3950	23	0	0
T11	10549	161	0	0
T12	49078	276	0	0
T13	28051	2815	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	476099	0	0
T1	7618	4	0	0
T2	1692	4	0	0
T3	7654	96	0	0
T7	403482	9	0	0
T8	88481	204	0	0
T9	322301	5	0	0
T10	3950	1	0	0
T11	10549	10	0	0
T12	49078	69	0	0
T13	28051	1645	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	583511	0	0
T1	7618	1	0	0
T2	1692	4	0	0
T3	7654	84	0	0
T7	403482	3	0	0
T8	88481	180	0	0
T9	322301	15	0	0
T10	3950	1	0	0
T11	10549	66	0	0
T12	49078	47	0	0
T13	28051	1400	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	19259226	0	0
T1	7618	78	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	7575	0	0
T8	88481	6110	0	0
T9	322301	4569	0	0
T10	3950	183	0	0
T11	10549	381	0	0
T12	49078	2339	0	0
T13	28051	1746	0	0

Line Coverage for Instance : tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_31

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T11,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	1845297	0	0
gen_host_fifo[1].idInRange	405209337	456291	0	0
gen_host_fifo[2].idInRange	405209337	587196	0	0
maxM	900	900	0	0
rspIdInRange	405209337	20212680	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1845297	0	0
T1	7618	42	0	0
T2	1692	65	0	0
T3	7654	576	0	0
T7	403482	1643	0	0
T8	88481	1374	0	0
T9	322301	73	0	0
T10	3950	24	0	0
T11	10549	170	0	0
T12	49078	248	0	0
T13	28051	2657	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	456291	0	0
T1	7618	3	0	0
T2	1692	4	0	0
T3	7654	97	0	0
T7	403482	6	0	0
T8	88481	198	0	0
T9	322301	12	0	0
T10	3950	3	0	0
T11	10549	13	0	0
T12	49078	62	0	0
T13	28051	1351	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	587196	0	0
T1	7618	5	0	0
T2	1692	7	0	0
T3	7654	73	0	0
T7	403482	2	0	0
T8	88481	239	0	0
T9	322301	6	0	0
T10	3950	5	0	0
T11	10549	54	0	0
T12	49078	41	0	0
T13	28051	1245	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	20212680	0	0
T1	7618	102	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	6924	0	0
T8	88481	6384	0	0
T9	322301	16712	0	0
T10	3950	174	0	0
T11	10549	394	0	0
T12	49078	2124	0	0
T13	28051	1680	0	0

Line Coverage for Instance : tb.dut.u_sm1_33

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_33

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	346654	0	0
gen_host_fifo[1].idInRange	405209337	461660	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4132465	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	346654	0	0
T1	7618	5	0	0
T2	1692	4	0	0
T3	7654	67	0	0
T7	403482	7	0	0
T8	88481	99	0	0
T9	322301	9	0	0
T10	3950	11	0	0
T11	10549	16	0	0
T12	49078	42	0	0
T13	28051	0	0	0
T14	0	40	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	461660	0	0
T1	7618	7	0	0
T2	1692	3	0	0
T3	7654	85	0	0
T7	403482	1023	0	0
T8	88481	157	0	0
T9	322301	9	0	0
T10	3950	7	0	0
T11	10549	19	0	0
T12	49078	43	0	0
T13	28051	0	0	0
T14	0	55	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4132465	0	0
T1	7618	23	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	1850	0	0
T8	88481	1018	0	0
T9	322301	1744	0	0
T10	3950	26	0	0
T11	10549	96	0	0
T12	49078	310	0	0
T13	28051	0	0	0
T14	0	134	0	0

Line Coverage for Instance : tb.dut.u_sm1_34

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_34

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T11
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	322836	0	0
gen_host_fifo[1].idInRange	405209337	428536	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3903384	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	322836	0	0
T1	7618	4	0	0
T2	1692	4	0	0
T3	7654	77	0	0
T7	403482	494	0	0
T8	88481	129	0	0
T9	322301	11	0	0
T10	3950	3	0	0
T11	10549	24	0	0
T12	49078	37	0	0
T13	28051	0	0	0
T14	0	77	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	428536	0	0
T1	7618	10	0	0
T2	1692	5	0	0
T3	7654	81	0	0
T7	403482	307	0	0
T8	88481	188	0	0
T9	322301	5	0	0
T10	3950	1	0	0
T11	10549	16	0	0
T12	49078	40	0	0
T13	28051	0	0	0
T14	0	42	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3903384	0	0
T1	7618	20	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	1411	0	0
T8	88481	1012	0	0
T9	322301	3871	0	0
T10	3950	15	0	0
T11	10549	117	0	0
T12	49078	326	0	0
T13	28051	0	0	0
T14	0	167	0	0

Line Coverage for Instance : tb.dut.u_sm1_36

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_36

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T11,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	716385	0	0
gen_host_fifo[1].idInRange	405209337	794036	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3486711	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	716385	0	0
T1	7618	6	0	0
T2	1692	7	0	0
T3	7654	136	0	0
T7	403482	2	0	0
T8	88481	118	0	0
T9	322301	4	0	0
T10	3950	3	0	0
T11	10549	18	0	0
T12	49078	48	0	0
T13	28051	7707	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	794036	0	0
T1	7618	21	0	0
T2	1692	13	0	0
T3	7654	73	0	0
T7	403482	3	0	0
T8	88481	241	0	0
T9	322301	10	0	0
T10	3950	4	0	0
T11	10549	27	0	0
T12	49078	29	0	0
T13	28051	7057	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3486711	0	0
T1	7618	19	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	572	0	0
T8	88481	988	0	0
T9	322301	1317	0	0
T10	3950	32	0	0
T11	10549	114	0	0
T12	49078	345	0	0
T13	28051	997	0	0

Line Coverage for Instance : tb.dut.u_sm1_38

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_38

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T26
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	544712	0	0
gen_host_fifo[1].idInRange	405209337	713104	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4559771	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	544712	0	0
T1	7618	21	0	0
T2	1692	16	0	0
T3	7654	89	0	0
T7	403482	4	0	0
T8	88481	191	0	0
T9	322301	23	0	0
T10	3950	1	0	0
T11	10549	18	0	0
T12	49078	36	0	0
T13	28051	0	0	0
T14	0	58	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	713104	0	0
T1	7618	26	0	0
T2	1692	3	0	0
T3	7654	83	0	0
T7	403482	2759	0	0
T8	88481	319	0	0
T9	322301	7	0	0
T10	3950	3	0	0
T11	10549	51	0	0
T12	49078	42	0	0
T13	28051	0	0	0
T14	0	40	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4559771	0	0
T1	7618	43	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	1249	0	0
T8	88481	951	0	0
T9	322301	2580	0	0
T10	3950	6	0	0
T11	10549	89	0	0
T12	49078	344	0	0
T13	28051	0	0	0
T14	0	196	0	0

Line Coverage for Instance : tb.dut.u_sm1_40

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_40

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	816296	0	0
gen_host_fifo[1].idInRange	405209337	991760	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3978322	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	816296	0	0
T1	7618	3	0	0
T2	1692	27	0	0
T3	7654	98	0	0
T7	403482	32	0	0
T8	88481	304	0	0
T9	322301	7	0	0
T10	3950	2	0	0
T11	10549	31	0	0
T12	49078	29	0	0
T13	28051	0	0	0
T14	0	47	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	991760	0	0
T1	7618	7	0	0
T2	1692	10	0	0
T3	7654	112	0	0
T7	403482	204	0	0
T8	88481	209	0	0
T9	322301	0	0	0
T10	3950	18	0	0
T11	10549	15	0	0
T12	49078	44	0	0
T13	28051	0	0	0
T14	0	48	0	0
T26	0	15	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3978322	0	0
T1	7618	62	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	1816	0	0
T8	88481	1020	0	0
T9	322301	2919	0	0
T10	3950	13	0	0
T11	10549	197	0	0
T12	49078	299	0	0
T13	28051	0	0	0
T14	0	205	0	0

Line Coverage for Instance : tb.dut.u_sm1_42

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	682408	0	0
gen_host_fifo[1].idInRange	405209337	832771	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4874950	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	682408	0	0
T1	7618	14	0	0
T2	1692	5	0	0
T3	7654	97	0	0
T7	403482	6	0	0
T8	88481	313	0	0
T9	322301	15	0	0
T10	3950	2	0	0
T11	10549	18	0	0
T12	49078	44	0	0
T13	28051	4159	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	832771	0	0
T1	7618	5	0	0
T2	1692	17	0	0
T3	7654	77	0	0
T7	403482	2	0	0
T8	88481	444	0	0
T9	322301	5	0	0
T10	3950	5	0	0
T11	10549	35	0	0
T12	49078	28	0	0
T13	28051	3522	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4874950	0	0
T1	7618	64	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	2655	0	0
T8	88481	929	0	0
T9	322301	3378	0	0
T10	3950	16	0	0
T11	10549	151	0	0
T12	49078	440	0	0
T13	28051	487	0	0

Line Coverage for Instance : tb.dut.u_sm1_43

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_43

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T11
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	286310	0	0
gen_host_fifo[1].idInRange	405209337	380821	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3800997	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	286310	0	0
T1	7618	6	0	0
T2	1692	4	0	0
T3	7654	123	0	0
T7	403482	6	0	0
T8	88481	113	0	0
T9	322301	6	0	0
T10	3950	5	0	0
T11	10549	10	0	0
T12	49078	28	0	0
T13	28051	929	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	380821	0	0
T1	7618	4	0	0
T2	1692	6	0	0
T3	7654	71	0	0
T7	403482	935	0	0
T8	88481	128	0	0
T9	322301	8	0	0
T10	3950	4	0	0
T11	10549	14	0	0
T12	49078	39	0	0
T13	28051	635	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3800997	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	1897	0	0
T8	88481	927	0	0
T9	322301	1915	0	0
T10	3950	30	0	0
T11	10549	68	0	0
T12	49078	265	0	0
T13	28051	465	0	0

Line Coverage for Instance : tb.dut.u_sm1_44

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_44

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	294965	0	0
gen_host_fifo[1].idInRange	405209337	381826	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4083581	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	294965	0	0
T1	7618	3	0	0
T2	1692	10	0	0
T3	7654	82	0	0
T7	403482	3	0	0
T8	88481	135	0	0
T9	322301	10	0	0
T10	3950	4	0	0
T11	10549	18	0	0
T12	49078	38	0	0
T13	28051	961	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	381826	0	0
T1	7618	3	0	0
T2	1692	5	0	0
T3	7654	58	0	0
T7	403482	8	0	0
T8	88481	215	0	0
T9	322301	1	0	0
T10	3950	3	0	0
T11	10549	22	0	0
T12	49078	47	0	0
T13	28051	774	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4083581	0	0
T1	7618	17	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	796	0	0
T8	88481	909	0	0
T9	322301	3512	0	0
T10	3950	54	0	0
T11	10549	136	0	0
T12	49078	304	0	0
T13	28051	534	0	0

Line Coverage for Instance : tb.dut.u_sm1_45

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_45

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	301483	0	0
gen_host_fifo[1].idInRange	405209337	397580	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4067114	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	301483	0	0
T1	7618	3	0	0
T2	1692	9	0	0
T3	7654	80	0	0
T7	403482	3	0	0
T8	88481	160	0	0
T9	322301	5	0	0
T10	3950	5	0	0
T11	10549	27	0	0
T12	49078	39	0	0
T13	28051	0	0	0
T14	0	52	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	397580	0	0
T1	7618	9	0	0
T2	1692	5	0	0
T3	7654	77	0	0
T7	403482	3	0	0
T8	88481	121	0	0
T9	322301	9	0	0
T10	3950	2	0	0
T11	10549	18	0	0
T12	49078	38	0	0
T13	28051	0	0	0
T14	0	53	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4067114	0	0
T1	7618	20	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	1042	0	0
T8	88481	1040	0	0
T9	322301	673	0	0
T10	3950	38	0	0
T11	10549	177	0	0
T12	49078	345	0	0
T13	28051	0	0	0
T14	0	165	0	0

Line Coverage for Instance : tb.dut.u_sm1_46

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_46

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T9
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	308754	0	0
gen_host_fifo[1].idInRange	405209337	416253	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3191892	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	308754	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	75	0	0
T7	403482	4	0	0
T8	88481	137	0	0
T9	322301	15	0	0
T10	3950	3	0	0
T11	10549	24	0	0
T12	49078	41	0	0
T13	28051	1868	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	416253	0	0
T1	7618	17	0	0
T2	1692	3	0	0
T3	7654	71	0	0
T7	403482	7	0	0
T8	88481	187	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	24	0	0
T12	49078	51	0	0
T13	28051	1465	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3191892	0	0
T1	7618	22	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	1633	0	0
T8	88481	1113	0	0
T9	322301	4540	0	0
T10	3950	37	0	0
T11	10549	137	0	0
T12	49078	354	0	0
T13	28051	998	0	0

Line Coverage for Instance : tb.dut.u_sm1_47

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_47

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T3,T7

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T11
1	0	1	Covered	T2,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	281270	0	0
gen_host_fifo[1].idInRange	405209337	371530	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3952179	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	281270	0	0
T2	1692	6	0	0
T3	7654	103	0	0
T7	403482	6	0	0
T8	88481	152	0	0
T9	322301	9	0	0
T10	3950	4	0	0
T11	10549	15	0	0
T12	49078	80	0	0
T13	28051	1083	0	0
T14	39063	64	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	371530	0	0
T1	7618	3	0	0
T2	1692	8	0	0
T3	7654	66	0	0
T7	403482	714	0	0
T8	88481	166	0	0
T9	322301	4	0	0
T10	3950	2	0	0
T11	10549	15	0	0
T12	49078	39	0	0
T13	28051	788	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3952179	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	778	0	0
T8	88481	1081	0	0
T9	322301	3890	0	0
T10	3950	14	0	0
T11	10549	104	0	0
T12	49078	437	0	0
T13	28051	542	0	0

Line Coverage for Instance : tb.dut.u_sm1_48

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_48

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	300409	0	0
gen_host_fifo[1].idInRange	405209337	400644	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3873729	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	300409	0	0
T1	7618	1	0	0
T2	1692	3	0	0
T3	7654	95	0	0
T7	403482	4	0	0
T8	88481	102	0	0
T9	322301	12	0	0
T10	3950	5	0	0
T11	10549	11	0	0
T12	49078	39	0	0
T13	28051	0	0	0
T14	0	43	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	400644	0	0
T1	7618	4	0	0
T2	1692	8	0	0
T3	7654	62	0	0
T7	403482	512	0	0
T8	88481	125	0	0
T9	322301	1	0	0
T10	3950	5	0	0
T11	10549	15	0	0
T12	49078	41	0	0
T13	28051	0	0	0
T14	0	69	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3873729	0	0
T1	7618	17	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	1610	0	0
T8	88481	709	0	0
T9	322301	2905	0	0
T10	3950	35	0	0
T11	10549	80	0	0
T12	49078	310	0	0
T13	28051	0	0	0
T14	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_49

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_49

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T28,T29
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	295655	0	0
gen_host_fifo[1].idInRange	405209337	401815	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4745505	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	295655	0	0
T1	7618	3	0	0
T2	1692	8	0	0
T3	7654	74	0	0
T7	403482	4	0	0
T8	88481	126	0	0
T9	322301	7	0	0
T10	3950	4	0	0
T11	10549	24	0	0
T12	49078	37	0	0
T13	28051	1009	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	401815	0	0
T1	7618	14	0	0
T2	1692	5	0	0
T3	7654	63	0	0
T7	403482	4	0	0
T8	88481	162	0	0
T9	322301	4	0	0
T10	3950	3	0	0
T11	10549	11	0	0
T12	49078	45	0	0
T13	28051	774	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4745505	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	608	0	0
T8	88481	857	0	0
T9	322301	2586	0	0
T10	3950	25	0	0
T11	10549	123	0	0
T12	49078	354	0	0
T13	28051	522	0	0

Line Coverage for Instance : tb.dut.u_sm1_50

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_50

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T18
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	298977	0	0
gen_host_fifo[1].idInRange	405209337	394729	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4058711	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	298977	0	0
T1	7618	6	0	0
T2	1692	5	0	0
T3	7654	79	0	0
T7	403482	3	0	0
T8	88481	131	0	0
T9	322301	21	0	0
T10	3950	4	0	0
T11	10549	9	0	0
T12	49078	32	0	0
T13	28051	1061	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	394729	0	0
T1	7618	1	0	0
T2	1692	3	0	0
T3	7654	69	0	0
T7	403482	6	0	0
T8	88481	194	0	0
T9	322301	5	0	0
T10	3950	4	0	0
T11	10549	17	0	0
T12	49078	29	0	0
T13	28051	782	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4058711	0	0
T1	7618	8	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	349	0	0
T8	88481	962	0	0
T9	322301	3063	0	0
T10	3950	35	0	0
T11	10549	67	0	0
T12	49078	273	0	0
T13	28051	531	0	0

Line Coverage for Instance : tb.dut.u_sm1_51

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_51

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	308523	0	0
gen_host_fifo[1].idInRange	405209337	408285	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3146967	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	308523	0	0
T1	7618	1	0	0
T2	1692	4	0	0
T3	7654	71	0	0
T7	403482	2	0	0
T8	88481	134	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	29	0	0
T12	49078	52	0	0
T13	28051	2905	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	408285	0	0
T1	7618	4	0	0
T2	1692	2	0	0
T3	7654	73	0	0
T7	403482	3	0	0
T8	88481	165	0	0
T9	322301	4	0	0
T10	3950	10	0	0
T11	10549	36	0	0
T12	49078	26	0	0
T13	28051	2112	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3146967	0	0
T1	7618	12	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	1105	0	0
T8	88481	868	0	0
T9	322301	4467	0	0
T10	3950	27	0	0
T11	10549	126	0	0
T12	49078	415	0	0
T13	28051	1503	0	0

Line Coverage for Instance : tb.dut.u_sm1_52

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_52

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	313827	0	0
gen_host_fifo[1].idInRange	405209337	409230	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3873241	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	313827	0	0
T1	7618	2	0	0
T2	1692	11	0	0
T3	7654	85	0	0
T7	403482	3	0	0
T8	88481	172	0	0
T9	322301	10	0	0
T10	3950	5	0	0
T11	10549	30	0	0
T12	49078	36	0	0
T13	28051	1057	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	409230	0	0
T1	7618	2	0	0
T2	1692	3	0	0
T3	7654	72	0	0
T7	403482	7	0	0
T8	88481	149	0	0
T9	322301	16	0	0
T10	3950	5	0	0
T11	10549	10	0	0
T12	49078	46	0	0
T13	28051	712	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3873241	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	653	0	0
T8	88481	966	0	0
T9	322301	2440	0	0
T10	3950	28	0	0
T11	10549	145	0	0
T12	49078	260	0	0
T13	28051	530	0	0

Line Coverage for Instance : tb.dut.u_sm1_53

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_53

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T11
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	330900	0	0
gen_host_fifo[1].idInRange	405209337	441113	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3622780	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	330900	0	0
T1	7618	3	0	0
T2	1692	8	0	0
T3	7654	74	0	0
T7	403482	3	0	0
T8	88481	114	0	0
T9	322301	13	0	0
T10	3950	2	0	0
T11	10549	19	0	0
T12	49078	45	0	0
T13	28051	0	0	0
T14	0	76	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	441113	0	0
T1	7618	1	0	0
T2	1692	6	0	0
T3	7654	90	0	0
T7	403482	9	0	0
T8	88481	161	0	0
T9	322301	12	0	0
T10	3950	3	0	0
T11	10549	17	0	0
T12	49078	36	0	0
T13	28051	0	0	0
T14	0	72	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3622780	0	0
T1	7618	12	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	678	0	0
T8	88481	1123	0	0
T9	322301	4938	0	0
T10	3950	17	0	0
T11	10549	118	0	0
T12	49078	382	0	0
T13	28051	0	0	0
T14	0	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_54

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_54

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	315013	0	0
gen_host_fifo[1].idInRange	405209337	429246	0	0
maxM	900	900	0	0
rspIdInRange	405209337	3403287	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	315013	0	0
T1	7618	8	0	0
T2	1692	3	0	0
T3	7654	88	0	0
T7	403482	4	0	0
T8	88481	157	0	0
T9	322301	6	0	0
T10	3950	4	0	0
T11	10549	15	0	0
T12	49078	33	0	0
T13	28051	861	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	429246	0	0
T1	7618	4	0	0
T2	1692	4	0	0
T3	7654	83	0	0
T7	403482	400	0	0
T8	88481	176	0	0
T9	322301	6	0	0
T10	3950	10	0	0
T11	10549	28	0	0
T12	49078	33	0	0
T13	28051	661	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3403287	0	0
T1	7618	40	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	1064	0	0
T8	88481	1197	0	0
T9	322301	2087	0	0
T10	3950	37	0	0
T11	10549	107	0	0
T12	49078	300	0	0
T13	28051	446	0	0

Line Coverage for Instance : tb.dut.u_sm1_55

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_55

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T11
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	322085	0	0
gen_host_fifo[1].idInRange	405209337	416441	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4407979	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	322085	0	0
T1	7618	3	0	0
T2	1692	6	0	0
T3	7654	56	0	0
T7	403482	4	0	0
T8	88481	136	0	0
T9	322301	12	0	0
T10	3950	4	0	0
T11	10549	11	0	0
T12	49078	34	0	0
T13	28051	0	0	0
T14	0	64	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	416441	0	0
T1	7618	5	0	0
T2	1692	4	0	0
T3	7654	66	0	0
T7	403482	4	0	0
T8	88481	149	0	0
T9	322301	9	0	0
T10	3950	7	0	0
T11	10549	34	0	0
T12	49078	42	0	0
T13	28051	0	0	0
T14	0	46	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4407979	0	0
T1	7618	29	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	526	0	0
T8	88481	795	0	0
T9	322301	5092	0	0
T10	3950	45	0	0
T11	10549	126	0	0
T12	49078	323	0	0
T13	28051	0	0	0
T14	0	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_56

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T11
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	338993	0	0
gen_host_fifo[1].idInRange	405209337	440335	0	0
maxM	900	900	0	0
rspIdInRange	405209337	4489417	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	338993	0	0
T1	7618	2	0	0
T2	1692	4	0	0
T3	7654	96	0	0
T7	403482	1	0	0
T8	88481	144	0	0
T9	322301	12	0	0
T10	3950	1	0	0
T11	10549	24	0	0
T12	49078	50	0	0
T13	28051	0	0	0
T14	0	90	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	440335	0	0
T1	7618	4	0	0
T2	1692	2	0	0
T3	7654	64	0	0
T7	403482	4	0	0
T8	88481	210	0	0
T9	322301	4	0	0
T10	3950	3	0	0
T11	10549	33	0	0
T12	49078	47	0	0
T13	28051	0	0	0
T14	0	44	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4489417	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	692	0	0
T8	88481	944	0	0
T9	322301	2664	0	0
T10	3950	10	0	0
T11	10549	137	0	0
T12	49078	463	0	0
T13	28051	0	0	0
T14	0	151	0	0

Line Coverage for Instance : tb.dut.u_sm1_30

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	405209337	10614279	0	0
gen_host_fifo[1].idInRange	405209337	1930214	0	0
gen_host_fifo[2].idInRange	405209337	2041883	0	0
maxM	900	900	0	0
rspIdInRange	405209337	20135358	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	10614279	0	0
T1	7618	345	0	0
T2	1692	47	0	0
T3	7654	494	0	0
T7	403482	9996	0	0
T8	88481	4893	0	0
T9	322301	107	0	0
T10	3950	330	0	0
T11	10549	803	0	0
T12	49078	1830	0	0
T13	28051	946	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1930214	0	0
T1	7618	19	0	0
T2	1692	8	0	0
T3	7654	65	0	0
T7	403482	1749	0	0
T8	88481	1055	0	0
T9	322301	25	0	0
T10	3950	24	0	0
T11	10549	123	0	0
T12	49078	287	0	0
T13	28051	0	0	0
T14	0	302	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	2041883	0	0
T1	7618	47	0	0
T2	1692	4	0	0
T3	7654	68	0	0
T7	403482	161	0	0
T8	88481	980	0	0
T9	322301	18	0	0
T10	3950	7	0	0
T11	10549	117	0	0
T12	49078	309	0	0
T13	28051	0	0	0
T14	0	409	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	20135358	0	0
T1	7618	143	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	6717	0	0
T8	88481	6119	0	0
T9	322301	7822	0	0
T10	3950	334	0	0
T11	10549	477	0	0
T12	49078	2123	0	0
T13	28051	946	0	0