Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7676101	0	0
GntImpliesValid_A	2147483647	7676101	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7676101	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	448479613	0	0
ReadyAndValidImplyGrant_A	2147483647	7676101	0	0
ReqAndReadyImplyGrant_A	2147483647	7676101	0	0
ReqImpliesValid_A	2147483647	35448239	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	31602	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7676101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	182832	182592	0	0
T2	40608	40128	0	0
T3	183696	183528	0	0
T7	9683568	9682224	0	0
T8	2123544	2123112	0	0
T9	7735224	7734456	0	0
T10	94800	94512	0	0
T11	253176	252648	0	0
T12	1177872	1176720	0	0
T13	673224	672576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7676101	0	0
T1	182832	355	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	380	0	0
T8	2123544	7964	0	0
T9	7735224	430	0	0
T10	94800	272	0	0
T11	253176	1149	0	0
T12	1177872	2786	0	0
T13	673224	12875	0	0
T14	0	797	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7676101	0	0
T1	182832	355	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	380	0	0
T8	2123544	7964	0	0
T9	7735224	430	0	0
T10	94800	272	0	0
T11	253176	1149	0	0
T12	1177872	2786	0	0
T13	673224	12875	0	0
T14	0	797	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	182832	182592	0	0
T2	40608	40128	0	0
T3	183696	183528	0	0
T7	9683568	9682224	0	0
T8	2123544	2123112	0	0
T9	7735224	7734456	0	0
T10	94800	94512	0	0
T11	253176	252648	0	0
T12	1177872	1176720	0	0
T13	673224	672576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	182832	182592	0	0
T2	40608	40128	0	0
T3	183696	183528	0	0
T7	9683568	9682224	0	0
T8	2123544	2123112	0	0
T9	7735224	7734456	0	0
T10	94800	94512	0	0
T11	253176	252648	0	0
T12	1177872	1176720	0	0
T13	673224	672576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7676101	0	0
T1	182832	355	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	380	0	0
T8	2123544	7964	0	0
T9	7735224	430	0	0
T10	94800	272	0	0
T11	253176	1149	0	0
T12	1177872	2786	0	0
T13	673224	12875	0	0
T14	0	797	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448479613	0	0
T1	182832	8818	0	0
T2	40608	447	0	0
T3	183696	5125	0	0
T7	9683568	512749	0	0
T8	2123544	134597	0	0
T9	7735224	270451	0	0
T10	94800	5092	0	0
T11	253176	15805	0	0
T12	1177872	62922	0	0
T13	673224	1577	0	0
T14	0	1250	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7676101	0	0
T1	182832	355	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	380	0	0
T8	2123544	7964	0	0
T9	7735224	430	0	0
T10	94800	272	0	0
T11	253176	1149	0	0
T12	1177872	2786	0	0
T13	673224	12875	0	0
T14	0	797	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7676101	0	0
T1	182832	355	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	380	0	0
T8	2123544	7964	0	0
T9	7735224	430	0	0
T10	94800	272	0	0
T11	253176	1149	0	0
T12	1177872	2786	0	0
T13	673224	12875	0	0
T14	0	797	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35448239	0	0
T1	182832	822	0	0
T2	40608	513	0	0
T3	183696	5913	0	0
T7	9683568	23986	0	0
T8	2123544	18455	0	0
T9	7735224	683	0	0
T10	94800	624	0	0
T11	253176	2573	0	0
T12	1177872	5063	0	0
T13	673224	31218	0	0
T14	0	1015	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31602	0	21600
T3	15308	16	0	2
T7	806964	0	0	2
T8	176962	1	0	2
T9	644602	0	0	2
T10	7900	0	0	2
T11	21098	0	0	2
T12	98156	1	0	2
T13	56102	0	0	2
T14	78126	0	0	2
T15	0	42	0	0
T16	0	25	0	0
T17	0	22	0	0
T18	0	1	0	0
T19	0	14	0	0
T20	0	24	0	0
T21	0	5	0	0
T22	0	1	0	0
T23	0	14	0	0
T24	0	9	0	0
T25	0	1	0	0
T26	954920	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	182832	182592	0	0
T2	40608	40128	0	0
T3	183696	183528	0	0
T7	9683568	9682224	0	0
T8	2123544	2123112	0	0
T9	7735224	7734456	0	0
T10	94800	94512	0	0
T11	253176	252648	0	0
T12	1177872	1176720	0	0
T13	673224	672576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7676101	0	0
T1	182832	355	0	0
T2	40608	429	0	0
T3	183696	5233	0	0
T7	9683568	380	0	0
T8	2123544	7964	0	0
T9	7735224	430	0	0
T10	94800	272	0	0
T11	253176	1149	0	0
T12	1177872	2786	0	0
T13	673224	12875	0	0
T14	0	797	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	856654	0	0
GntImpliesValid_A	405209337	856654	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	856654	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	12388515	0	0
ReadyAndValidImplyGrant_A	405209337	856654	0	0
ReqAndReadyImplyGrant_A	405209337	856654	0	0
ReqImpliesValid_A	405209337	2504038	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	856654	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	856654	0	0
T1	7618	35	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	54	0	0
T8	88481	864	0	0
T9	322301	33	0	0
T10	3950	22	0	0
T11	10549	129	0	0
T12	49078	309	0	0
T13	28051	1746	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	856654	0	0
T1	7618	35	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	54	0	0
T8	88481	864	0	0
T9	322301	33	0	0
T10	3950	22	0	0
T11	10549	129	0	0
T12	49078	309	0	0
T13	28051	1746	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	856654	0	0
T1	7618	35	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	54	0	0
T8	88481	864	0	0
T9	322301	33	0	0
T10	3950	22	0	0
T11	10549	129	0	0
T12	49078	309	0	0
T13	28051	1746	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	12388515	0	0
T1	7618	261	0	0
T2	1692	39	0	0
T3	7654	440	0	0
T7	403482	17761	0	0
T8	88481	6226	0	0
T9	322301	129	0	0
T10	3950	166	0	0
T11	10549	921	0	0
T12	49078	2370	0	0
T13	28051	660	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	856654	0	0
T1	7618	35	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	54	0	0
T8	88481	864	0	0
T9	322301	33	0	0
T10	3950	22	0	0
T11	10549	129	0	0
T12	49078	309	0	0
T13	28051	1746	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	856654	0	0
T1	7618	35	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	54	0	0
T8	88481	864	0	0
T9	322301	33	0	0
T10	3950	22	0	0
T11	10549	129	0	0
T12	49078	309	0	0
T13	28051	1746	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	2504038	0	0
T1	7618	40	0	0
T2	1692	72	0	0
T3	7654	809	0	0
T7	403482	417	0	0
T8	88481	1530	0	0
T9	322301	44	0	0
T10	3950	25	0	0
T11	10549	236	0	0
T12	49078	392	0	0
T13	28051	2833	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	856654	0	0
T1	7618	35	0	0
T2	1692	55	0	0
T3	7654	624	0	0
T7	403482	54	0	0
T8	88481	864	0	0
T9	322301	33	0	0
T10	3950	22	0	0
T11	10549	129	0	0
T12	49078	309	0	0
T13	28051	1746	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	846182	0	0
GntImpliesValid_A	405209337	846182	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	846182	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	12511799	0	0
ReadyAndValidImplyGrant_A	405209337	846182	0	0
ReqAndReadyImplyGrant_A	405209337	846182	0	0
ReqImpliesValid_A	405209337	2462512	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	846182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846182	0	0
T1	7618	39	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	54	0	0
T8	88481	903	0	0
T9	322301	49	0	0
T10	3950	30	0	0
T11	10549	120	0	0
T12	49078	306	0	0
T13	28051	1680	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846182	0	0
T1	7618	39	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	54	0	0
T8	88481	903	0	0
T9	322301	49	0	0
T10	3950	30	0	0
T11	10549	120	0	0
T12	49078	306	0	0
T13	28051	1680	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846182	0	0
T1	7618	39	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	54	0	0
T8	88481	903	0	0
T9	322301	49	0	0
T10	3950	30	0	0
T11	10549	120	0	0
T12	49078	306	0	0
T13	28051	1680	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	12511799	0	0
T1	7618	274	0	0
T2	1692	41	0	0
T3	7654	437	0	0
T7	403482	17992	0	0
T8	88481	6652	0	0
T9	322301	253	0	0
T10	3950	262	0	0
T11	10549	714	0	0
T12	49078	2374	0	0
T13	28051	677	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846182	0	0
T1	7618	39	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	54	0	0
T8	88481	903	0	0
T9	322301	49	0	0
T10	3950	30	0	0
T11	10549	120	0	0
T12	49078	306	0	0
T13	28051	1680	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846182	0	0
T1	7618	39	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	54	0	0
T8	88481	903	0	0
T9	322301	49	0	0
T10	3950	30	0	0
T11	10549	120	0	0
T12	49078	306	0	0
T13	28051	1680	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	2462512	0	0
T1	7618	50	0	0
T2	1692	76	0	0
T3	7654	736	0	0
T7	403482	1651	0	0
T8	88481	1785	0	0
T9	322301	91	0	0
T10	3950	32	0	0
T11	10549	237	0	0
T12	49078	351	0	0
T13	28051	2684	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846182	0	0
T1	7618	39	0	0
T2	1692	58	0	0
T3	7654	586	0	0
T7	403482	54	0	0
T8	88481	903	0	0
T9	322301	49	0	0
T10	3950	30	0	0
T11	10549	120	0	0
T12	49078	306	0	0
T13	28051	1680	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	228323	0	0
GntImpliesValid_A	405209337	228323	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	228323	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3163409	0	0
ReadyAndValidImplyGrant_A	405209337	228323	0	0
ReqAndReadyImplyGrant_A	405209337	228323	0	0
ReqImpliesValid_A	405209337	662524	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	228323	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	228323	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	16	0	0
T8	88481	219	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	29	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	228323	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	16	0	0
T8	88481	219	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	29	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	228323	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	16	0	0
T8	88481	219	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	29	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	80	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3163409	0	0
T1	7618	89	0	0
T2	1692	8	0	0
T3	7654	133	0	0
T7	403482	5108	0	0
T8	88481	1638	0	0
T9	322301	41	0	0
T10	3950	70	0	0
T11	10549	204	0	0
T12	49078	592	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	228323	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	16	0	0
T8	88481	219	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	29	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	228323	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	16	0	0
T8	88481	219	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	29	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	662524	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	150	0	0
T7	403482	1030	0	0
T8	88481	255	0	0
T9	322301	18	0	0
T10	3950	18	0	0
T11	10549	35	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	228323	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	141	0	0
T7	403482	16	0	0
T8	88481	219	0	0
T9	322301	9	0	0
T10	3950	10	0	0
T11	10549	29	0	0
T12	49078	85	0	0
T13	28051	0	0	0
T14	0	80	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	215088	0	0
GntImpliesValid_A	405209337	215088	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	215088	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3141756	0	0
ReadyAndValidImplyGrant_A	405209337	215088	0	0
ReqAndReadyImplyGrant_A	405209337	215088	0	0
ReqImpliesValid_A	405209337	621139	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	215088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	215088	0	0
T1	7618	13	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	12	0	0
T8	88481	227	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	28	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	215088	0	0
T1	7618	13	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	12	0	0
T8	88481	227	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	28	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	215088	0	0
T1	7618	13	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	12	0	0
T8	88481	227	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	28	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3141756	0	0
T1	7618	64	0	0
T2	1692	10	0	0
T3	7654	145	0	0
T7	403482	4002	0	0
T8	88481	1768	0	0
T9	322301	73	0	0
T10	3950	20	0	0
T11	10549	211	0	0
T12	49078	548	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	215088	0	0
T1	7618	13	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	12	0	0
T8	88481	227	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	28	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	215088	0	0
T1	7618	13	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	12	0	0
T8	88481	227	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	28	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	621139	0	0
T1	7618	14	0	0
T2	1692	9	0	0
T3	7654	156	0	0
T7	403482	801	0	0
T8	88481	317	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	40	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	215088	0	0
T1	7618	13	0	0
T2	1692	9	0	0
T3	7654	150	0	0
T7	403482	12	0	0
T8	88481	227	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	28	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	207248	0	0
GntImpliesValid_A	405209337	207248	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	207248	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	4866723	0	0
ReadyAndValidImplyGrant_A	405209337	207248	0	0
ReqAndReadyImplyGrant_A	405209337	207248	0	0
ReqImpliesValid_A	405209337	1156172	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	207248	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	207248	0	0
T1	7618	12	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	230	0	0
T9	322301	10	0	0
T10	3950	7	0	0
T11	10549	29	0	0
T12	49078	77	0	0
T13	28051	997	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	207248	0	0
T1	7618	12	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	230	0	0
T9	322301	10	0	0
T10	3950	7	0	0
T11	10549	29	0	0
T12	49078	77	0	0
T13	28051	997	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	207248	0	0
T1	7618	12	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	230	0	0
T9	322301	10	0	0
T10	3950	7	0	0
T11	10549	29	0	0
T12	49078	77	0	0
T13	28051	997	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	4866723	0	0
T1	7618	125	0	0
T2	1692	70	0	0
T3	7654	688	0	0
T7	403482	2722	0	0
T8	88481	2135	0	0
T9	322301	65	0	0
T10	3950	95	0	0
T11	10549	166	0	0
T12	49078	826	0	0
T13	28051	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	207248	0	0
T1	7618	12	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	230	0	0
T9	322301	10	0	0
T10	3950	7	0	0
T11	10549	29	0	0
T12	49078	77	0	0
T13	28051	997	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	207248	0	0
T1	7618	12	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	230	0	0
T9	322301	10	0	0
T10	3950	7	0	0
T11	10549	29	0	0
T12	49078	77	0	0
T13	28051	997	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1156172	0	0
T1	7618	27	0	0
T2	1692	20	0	0
T3	7654	207	0	0
T7	403482	5	0	0
T8	88481	359	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	45	0	0
T12	49078	77	0	0
T13	28051	7707	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	207248	0	0
T1	7618	12	0	0
T2	1692	16	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	230	0	0
T9	322301	10	0	0
T10	3950	7	0	0
T11	10549	29	0	0
T12	49078	77	0	0
T13	28051	997	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	209336	0	0
GntImpliesValid_A	405209337	209336	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	209336	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	5127253	0	0
ReadyAndValidImplyGrant_A	405209337	209336	0	0
ReqAndReadyImplyGrant_A	405209337	209336	0	0
ReqImpliesValid_A	405209337	1004647	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	209336	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209336	0	0
T1	7618	19	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	11	0	0
T8	88481	214	0	0
T9	322301	15	0	0
T10	3950	4	0	0
T11	10549	39	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209336	0	0
T1	7618	19	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	11	0	0
T8	88481	214	0	0
T9	322301	15	0	0
T10	3950	4	0	0
T11	10549	39	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209336	0	0
T1	7618	19	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	11	0	0
T8	88481	214	0	0
T9	322301	15	0	0
T10	3950	4	0	0
T11	10549	39	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	5127253	0	0
T1	7618	141	0	0
T2	1692	34	0	0
T3	7654	425	0	0
T7	403482	7865	0	0
T8	88481	6161	0	0
T9	322301	467	0	0
T10	3950	35	0	0
T11	10549	380	0	0
T12	49078	1069	0	0
T13	28051	0	0	0
T14	0	663	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209336	0	0
T1	7618	19	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	11	0	0
T8	88481	214	0	0
T9	322301	15	0	0
T10	3950	4	0	0
T11	10549	39	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209336	0	0
T1	7618	19	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	11	0	0
T8	88481	214	0	0
T9	322301	15	0	0
T10	3950	4	0	0
T11	10549	39	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1004647	0	0
T1	7618	47	0	0
T2	1692	19	0	0
T3	7654	169	0	0
T7	403482	2763	0	0
T8	88481	510	0	0
T9	322301	30	0	0
T10	3950	4	0	0
T11	10549	69	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	98	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209336	0	0
T1	7618	19	0	0
T2	1692	11	0	0
T3	7654	132	0	0
T7	403482	11	0	0
T8	88481	214	0	0
T9	322301	15	0	0
T10	3950	4	0	0
T11	10549	39	0	0
T12	49078	78	0	0
T13	28051	0	0	0
T14	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	214355	0	0
GntImpliesValid_A	405209337	214355	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	214355	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	6037421	0	0
ReadyAndValidImplyGrant_A	405209337	214355	0	0
ReqAndReadyImplyGrant_A	405209337	214355	0	0
ReqImpliesValid_A	405209337	1414087	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	214355	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214355	0	0
T1	7618	10	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	15	0	0
T8	88481	233	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	40	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	93	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214355	0	0
T1	7618	10	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	15	0	0
T8	88481	233	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	40	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	93	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214355	0	0
T1	7618	10	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	15	0	0
T8	88481	233	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	40	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	93	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	6037421	0	0
T1	7618	46	0	0
T2	1692	47	0	0
T3	7654	474	0	0
T7	403482	6003	0	0
T8	88481	4134	0	0
T9	322301	102	0	0
T10	3950	56	0	0
T11	10549	260	0	0
T12	49078	885	0	0
T13	28051	0	0	0
T14	0	587	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214355	0	0
T1	7618	10	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	15	0	0
T8	88481	233	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	40	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	93	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214355	0	0
T1	7618	10	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	15	0	0
T8	88481	233	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	40	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	93	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1414087	0	0
T1	7618	10	0	0
T2	1692	37	0	0
T3	7654	210	0	0
T7	403482	236	0	0
T8	88481	499	0	0
T9	322301	7	0	0
T10	3950	20	0	0
T11	10549	46	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214355	0	0
T1	7618	10	0	0
T2	1692	16	0	0
T3	7654	147	0	0
T7	403482	15	0	0
T8	88481	233	0	0
T9	322301	7	0	0
T10	3950	5	0	0
T11	10549	40	0	0
T12	49078	73	0	0
T13	28051	0	0	0
T14	0	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	214720	0	0
GntImpliesValid_A	405209337	214720	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	214720	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	5242860	0	0
ReadyAndValidImplyGrant_A	405209337	214720	0	0
ReqAndReadyImplyGrant_A	405209337	214720	0	0
ReqImpliesValid_A	405209337	1159590	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	214720	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214720	0	0
T1	7618	13	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	237	0	0
T9	322301	13	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	72	0	0
T13	28051	487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214720	0	0
T1	7618	13	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	237	0	0
T9	322301	13	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	72	0	0
T13	28051	487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214720	0	0
T1	7618	13	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	237	0	0
T9	322301	13	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	72	0	0
T13	28051	487	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	5242860	0	0
T1	7618	64	0	0
T2	1692	38	0	0
T3	7654	461	0	0
T7	403482	3088	0	0
T8	88481	5373	0	0
T9	322301	74	0	0
T10	3950	55	0	0
T11	10549	253	0	0
T12	49078	1028	0	0
T13	28051	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214720	0	0
T1	7618	13	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	237	0	0
T9	322301	13	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	72	0	0
T13	28051	487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214720	0	0
T1	7618	13	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	237	0	0
T9	322301	13	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	72	0	0
T13	28051	487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	1159590	0	0
T1	7618	19	0	0
T2	1692	22	0	0
T3	7654	174	0	0
T7	403482	8	0	0
T8	88481	757	0	0
T9	322301	20	0	0
T10	3950	7	0	0
T11	10549	53	0	0
T12	49078	72	0	0
T13	28051	4159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214720	0	0
T1	7618	13	0	0
T2	1692	12	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	237	0	0
T9	322301	13	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	72	0	0
T13	28051	487	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	211326	0	0
GntImpliesValid_A	405209337	211326	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	211326	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3145011	0	0
ReadyAndValidImplyGrant_A	405209337	211326	0	0
ReqAndReadyImplyGrant_A	405209337	211326	0	0
ReqImpliesValid_A	405209337	562559	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	211326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	211326	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	11	0	0
T8	88481	201	0	0
T9	322301	12	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	465	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	211326	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	11	0	0
T8	88481	201	0	0
T9	322301	12	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	465	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	211326	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	11	0	0
T8	88481	201	0	0
T9	322301	12	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	465	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3145011	0	0
T1	7618	71	0	0
T2	1692	11	0	0
T3	7654	160	0	0
T7	403482	2764	0	0
T8	88481	1497	0	0
T9	322301	56	0	0
T10	3950	87	0	0
T11	10549	195	0	0
T12	49078	520	0	0
T13	28051	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	211326	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	11	0	0
T8	88481	201	0	0
T9	322301	12	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	465	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	211326	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	11	0	0
T8	88481	201	0	0
T9	322301	12	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	465	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	562559	0	0
T1	7618	10	0	0
T2	1692	10	0	0
T3	7654	193	0	0
T7	403482	941	0	0
T8	88481	241	0	0
T9	322301	14	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	929	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	211326	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	176	0	0
T7	403482	11	0	0
T8	88481	201	0	0
T9	322301	12	0	0
T10	3950	9	0	0
T11	10549	24	0	0
T12	49078	67	0	0
T13	28051	465	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	201102	0	0
GntImpliesValid_A	405209337	201102	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	201102	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3008557	0	0
ReadyAndValidImplyGrant_A	405209337	201102	0	0
ReqAndReadyImplyGrant_A	405209337	201102	0	0
ReqImpliesValid_A	405209337	558255	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	201102	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	201102	0	0
T1	7618	6	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	11	0	0
T8	88481	227	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	83	0	0
T13	28051	534	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	201102	0	0
T1	7618	6	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	11	0	0
T8	88481	227	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	83	0	0
T13	28051	534	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	201102	0	0
T1	7618	6	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	11	0	0
T8	88481	227	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	83	0	0
T13	28051	534	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3008557	0	0
T1	7618	45	0	0
T2	1692	14	0	0
T3	7654	125	0	0
T7	403482	3265	0	0
T8	88481	1634	0	0
T9	322301	42	0	0
T10	3950	67	0	0
T11	10549	321	0	0
T12	49078	705	0	0
T13	28051	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	201102	0	0
T1	7618	6	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	11	0	0
T8	88481	227	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	83	0	0
T13	28051	534	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	201102	0	0
T1	7618	6	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	11	0	0
T8	88481	227	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	83	0	0
T13	28051	534	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	558255	0	0
T1	7618	6	0	0
T2	1692	15	0	0
T3	7654	138	0	0
T7	403482	11	0	0
T8	88481	342	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	85	0	0
T13	28051	1015	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	201102	0	0
T1	7618	6	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	11	0	0
T8	88481	227	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	40	0	0
T12	49078	83	0	0
T13	28051	534	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	209963	0	0
GntImpliesValid_A	405209337	209963	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	209963	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3124613	0	0
ReadyAndValidImplyGrant_A	405209337	209963	0	0
ReqAndReadyImplyGrant_A	405209337	209963	0	0
ReqImpliesValid_A	405209337	582933	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	209963	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209963	0	0
T1	7618	8	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	6	0	0
T8	88481	226	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	30	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209963	0	0
T1	7618	8	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	6	0	0
T8	88481	226	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	30	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209963	0	0
T1	7618	8	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	6	0	0
T8	88481	226	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	30	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3124613	0	0
T1	7618	68	0	0
T2	1692	13	0	0
T3	7654	140	0	0
T7	403482	2507	0	0
T8	88481	1646	0	0
T9	322301	58	0	0
T10	3950	84	0	0
T11	10549	257	0	0
T12	49078	579	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209963	0	0
T1	7618	8	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	6	0	0
T8	88481	226	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	30	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209963	0	0
T1	7618	8	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	6	0	0
T8	88481	226	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	30	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	582933	0	0
T1	7618	12	0	0
T2	1692	14	0	0
T3	7654	155	0	0
T7	403482	6	0	0
T8	88481	281	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	45	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	105	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	209963	0	0
T1	7618	8	0	0
T2	1692	13	0	0
T3	7654	147	0	0
T7	403482	6	0	0
T8	88481	226	0	0
T9	322301	14	0	0
T10	3950	7	0	0
T11	10549	30	0	0
T12	49078	77	0	0
T13	28051	0	0	0
T14	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	212535	0	0
GntImpliesValid_A	405209337	212535	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	212535	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3078022	0	0
ReadyAndValidImplyGrant_A	405209337	212535	0	0
ReqAndReadyImplyGrant_A	405209337	212535	0	0
ReqImpliesValid_A	405209337	609887	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	212535	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	212535	0	0
T1	7618	16	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	11	0	0
T8	88481	231	0	0
T9	322301	20	0	0
T10	3950	12	0	0
T11	10549	37	0	0
T12	49078	89	0	0
T13	28051	998	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	212535	0	0
T1	7618	16	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	11	0	0
T8	88481	231	0	0
T9	322301	20	0	0
T10	3950	12	0	0
T11	10549	37	0	0
T12	49078	89	0	0
T13	28051	998	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	212535	0	0
T1	7618	16	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	11	0	0
T8	88481	231	0	0
T9	322301	20	0	0
T10	3950	12	0	0
T11	10549	37	0	0
T12	49078	89	0	0
T13	28051	998	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3078022	0	0
T1	7618	113	0	0
T2	1692	11	0	0
T3	7654	136	0	0
T7	403482	4060	0	0
T8	88481	1632	0	0
T9	322301	90	0	0
T10	3950	73	0	0
T11	10549	267	0	0
T12	49078	699	0	0
T13	28051	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	212535	0	0
T1	7618	16	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	11	0	0
T8	88481	231	0	0
T9	322301	20	0	0
T10	3950	12	0	0
T11	10549	37	0	0
T12	49078	89	0	0
T13	28051	998	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	212535	0	0
T1	7618	16	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	11	0	0
T8	88481	231	0	0
T9	322301	20	0	0
T10	3950	12	0	0
T11	10549	37	0	0
T12	49078	89	0	0
T13	28051	998	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	609887	0	0
T1	7618	22	0	0
T2	1692	14	0	0
T3	7654	145	0	0
T7	403482	11	0	0
T8	88481	324	0	0
T9	322301	24	0	0
T10	3950	13	0	0
T11	10549	48	0	0
T12	49078	92	0	0
T13	28051	1935	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	212535	0	0
T1	7618	16	0	0
T2	1692	12	0	0
T3	7654	140	0	0
T7	403482	11	0	0
T8	88481	231	0	0
T9	322301	20	0	0
T10	3950	12	0	0
T11	10549	37	0	0
T12	49078	89	0	0
T13	28051	998	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	206854	0	0
GntImpliesValid_A	405209337	206854	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	206854	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3083100	0	0
ReadyAndValidImplyGrant_A	405209337	206854	0	0
ReqAndReadyImplyGrant_A	405209337	206854	0	0
ReqImpliesValid_A	405209337	550848	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	206854	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	206854	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	240	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	25	0	0
T12	49078	93	0	0
T13	28051	542	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	206854	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	240	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	25	0	0
T12	49078	93	0	0
T13	28051	542	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	206854	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	240	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	25	0	0
T12	49078	93	0	0
T13	28051	542	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3083100	0	0
T1	7618	19	0	0
T2	1692	15	0	0
T3	7654	146	0	0
T7	403482	4128	0	0
T8	88481	1719	0	0
T9	322301	50	0	0
T10	3950	42	0	0
T11	10549	170	0	0
T12	49078	749	0	0
T13	28051	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	206854	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	240	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	25	0	0
T12	49078	93	0	0
T13	28051	542	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	206854	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	240	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	25	0	0
T12	49078	93	0	0
T13	28051	542	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	550848	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	169	0	0
T7	403482	720	0	0
T8	88481	318	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	30	0	0
T12	49078	118	0	0
T13	28051	1083	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	206854	0	0
T1	7618	3	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	240	0	0
T9	322301	13	0	0
T10	3950	6	0	0
T11	10549	25	0	0
T12	49078	93	0	0
T13	28051	542	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	210303	0	0
GntImpliesValid_A	405209337	210303	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	210303	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3130664	0	0
ReadyAndValidImplyGrant_A	405209337	210303	0	0
ReqAndReadyImplyGrant_A	405209337	210303	0	0
ReqImpliesValid_A	405209337	588396	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	210303	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210303	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	181	0	0
T9	322301	7	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210303	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	181	0	0
T9	322301	7	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210303	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	181	0	0
T9	322301	7	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3130664	0	0
T1	7618	53	0	0
T2	1692	12	0	0
T3	7654	129	0	0
T7	403482	2967	0	0
T8	88481	1388	0	0
T9	322301	38	0	0
T10	3950	74	0	0
T11	10549	192	0	0
T12	49078	717	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210303	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	181	0	0
T9	322301	7	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210303	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	181	0	0
T9	322301	7	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	588396	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	154	0	0
T7	403482	516	0	0
T8	88481	222	0	0
T9	322301	13	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210303	0	0
T1	7618	5	0	0
T2	1692	11	0	0
T3	7654	141	0	0
T7	403482	8	0	0
T8	88481	181	0	0
T9	322301	7	0	0
T10	3950	10	0	0
T11	10549	26	0	0
T12	49078	80	0	0
T13	28051	0	0	0
T14	0	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	214467	0	0
GntImpliesValid_A	405209337	214467	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	214467	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3116833	0	0
ReadyAndValidImplyGrant_A	405209337	214467	0	0
ReqAndReadyImplyGrant_A	405209337	214467	0	0
ReqImpliesValid_A	405209337	583321	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	214467	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214467	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	8	0	0
T8	88481	207	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	28	0	0
T12	49078	78	0	0
T13	28051	522	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214467	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	8	0	0
T8	88481	207	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	28	0	0
T12	49078	78	0	0
T13	28051	522	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214467	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	8	0	0
T8	88481	207	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	28	0	0
T12	49078	78	0	0
T13	28051	522	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3116833	0	0
T1	7618	119	0	0
T2	1692	14	0	0
T3	7654	131	0	0
T7	403482	2992	0	0
T8	88481	1508	0	0
T9	322301	53	0	0
T10	3950	36	0	0
T11	10549	207	0	0
T12	49078	549	0	0
T13	28051	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214467	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	8	0	0
T8	88481	207	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	28	0	0
T12	49078	78	0	0
T13	28051	522	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214467	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	8	0	0
T8	88481	207	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	28	0	0
T12	49078	78	0	0
T13	28051	522	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	583321	0	0
T1	7618	17	0	0
T2	1692	13	0	0
T3	7654	136	0	0
T7	403482	8	0	0
T8	88481	288	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	35	0	0
T12	49078	82	0	0
T13	28051	1027	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214467	0	0
T1	7618	11	0	0
T2	1692	13	0	0
T3	7654	133	0	0
T7	403482	8	0	0
T8	88481	207	0	0
T9	322301	11	0	0
T10	3950	7	0	0
T11	10549	28	0	0
T12	49078	78	0	0
T13	28051	522	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	214542	0	0
GntImpliesValid_A	405209337	214542	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	214542	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3115715	0	0
ReadyAndValidImplyGrant_A	405209337	214542	0	0
ReqAndReadyImplyGrant_A	405209337	214542	0	0
ReqImpliesValid_A	405209337	578594	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	214542	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214542	0	0
T1	7618	7	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	9	0	0
T8	88481	215	0	0
T9	322301	16	0	0
T10	3950	8	0	0
T11	10549	24	0	0
T12	49078	61	0	0
T13	28051	531	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214542	0	0
T1	7618	7	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	9	0	0
T8	88481	215	0	0
T9	322301	16	0	0
T10	3950	8	0	0
T11	10549	24	0	0
T12	49078	61	0	0
T13	28051	531	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214542	0	0
T1	7618	7	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	9	0	0
T8	88481	215	0	0
T9	322301	16	0	0
T10	3950	8	0	0
T11	10549	24	0	0
T12	49078	61	0	0
T13	28051	531	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3115715	0	0
T1	7618	61	0	0
T2	1692	7	0	0
T3	7654	131	0	0
T7	403482	3512	0	0
T8	88481	1514	0	0
T9	322301	75	0	0
T10	3950	66	0	0
T11	10549	143	0	0
T12	49078	456	0	0
T13	28051	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214542	0	0
T1	7618	7	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	9	0	0
T8	88481	215	0	0
T9	322301	16	0	0
T10	3950	8	0	0
T11	10549	24	0	0
T12	49078	61	0	0
T13	28051	531	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214542	0	0
T1	7618	7	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	9	0	0
T8	88481	215	0	0
T9	322301	16	0	0
T10	3950	8	0	0
T11	10549	24	0	0
T12	49078	61	0	0
T13	28051	531	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	578594	0	0
T1	7618	7	0	0
T2	1692	8	0	0
T3	7654	148	0	0
T7	403482	9	0	0
T8	88481	325	0	0
T9	322301	26	0	0
T10	3950	8	0	0
T11	10549	26	0	0
T12	49078	61	0	0
T13	28051	1061	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	214542	0	0
T1	7618	7	0	0
T2	1692	7	0	0
T3	7654	139	0	0
T7	403482	9	0	0
T8	88481	215	0	0
T9	322301	16	0	0
T10	3950	8	0	0
T11	10549	24	0	0
T12	49078	61	0	0
T13	28051	531	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	219616	0	0
GntImpliesValid_A	405209337	219616	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	219616	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3160607	0	0
ReadyAndValidImplyGrant_A	405209337	219616	0	0
ReqAndReadyImplyGrant_A	405209337	219616	0	0
ReqImpliesValid_A	405209337	597773	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	219616	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219616	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	209	0	0
T9	322301	11	0	0
T10	3950	11	0	0
T11	10549	38	0	0
T12	49078	78	0	0
T13	28051	1503	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219616	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	209	0	0
T9	322301	11	0	0
T10	3950	11	0	0
T11	10549	38	0	0
T12	49078	78	0	0
T13	28051	1503	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219616	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	209	0	0
T9	322301	11	0	0
T10	3950	11	0	0
T11	10549	38	0	0
T12	49078	78	0	0
T13	28051	1503	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3160607	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	122	0	0
T7	403482	2272	0	0
T8	88481	1678	0	0
T9	322301	39	0	0
T10	3950	82	0	0
T11	10549	285	0	0
T12	49078	634	0	0
T13	28051	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219616	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	209	0	0
T9	322301	11	0	0
T10	3950	11	0	0
T11	10549	38	0	0
T12	49078	78	0	0
T13	28051	1503	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219616	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	209	0	0
T9	322301	11	0	0
T10	3950	11	0	0
T11	10549	38	0	0
T12	49078	78	0	0
T13	28051	1503	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	597773	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	143	0	0
T7	403482	5	0	0
T8	88481	299	0	0
T9	322301	11	0	0
T10	3950	15	0	0
T11	10549	65	0	0
T12	49078	78	0	0
T13	28051	2955	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219616	0	0
T1	7618	5	0	0
T2	1692	6	0	0
T3	7654	132	0	0
T7	403482	5	0	0
T8	88481	209	0	0
T9	322301	11	0	0
T10	3950	11	0	0
T11	10549	38	0	0
T12	49078	78	0	0
T13	28051	1503	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	210076	0	0
GntImpliesValid_A	405209337	210076	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	210076	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3092019	0	0
ReadyAndValidImplyGrant_A	405209337	210076	0	0
ReqAndReadyImplyGrant_A	405209337	210076	0	0
ReqImpliesValid_A	405209337	593437	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	210076	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210076	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	10	0	0
T8	88481	227	0	0
T9	322301	20	0	0
T10	3950	10	0	0
T11	10549	30	0	0
T12	49078	71	0	0
T13	28051	530	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210076	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	10	0	0
T8	88481	227	0	0
T9	322301	20	0	0
T10	3950	10	0	0
T11	10549	30	0	0
T12	49078	71	0	0
T13	28051	530	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210076	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	10	0	0
T8	88481	227	0	0
T9	322301	20	0	0
T10	3950	10	0	0
T11	10549	30	0	0
T12	49078	71	0	0
T13	28051	530	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3092019	0	0
T1	7618	36	0	0
T2	1692	13	0	0
T3	7654	149	0	0
T7	403482	3513	0	0
T8	88481	1619	0	0
T9	322301	83	0	0
T10	3950	62	0	0
T11	10549	220	0	0
T12	49078	577	0	0
T13	28051	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210076	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	10	0	0
T8	88481	227	0	0
T9	322301	20	0	0
T10	3950	10	0	0
T11	10549	30	0	0
T12	49078	71	0	0
T13	28051	530	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210076	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	10	0	0
T8	88481	227	0	0
T9	322301	20	0	0
T10	3950	10	0	0
T11	10549	30	0	0
T12	49078	71	0	0
T13	28051	530	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	593437	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	156	0	0
T7	403482	10	0	0
T8	88481	311	0	0
T9	322301	26	0	0
T10	3950	10	0	0
T11	10549	40	0	0
T12	49078	82	0	0
T13	28051	1059	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210076	0	0
T1	7618	4	0	0
T2	1692	13	0	0
T3	7654	152	0	0
T7	403482	10	0	0
T8	88481	227	0	0
T9	322301	20	0	0
T10	3950	10	0	0
T11	10549	30	0	0
T12	49078	71	0	0
T13	28051	530	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	219689	0	0
GntImpliesValid_A	405209337	219689	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	219689	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3077221	0	0
ReadyAndValidImplyGrant_A	405209337	219689	0	0
ReqAndReadyImplyGrant_A	405209337	219689	0	0
ReqImpliesValid_A	405209337	632821	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	219689	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219689	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	238	0	0
T9	322301	18	0	0
T10	3950	5	0	0
T11	10549	31	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219689	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	238	0	0
T9	322301	18	0	0
T10	3950	5	0	0
T11	10549	31	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219689	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	238	0	0
T9	322301	18	0	0
T10	3950	5	0	0
T11	10549	31	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3077221	0	0
T1	7618	45	0	0
T2	1692	15	0	0
T3	7654	152	0	0
T7	403482	3918	0	0
T8	88481	1834	0	0
T9	322301	76	0	0
T10	3950	35	0	0
T11	10549	221	0	0
T12	49078	668	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219689	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	238	0	0
T9	322301	18	0	0
T10	3950	5	0	0
T11	10549	31	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219689	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	238	0	0
T9	322301	18	0	0
T10	3950	5	0	0
T11	10549	31	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	632821	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	163	0	0
T7	403482	12	0	0
T8	88481	275	0	0
T9	322301	25	0	0
T10	3950	5	0	0
T11	10549	36	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	219689	0	0
T1	7618	4	0	0
T2	1692	14	0	0
T3	7654	157	0	0
T7	403482	12	0	0
T8	88481	238	0	0
T9	322301	18	0	0
T10	3950	5	0	0
T11	10549	31	0	0
T12	49078	81	0	0
T13	28051	0	0	0
T14	0	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	210820	0	0
GntImpliesValid_A	405209337	210820	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	210820	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3110281	0	0
ReadyAndValidImplyGrant_A	405209337	210820	0	0
ReqAndReadyImplyGrant_A	405209337	210820	0	0
ReqImpliesValid_A	405209337	610627	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	210820	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210820	0	0
T1	7618	11	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	8	0	0
T8	88481	257	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	28	0	0
T12	49078	66	0	0
T13	28051	446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210820	0	0
T1	7618	11	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	8	0	0
T8	88481	257	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	28	0	0
T12	49078	66	0	0
T13	28051	446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210820	0	0
T1	7618	11	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	8	0	0
T8	88481	257	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	28	0	0
T12	49078	66	0	0
T13	28051	446	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3110281	0	0
T1	7618	104	0	0
T2	1692	8	0	0
T3	7654	147	0	0
T7	403482	2247	0	0
T8	88481	1928	0	0
T9	322301	44	0	0
T10	3950	138	0	0
T11	10549	191	0	0
T12	49078	518	0	0
T13	28051	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210820	0	0
T1	7618	11	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	8	0	0
T8	88481	257	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	28	0	0
T12	49078	66	0	0
T13	28051	446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210820	0	0
T1	7618	11	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	8	0	0
T8	88481	257	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	28	0	0
T12	49078	66	0	0
T13	28051	446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	610627	0	0
T1	7618	12	0	0
T2	1692	7	0	0
T3	7654	170	0	0
T7	403482	404	0	0
T8	88481	333	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	43	0	0
T12	49078	66	0	0
T13	28051	877	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	210820	0	0
T1	7618	11	0	0
T2	1692	7	0	0
T3	7654	158	0	0
T7	403482	8	0	0
T8	88481	257	0	0
T9	322301	12	0	0
T10	3950	14	0	0
T11	10549	28	0	0
T12	49078	66	0	0
T13	28051	446	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	224443	0	0
GntImpliesValid_A	405209337	224443	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	224443	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3151683	0	0
ReadyAndValidImplyGrant_A	405209337	224443	0	0
ReqAndReadyImplyGrant_A	405209337	224443	0	0
ReqImpliesValid_A	405209337	615092	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	224443	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	224443	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	8	0	0
T8	88481	192	0	0
T9	322301	19	0	0
T10	3950	11	0	0
T11	10549	30	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	224443	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	8	0	0
T8	88481	192	0	0
T9	322301	19	0	0
T10	3950	11	0	0
T11	10549	30	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	224443	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	8	0	0
T8	88481	192	0	0
T9	322301	19	0	0
T10	3950	11	0	0
T11	10549	30	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3151683	0	0
T1	7618	51	0	0
T2	1692	11	0	0
T3	7654	118	0	0
T7	403482	3698	0	0
T8	88481	1387	0	0
T9	322301	89	0	0
T10	3950	60	0	0
T11	10549	228	0	0
T12	49078	618	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	224443	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	8	0	0
T8	88481	192	0	0
T9	322301	19	0	0
T10	3950	11	0	0
T11	10549	30	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	224443	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	8	0	0
T8	88481	192	0	0
T9	322301	19	0	0
T10	3950	11	0	0
T11	10549	30	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	615092	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	121	0	0
T7	403482	8	0	0
T8	88481	274	0	0
T9	322301	21	0	0
T10	3950	11	0	0
T11	10549	45	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	110	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	224443	0	0
T1	7618	8	0	0
T2	1692	10	0	0
T3	7654	119	0	0
T7	403482	8	0	0
T8	88481	192	0	0
T9	322301	19	0	0
T10	3950	11	0	0
T11	10549	30	0	0
T12	49078	76	0	0
T13	28051	0	0	0
T14	0	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	217143	0	0
GntImpliesValid_A	405209337	217143	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	217143	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	3162865	0	0
ReadyAndValidImplyGrant_A	405209337	217143	0	0
ReqAndReadyImplyGrant_A	405209337	217143	0	0
ReqImpliesValid_A	405209337	640614	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	0	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	217143	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	217143	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	5	0	0
T8	88481	220	0	0
T9	322301	13	0	0
T10	3950	4	0	0
T11	10549	45	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	92	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	217143	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	5	0	0
T8	88481	220	0	0
T9	322301	13	0	0
T10	3950	4	0	0
T11	10549	45	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	92	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	217143	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	5	0	0
T8	88481	220	0	0
T9	322301	13	0	0
T10	3950	4	0	0
T11	10549	45	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	92	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	3162865	0	0
T1	7618	72	0	0
T2	1692	7	0	0
T3	7654	134	0	0
T7	403482	1968	0	0
T8	88481	1613	0	0
T9	322301	70	0	0
T10	3950	20	0	0
T11	10549	314	0	0
T12	49078	755	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	217143	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	5	0	0
T8	88481	220	0	0
T9	322301	13	0	0
T10	3950	4	0	0
T11	10549	45	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	92	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	217143	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	5	0	0
T8	88481	220	0	0
T9	322301	13	0	0
T10	3950	4	0	0
T11	10549	45	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	92	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	640614	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	159	0	0
T7	403482	5	0	0
T8	88481	354	0	0
T9	322301	16	0	0
T10	3950	4	0	0
T11	10549	57	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	217143	0	0
T1	7618	6	0	0
T2	1692	6	0	0
T3	7654	146	0	0
T7	403482	5	0	0
T8	88481	220	0	0
T9	322301	13	0	0
T10	3950	4	0	0
T11	10549	45	0	0
T12	49078	97	0	0
T13	28051	0	0	0
T14	0	92	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	846755	0	0
GntImpliesValid_A	405209337	846755	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	846755	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	11908548	0	0
ReadyAndValidImplyGrant_A	405209337	846755	0	0
ReqAndReadyImplyGrant_A	405209337	846755	0	0
ReqImpliesValid_A	405209337	2362637	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	13816	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	846755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846755	0	0
T1	7618	53	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	43	0	0
T8	88481	892	0	0
T9	322301	41	0	0
T10	3950	21	0	0
T11	10549	135	0	0
T12	49078	302	0	0
T13	28051	948	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846755	0	0
T1	7618	53	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	43	0	0
T8	88481	892	0	0
T9	322301	41	0	0
T10	3950	21	0	0
T11	10549	135	0	0
T12	49078	302	0	0
T13	28051	948	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846755	0	0
T1	7618	53	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	43	0	0
T8	88481	892	0	0
T9	322301	41	0	0
T10	3950	21	0	0
T11	10549	135	0	0
T12	49078	302	0	0
T13	28051	948	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	11908548	0	0
T1	7618	337	0	0
T2	1692	1	0	0
T3	7654	1	0	0
T7	403482	17892	0	0
T8	88481	5923	0	0
T9	322301	109	0	0
T10	3950	162	0	0
T11	10549	836	0	0
T12	49078	1942	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846755	0	0
T1	7618	53	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	43	0	0
T8	88481	892	0	0
T9	322301	41	0	0
T10	3950	21	0	0
T11	10549	135	0	0
T12	49078	302	0	0
T13	28051	948	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846755	0	0
T1	7618	53	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	43	0	0
T8	88481	892	0	0
T9	322301	41	0	0
T10	3950	21	0	0
T11	10549	135	0	0
T12	49078	302	0	0
T13	28051	948	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	2362637	0	0
T1	7618	71	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	2503	0	0
T8	88481	1471	0	0
T9	322301	56	0	0
T10	3950	25	0	0
T11	10549	226	0	0
T12	49078	318	0	0
T13	28051	948	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	13816	0	900
T3	7654	7	0	1
T7	403482	0	0	1
T8	88481	0	0	1
T9	322301	0	0	1
T10	3950	0	0	1
T11	10549	0	0	1
T12	49078	0	0	1
T13	28051	0	0	1
T14	39063	0	0	1
T15	0	25	0	0
T16	0	14	0	0
T17	0	12	0	0
T20	0	8	0	0
T21	0	4	0	0
T22	0	1	0	0
T23	0	14	0	0
T24	0	9	0	0
T25	0	1	0	0
T26	477460	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	846755	0	0
T1	7618	53	0	0
T2	1692	36	0	0
T3	7654	536	0	0
T7	403482	43	0	0
T8	88481	892	0	0
T9	322301	41	0	0
T10	3950	21	0	0
T11	10549	135	0	0
T12	49078	302	0	0
T13	28051	948	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405209337	405079281	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405209337	854561	0	0
GntImpliesValid_A	405209337	854561	0	0
GrantKnown_A	405209337	405079281	0	0
IdxKnown_A	405209337	405079281	0	0
IndexIsCorrect_A	405209337	854561	0	0
LockArbDecision_A	405209337	0	0	0
NoReadyValidNoGrant_A	405209337	340534138	0	0
ReadyAndValidImplyGrant_A	405209337	854561	0	0
ReqAndReadyImplyGrant_A	405209337	854561	0	0
ReqImpliesValid_A	405209337	13795736	0	0
ReqStaysHighUntilGranted0_M	405209337	0	0	0
RoundRobin_A	405209337	17786	0	900
ValidKnown_A	405209337	405079281	0	0
gen_data_port_assertion.DataFlow_A	405209337	854561	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	854561	0	0
T1	7618	47	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	38	0	0
T8	88481	874	0	0
T9	322301	40	0	0
T10	3950	41	0	0
T11	10549	124	0	0
T12	49078	310	0	0
T13	28051	946	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	854561	0	0
T1	7618	47	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	38	0	0
T8	88481	874	0	0
T9	322301	40	0	0
T10	3950	41	0	0
T11	10549	124	0	0
T12	49078	310	0	0
T13	28051	946	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	854561	0	0
T1	7618	47	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	38	0	0
T8	88481	874	0	0
T9	322301	40	0	0
T10	3950	41	0	0
T11	10549	124	0	0
T12	49078	310	0	0
T13	28051	946	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	340534138	0	0
T1	7618	6548	0	0
T2	1692	1	0	0
T3	7654	1	0	0
T7	403482	386505	0	0
T8	88481	71990	0	0
T9	322301	268275	0	0
T10	3950	3245	0	0
T11	10549	8649	0	0
T12	49078	42544	0	0
T13	28051	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	854561	0	0
T1	7618	47	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	38	0	0
T8	88481	874	0	0
T9	322301	40	0	0
T10	3950	41	0	0
T11	10549	124	0	0
T12	49078	310	0	0
T13	28051	946	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	854561	0	0
T1	7618	47	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	38	0	0
T8	88481	874	0	0
T9	322301	40	0	0
T10	3950	41	0	0
T11	10549	124	0	0
T12	49078	310	0	0
T13	28051	946	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	13795736	0	0
T1	7618	411	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	11906	0	0
T8	88481	6785	0	0
T9	322301	150	0	0
T10	3950	356	0	0
T11	10549	1026	0	0
T12	49078	2398	0	0
T13	28051	946	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	17786	0	900
T3	7654	9	0	1
T7	403482	0	0	1
T8	88481	1	0	1
T9	322301	0	0	1
T10	3950	0	0	1
T11	10549	0	0	1
T12	49078	1	0	1
T13	28051	0	0	1
T14	39063	0	0	1
T15	0	17	0	0
T16	0	11	0	0
T17	0	10	0	0
T18	0	1	0	0
T19	0	14	0	0
T20	0	16	0	0
T21	0	1	0	0
T26	477460	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	405079281	0	0
T1	7618	7608	0	0
T2	1692	1672	0	0
T3	7654	7647	0	0
T7	403482	403426	0	0
T8	88481	88463	0	0
T9	322301	322269	0	0
T10	3950	3938	0	0
T11	10549	10527	0	0
T12	49078	49030	0	0
T13	28051	28024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405209337	854561	0	0
T1	7618	47	0	0
T2	1692	59	0	0
T3	7654	616	0	0
T7	403482	38	0	0
T8	88481	874	0	0
T9	322301	40	0	0
T10	3950	41	0	0
T11	10549	124	0	0
T12	49078	310	0	0
T13	28051	946	0	0