Unified Coverage Report :: Module :: tlul_socket_m1

Module : tlul_socket_m1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28	95.96	100.00	87.88				100.00
tb.dut.u_sm1_29	95.96	100.00	87.88				100.00
tb.dut.u_sm1_31	95.96	100.00	87.88				100.00
tb.dut.u_sm1_33	96.97	100.00	90.91				100.00
tb.dut.u_sm1_34	96.97	100.00	90.91				100.00
tb.dut.u_sm1_36	96.97	100.00	90.91				100.00
tb.dut.u_sm1_38	96.97	100.00	90.91				100.00
tb.dut.u_sm1_40	96.97	100.00	90.91				100.00
tb.dut.u_sm1_42	96.97	100.00	90.91				100.00
tb.dut.u_sm1_43	96.97	100.00	90.91				100.00
tb.dut.u_sm1_44	96.97	100.00	90.91				100.00
tb.dut.u_sm1_45	96.97	100.00	90.91				100.00
tb.dut.u_sm1_46	96.97	100.00	90.91				100.00
tb.dut.u_sm1_47	96.97	100.00	90.91				100.00
tb.dut.u_sm1_48	96.97	100.00	90.91				100.00
tb.dut.u_sm1_49	96.97	100.00	90.91				100.00
tb.dut.u_sm1_50	96.97	100.00	90.91				100.00
tb.dut.u_sm1_51	96.97	100.00	90.91				100.00
tb.dut.u_sm1_52	96.97	100.00	90.91				100.00
tb.dut.u_sm1_53	96.97	100.00	90.91				100.00
tb.dut.u_sm1_54	96.97	100.00	90.91				100.00
tb.dut.u_sm1_55	96.97	100.00	90.91				100.00
tb.dut.u_sm1_56	96.97	100.00	90.91				100.00
tb.dut.u_sm1_30	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sm1_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.51	98.68	85.92			92.73	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	92.21	97.50	82.14			89.19	100.00

---

Module Instance : tb.dut.u_sm1_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78	100.00	98.39			100.00	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_28

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_29

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_33

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_34

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_36

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_38

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_40

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_42

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_43

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_44

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_45

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_46

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_47

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_48

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_49

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_50

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_51

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_52

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_53

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_54

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_55

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
95.96	87.88

tb.dut.u_sm1_28

SCORE	COND
95.96	87.88

tb.dut.u_sm1_29

SCORE	COND
95.96	87.88

tb.dut.u_sm1_31

SCORE	COND
100.00	100.00

tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T11,T13,T25
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T11,T13,T25
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.97	90.91

tb.dut.u_sm1_33

SCORE	COND
96.97	90.91

tb.dut.u_sm1_34

SCORE	COND
96.97	90.91

tb.dut.u_sm1_43

SCORE	COND
96.97	90.91

tb.dut.u_sm1_44

SCORE	COND
96.97	90.91

tb.dut.u_sm1_45

SCORE	COND
96.97	90.91

tb.dut.u_sm1_46

SCORE	COND
96.97	90.91

tb.dut.u_sm1_47

SCORE	COND
96.97	90.91

tb.dut.u_sm1_48

SCORE	COND
96.97	90.91

tb.dut.u_sm1_49

SCORE	COND
96.97	90.91

tb.dut.u_sm1_50

SCORE	COND
96.97	90.91

tb.dut.u_sm1_51

SCORE	COND
96.97	90.91

tb.dut.u_sm1_52

SCORE	COND
96.97	90.91

tb.dut.u_sm1_53

SCORE	COND
96.97	90.91

tb.dut.u_sm1_54

SCORE	COND
96.97	90.91

tb.dut.u_sm1_55

SCORE	COND
96.97	90.91

tb.dut.u_sm1_56

SCORE	COND
96.97	90.91

tb.dut.u_sm1_36

SCORE	COND
96.97	90.91

tb.dut.u_sm1_38

SCORE	COND
96.97	90.91

tb.dut.u_sm1_40

SCORE	COND
96.97	90.91

tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_m1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	2147483647	21319413	0	0
gen_host_fifo[1].idInRange	2147483647	11980485	0	0
gen_host_fifo[2].idInRange	1688532160	3268845	0	0
maxM	21600	21600	0	0
rspIdInRange	2147483647	169866273	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21319413	0	0
T1	63552	262	0	0
T2	310608	652	0	0
T3	8542992	513	0	0
T7	1996080	12992	0	0
T8	316536	6329	0	0
T9	24840	1225	0	0
T10	323400	2092	0	0
T11	10374744	15637	0	0
T12	8702808	30565	0	0
T13	153408	1802	0	0
T14	0	2062	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11980485	0	0
T1	63552	206	0	0
T2	310608	241	0	0
T3	8542992	200	0	0
T7	1996080	5363	0	0
T8	316536	3174	0	0
T9	24840	687	0	0
T10	323400	818	0	0
T11	10374744	3809	0	0
T12	8702808	13322	0	0
T13	153408	939	0	0
T14	0	2429	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688532160	3268845	0	0
T1	10592	29	0	0
T2	51768	38	0	0
T3	1423832	60	0	0
T7	332680	1864	0	0
T8	52756	558	0	0
T9	4140	0	0	0
T10	53900	320	0	0
T11	1729124	1951	0	0
T12	1450468	3580	0	0
T13	25568	159	0	0
T14	0	418	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	169866273	0	0
T1	63552	416	0	0
T2	310608	2549	0	0
T3	8542992	107007	0	0
T7	1996080	48273	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	4649	0	0
T11	10374744	107424	0	0
T12	8702808	159629	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

Line Coverage for Instance : tb.dut.u_sm1_28

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	1548046	0	0
gen_host_fifo[1].idInRange	422133040	368567	0	0
gen_host_fifo[2].idInRange	422133040	454961	0	0
maxM	900	900	0	0
rspIdInRange	422133040	20807307	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1548046	0	0
T1	2648	29	0	0
T2	12942	37	0	0
T3	355958	49	0	0
T7	83170	1279	0	0
T8	13189	778	0	0
T9	1035	68	0	0
T10	13475	195	0	0
T11	432281	883	0	0
T12	362617	1029	0	0
T13	6392	210	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	368567	0	0
T1	2648	6	0	0
T2	12942	9	0	0
T3	355958	5	0	0
T7	83170	207	0	0
T8	13189	135	0	0
T9	1035	0	0	0
T10	13475	10	0	0
T11	432281	795	0	0
T12	362617	796	0	0
T13	6392	22	0	0
T14	0	103	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	454961	0	0
T1	2648	10	0	0
T2	12942	5	0	0
T3	355958	15	0	0
T7	83170	196	0	0
T8	13189	117	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	3	0	0
T12	362617	452	0	0
T13	6392	40	0	0
T14	0	122	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	20807307	0	0
T1	2648	45	0	0
T2	12942	399	0	0
T3	355958	19086	0	0
T7	83170	6790	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	378	0	0
T11	432281	13628	0	0
T12	362617	10881	0	0
T13	6392	272	0	0

Line Coverage for Instance : tb.dut.u_sm1_29

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_29

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	1718069	0	0
gen_host_fifo[1].idInRange	422133040	434915	0	0
gen_host_fifo[2].idInRange	422133040	547335	0	0
maxM	900	900	0	0
rspIdInRange	422133040	20677205	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1718069	0	0
T1	2648	32	0	0
T2	12942	55	0	0
T3	355958	53	0	0
T7	83170	1340	0	0
T8	13189	981	0	0
T9	1035	107	0	0
T10	13475	204	0	0
T11	432281	1151	0	0
T12	362617	3373	0	0
T13	6392	280	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	434915	0	0
T1	2648	4	0	0
T2	12942	4	0	0
T3	355958	10	0	0
T7	83170	198	0	0
T8	13189	181	0	0
T9	1035	0	0	0
T10	13475	52	0	0
T11	432281	5	0	0
T12	362617	268	0	0
T13	6392	34	0	0
T14	0	106	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	547335	0	0
T1	2648	7	0	0
T2	12942	8	0	0
T3	355958	13	0	0
T7	83170	309	0	0
T8	13189	135	0	0
T9	1035	0	0	0
T10	13475	57	0	0
T11	432281	6	0	0
T12	362617	7	0	0
T13	6392	32	0	0
T14	0	107	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	20677205	0	0
T1	2648	36	0	0
T2	12942	298	0	0
T3	355958	16484	0	0
T7	83170	6877	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	502	0	0
T11	432281	18293	0	0
T12	362617	9639	0	0
T13	6392	296	0	0

Line Coverage for Instance : tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_31

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	1746722	0	0
gen_host_fifo[1].idInRange	422133040	425073	0	0
gen_host_fifo[2].idInRange	422133040	536394	0	0
maxM	900	900	0	0
rspIdInRange	422133040	19269122	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1746722	0	0
T1	2648	22	0	0
T2	12942	66	0	0
T3	355958	45	0	0
T7	83170	1365	0	0
T8	13189	1011	0	0
T9	1035	98	0	0
T10	13475	189	0	0
T11	432281	1864	0	0
T12	362617	999	0	0
T13	6392	242	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	425073	0	0
T1	2648	4	0	0
T2	12942	2	0	0
T3	355958	11	0	0
T7	83170	243	0	0
T8	13189	141	0	0
T9	1035	0	0	0
T10	13475	26	0	0
T11	432281	6	0	0
T12	362617	13	0	0
T13	6392	26	0	0
T14	0	135	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	536394	0	0
T1	2648	8	0	0
T2	12942	3	0	0
T3	355958	1	0	0
T7	83170	311	0	0
T8	13189	164	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	783	0	0
T12	362617	215	0	0
T13	6392	37	0	0
T14	0	86	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	19269122	0	0
T1	2648	33	0	0
T2	12942	270	0	0
T3	355958	14839	0	0
T7	83170	6530	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	510	0	0
T11	432281	12556	0	0
T12	362617	11333	0	0
T13	6392	272	0	0

Line Coverage for Instance : tb.dut.u_sm1_33

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_33

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	303525	0	0
gen_host_fifo[1].idInRange	422133040	402151	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4394997	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	303525	0	0
T1	2648	3	0	0
T2	12942	21	0	0
T3	355958	6	0	0
T7	83170	120	0	0
T8	13189	142	0	0
T9	1035	0	0	0
T10	13475	15	0	0
T11	432281	9	0	0
T12	362617	18	0	0
T13	6392	35	0	0
T14	0	113	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	402151	0	0
T1	2648	11	0	0
T2	12942	20	0	0
T3	355958	6	0	0
T7	83170	180	0	0
T8	13189	126	0	0
T9	1035	0	0	0
T10	13475	26	0	0
T11	432281	1	0	0
T12	362617	230	0	0
T13	6392	47	0	0
T14	0	123	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4394997	0	0
T1	2648	14	0	0
T2	12942	75	0	0
T3	355958	1854	0	0
T7	83170	1040	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	134	0	0
T11	432281	4063	0	0
T12	362617	5529	0	0
T13	6392	80	0	0
T14	0	232	0	0

Line Coverage for Instance : tb.dut.u_sm1_34

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_34

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	284911	0	0
gen_host_fifo[1].idInRange	422133040	358544	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4363546	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	284911	0	0
T1	2648	3	0	0
T2	12942	15	0	0
T3	355958	4	0	0
T7	83170	147	0	0
T8	13189	141	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	4	0	0
T12	362617	18	0	0
T13	6392	39	0	0
T14	0	96	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	358544	0	0
T1	2648	8	0	0
T2	12942	4	0	0
T3	355958	7	0	0
T7	83170	139	0	0
T8	13189	142	0	0
T9	1035	0	0	0
T10	13475	20	0	0
T11	432281	512	0	0
T12	362617	565	0	0
T13	6392	35	0	0
T14	0	104	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4363546	0	0
T1	2648	10	0	0
T2	12942	119	0	0
T3	355958	1024	0	0
T7	83170	1068	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	179	0	0
T11	432281	924	0	0
T12	362617	6397	0	0
T13	6392	72	0	0
T14	0	195	0	0

Line Coverage for Instance : tb.dut.u_sm1_36

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_36

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	750501	0	0
gen_host_fifo[1].idInRange	422133040	838067	0	0
maxM	900	900	0	0
rspIdInRange	422133040	5245071	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	750501	0	0
T1	2648	48	0	0
T2	12942	7	0	0
T3	355958	6	0	0
T7	83170	161	0	0
T8	13189	186	0	0
T9	1035	0	0	0
T10	13475	59	0	0
T11	432281	6	0	0
T12	362617	70	0	0
T13	6392	48	0	0
T14	0	100	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	838067	0	0
T1	2648	5	0	0
T2	12942	9	0	0
T3	355958	4	0	0
T7	83170	167	0	0
T8	13189	151	0	0
T9	1035	0	0	0
T10	13475	20	0	0
T11	432281	2	0	0
T12	362617	26	0	0
T13	6392	52	0	0
T14	0	97	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	5245071	0	0
T1	2648	12	0	0
T2	12942	69	0	0
T3	355958	2176	0	0
T7	83170	1072	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	132	0	0
T11	432281	2062	0	0
T12	362617	9120	0	0
T13	6392	73	0	0
T14	0	189	0	0

Line Coverage for Instance : tb.dut.u_sm1_38

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_38

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	534758	0	0
gen_host_fifo[1].idInRange	422133040	642834	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4167428	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	534758	0	0
T1	2648	14	0	0
T2	12942	25	0	0
T3	355958	12	0	0
T7	83170	162	0	0
T8	13189	144	0	0
T9	1035	0	0	0
T10	13475	44	0	0
T11	432281	7	0	0
T12	362617	16	0	0
T13	6392	45	0	0
T14	0	114	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	642834	0	0
T1	2648	13	0	0
T2	12942	3	0	0
T3	355958	18	0	0
T7	83170	236	0	0
T8	13189	181	0	0
T9	1035	0	0	0
T10	13475	29	0	0
T11	432281	2	0	0
T12	362617	6	0	0
T13	6392	56	0	0
T14	0	122	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4167428	0	0
T1	2648	14	0	0
T2	12942	64	0	0
T3	355958	1145	0	0
T7	83170	1065	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	88	0	0
T11	432281	1793	0	0
T12	362617	7416	0	0
T13	6392	72	0	0
T14	0	226	0	0

Line Coverage for Instance : tb.dut.u_sm1_40

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_40

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T8,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T10,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	641630	0	0
gen_host_fifo[1].idInRange	422133040	768020	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4878550	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	641630	0	0
T1	2648	6	0	0
T2	12942	2	0	0
T3	355958	4	0	0
T7	83170	125	0	0
T8	13189	192	0	0
T9	1035	0	0	0
T10	13475	44	0	0
T11	432281	4	0	0
T12	362617	15	0	0
T13	6392	40	0	0
T14	0	117	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	768020	0	0
T1	2648	6	0	0
T2	12942	4	0	0
T3	355958	3	0	0
T7	83170	212	0	0
T8	13189	182	0	0
T9	1035	0	0	0
T10	13475	43	0	0
T11	432281	5	0	0
T12	362617	11	0	0
T13	6392	61	0	0
T14	0	110	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4878550	0	0
T1	2648	12	0	0
T2	12942	35	0	0
T3	355958	1439	0	0
T7	83170	1132	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	125	0	0
T11	432281	1375	0	0
T12	362617	7471	0	0
T13	6392	64	0	0
T14	0	216	0	0

Line Coverage for Instance : tb.dut.u_sm1_42

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T12,T26
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	652669	0	0
gen_host_fifo[1].idInRange	422133040	773218	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4334288	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	652669	0	0
T1	2648	4	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	324	0	0
T8	13189	156	0	0
T9	1035	0	0	0
T10	13475	27	0	0
T11	432281	9	0	0
T12	362617	8	0	0
T13	6392	54	0	0
T14	0	123	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	773218	0	0
T1	2648	21	0	0
T2	12942	19	0	0
T3	355958	3	0	0
T7	83170	276	0	0
T8	13189	128	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	907	0	0
T12	362617	13	0	0
T13	6392	58	0	0
T14	0	127	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4334288	0	0
T1	2648	13	0	0
T2	12942	40	0	0
T3	355958	1759	0	0
T7	83170	1085	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	137	0	0
T11	432281	3054	0	0
T12	362617	3608	0	0
T13	6392	79	0	0
T14	0	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_43

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_43

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	285333	0	0
gen_host_fifo[1].idInRange	422133040	374145	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4694496	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	285333	0	0
T1	2648	4	0	0
T2	12942	7	0	0
T3	355958	3	0	0
T7	83170	133	0	0
T8	13189	145	0	0
T9	1035	884	0	0
T10	13475	17	0	0
T11	432281	11	0	0
T12	362617	13	0	0
T13	6392	35	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	374145	0	0
T1	2648	8	0	0
T2	12942	3	0	0
T3	355958	10	0	0
T7	83170	193	0	0
T8	13189	133	0	0
T9	1035	687	0	0
T10	13475	18	0	0
T11	432281	2	0	0
T12	362617	17	0	0
T13	6392	29	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4694496	0	0
T1	2648	12	0	0
T2	12942	57	0	0
T3	355958	999	0	0
T7	83170	959	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	90	0	0
T11	432281	2626	0	0
T12	362617	5420	0	0
T13	6392	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_44

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_44

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	277687	0	0
gen_host_fifo[1].idInRange	422133040	351840	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4150625	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	277687	0	0
T1	2648	4	0	0
T2	12942	8	0	0
T3	355958	7	0	0
T7	83170	124	0	0
T8	13189	136	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	13	0	0
T13	6392	43	0	0
T14	0	116	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	351840	0	0
T1	2648	12	0	0
T2	12942	11	0	0
T3	355958	12	0	0
T7	83170	206	0	0
T8	13189	112	0	0
T9	1035	0	0	0
T10	13475	27	0	0
T11	432281	5	0	0
T12	362617	328	0	0
T13	6392	41	0	0
T14	0	110	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4150625	0	0
T1	2648	16	0	0
T2	12942	40	0	0
T3	355958	3417	0	0
T7	83170	889	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	156	0	0
T11	432281	3969	0	0
T12	362617	5277	0	0
T13	6392	79	0	0
T14	0	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_45

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_45

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	255933	0	0
gen_host_fifo[1].idInRange	422133040	339559	0	0
maxM	900	900	0	0
rspIdInRange	422133040	3328313	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	255933	0	0
T1	2648	8	0	0
T2	12942	6	0	0
T3	355958	11	0	0
T7	83170	171	0	0
T8	13189	142	0	0
T9	1035	0	0	0
T10	13475	18	0	0
T11	432281	10	0	0
T12	362617	12	0	0
T13	6392	32	0	0
T14	0	103	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	339559	0	0
T1	2648	9	0	0
T2	12942	8	0	0
T3	355958	4	0	0
T7	83170	243	0	0
T8	13189	105	0	0
T9	1035	0	0	0
T10	13475	25	0	0
T11	432281	5	0	0
T12	362617	1052	0	0
T13	6392	41	0	0
T14	0	96	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	3328313	0	0
T1	2648	15	0	0
T2	12942	58	0	0
T3	355958	1409	0	0
T7	83170	1144	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	132	0	0
T11	432281	3256	0	0
T12	362617	5764	0	0
T13	6392	69	0	0
T14	0	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_46

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_46

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	304333	0	0
gen_host_fifo[1].idInRange	422133040	392801	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4012697	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	304333	0	0
T1	2648	5	0	0
T2	12942	7	0	0
T3	355958	4	0	0
T7	83170	169	0	0
T8	13189	120	0	0
T9	1035	0	0	0
T10	13475	22	0	0
T11	432281	4	0	0
T12	362617	60	0	0
T13	6392	55	0	0
T14	0	115	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	392801	0	0
T1	2648	6	0	0
T2	12942	7	0	0
T3	355958	15	0	0
T7	83170	193	0	0
T8	13189	106	0	0
T9	1035	0	0	0
T10	13475	22	0	0
T11	432281	7	0	0
T12	362617	1490	0	0
T13	6392	26	0	0
T14	0	99	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4012697	0	0
T1	2648	10	0	0
T2	12942	43	0	0
T3	355958	2023	0	0
T7	83170	1145	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	92	0	0
T11	432281	1032	0	0
T12	362617	6431	0	0
T13	6392	72	0	0
T14	0	210	0	0

Line Coverage for Instance : tb.dut.u_sm1_47

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_47

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	293613	0	0
gen_host_fifo[1].idInRange	422133040	388875	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4521778	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	293613	0	0
T1	2648	4	0	0
T2	12942	21	0	0
T3	355958	2	0	0
T7	83170	151	0	0
T8	13189	124	0	0
T9	1035	0	0	0
T10	13475	25	0	0
T11	432281	8	0	0
T12	362617	12	0	0
T13	6392	49	0	0
T14	0	103	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	388875	0	0
T1	2648	5	0	0
T2	12942	5	0	0
T3	355958	12	0	0
T7	83170	165	0	0
T8	13189	135	0	0
T9	1035	0	0	0
T10	13475	18	0	0
T11	432281	5	0	0
T12	362617	7	0	0
T13	6392	33	0	0
T14	0	98	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4521778	0	0
T1	2648	9	0	0
T2	12942	113	0	0
T3	355958	1116	0	0
T7	83170	1134	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	88	0	0
T11	432281	2128	0	0
T12	362617	4696	0	0
T13	6392	78	0	0
T14	0	198	0	0

Line Coverage for Instance : tb.dut.u_sm1_48

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_48

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	271838	0	0
gen_host_fifo[1].idInRange	422133040	358695	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4953434	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	271838	0	0
T1	2648	7	0	0
T2	12942	7	0	0
T3	355958	5	0	0
T7	83170	145	0	0
T8	13189	117	0	0
T9	1035	0	0	0
T10	13475	16	0	0
T11	432281	154	0	0
T12	362617	22	0	0
T13	6392	40	0	0
T14	0	118	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	358695	0	0
T1	2648	12	0	0
T2	12942	12	0	0
T3	355958	4	0	0
T7	83170	162	0	0
T8	13189	133	0	0
T9	1035	0	0	0
T10	13475	21	0	0
T11	432281	163	0	0
T12	362617	404	0	0
T13	6392	36	0	0
T14	0	92	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4953434	0	0
T1	2648	17	0	0
T2	12942	68	0	0
T3	355958	2383	0	0
T7	83170	1094	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	137	0	0
T11	432281	3447	0	0
T12	362617	5935	0	0
T13	6392	73	0	0
T14	0	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_49

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_49

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	274930	0	0
gen_host_fifo[1].idInRange	422133040	347353	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4410595	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	274930	0	0
T1	2648	5	0	0
T2	12942	4	0	0
T3	355958	6	0	0
T7	83170	155	0	0
T8	13189	116	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	406	0	0
T13	6392	28	0	0
T14	0	103	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	347353	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	2	0	0
T7	83170	253	0	0
T8	13189	127	0	0
T9	1035	0	0	0
T10	13475	23	0	0
T11	432281	2	0	0
T12	362617	470	0	0
T13	6392	33	0	0
T14	0	100	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4410595	0	0
T1	2648	16	0	0
T2	12942	43	0	0
T3	355958	2947	0	0
T7	83170	1120	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	199	0	0
T11	432281	3404	0	0
T12	362617	4308	0	0
T13	6392	60	0	0
T14	0	200	0	0

Line Coverage for Instance : tb.dut.u_sm1_50

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_50

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T8,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	327711	0	0
gen_host_fifo[1].idInRange	422133040	418371	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4378686	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	327711	0	0
T1	2648	9	0	0
T2	12942	4	0	0
T3	355958	6	0	0
T7	83170	118	0	0
T8	13189	110	0	0
T9	1035	0	0	0
T10	13475	52	0	0
T11	432281	9	0	0
T12	362617	17	0	0
T13	6392	53	0	0
T14	0	103	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	418371	0	0
T1	2648	9	0	0
T2	12942	6	0	0
T3	355958	4	0	0
T7	83170	184	0	0
T8	13189	116	0	0
T9	1035	0	0	0
T10	13475	30	0	0
T11	432281	7	0	0
T12	362617	153	0	0
T13	6392	39	0	0
T14	0	98	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4378686	0	0
T1	2648	17	0	0
T2	12942	62	0	0
T3	355958	1923	0	0
T7	83170	1006	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	198	0	0
T11	432281	3545	0	0
T12	362617	7047	0	0
T13	6392	85	0	0
T14	0	197	0	0

Line Coverage for Instance : tb.dut.u_sm1_51

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_51

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	298263	0	0
gen_host_fifo[1].idInRange	422133040	386245	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4485794	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	298263	0	0
T1	2648	5	0	0
T2	12942	7	0	0
T3	355958	7	0	0
T7	83170	182	0	0
T8	13189	146	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	8	0	0
T12	362617	9	0	0
T13	6392	56	0	0
T14	0	101	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	386245	0	0
T1	2648	9	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	187	0	0
T8	13189	119	0	0
T9	1035	0	0	0
T10	13475	53	0	0
T11	432281	234	0	0
T12	362617	14	0	0
T13	6392	58	0	0
T14	0	105	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4485794	0	0
T1	2648	14	0	0
T2	12942	64	0	0
T3	355958	1115	0	0
T7	83170	1109	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	152	0	0
T11	432281	1750	0	0
T12	362617	3197	0	0
T13	6392	107	0	0
T14	0	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_52

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_52

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	291593	0	0
gen_host_fifo[1].idInRange	422133040	385174	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4523013	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	291593	0	0
T1	2648	1	0	0
T2	12942	10	0	0
T3	355958	3	0	0
T7	83170	173	0	0
T8	13189	131	0	0
T9	1035	0	0	0
T10	13475	11	0	0
T11	432281	4	0	0
T12	362617	210	0	0
T13	6392	43	0	0
T14	0	101	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	385174	0	0
T1	2648	5	0	0
T2	12942	4	0	0
T3	355958	13	0	0
T7	83170	153	0	0
T8	13189	136	0	0
T9	1035	0	0	0
T10	13475	16	0	0
T11	432281	3	0	0
T12	362617	502	0	0
T13	6392	28	0	0
T14	0	94	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4523013	0	0
T1	2648	6	0	0
T2	12942	57	0	0
T3	355958	1489	0	0
T7	83170	1118	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	86	0	0
T11	432281	922	0	0
T12	362617	4382	0	0
T13	6392	69	0	0
T14	0	193	0	0

Line Coverage for Instance : tb.dut.u_sm1_53

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_53

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	278768	0	0
gen_host_fifo[1].idInRange	422133040	357789	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4800790	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	278768	0	0
T1	2648	4	0	0
T2	12942	3	0	0
T3	355958	12	0	0
T7	83170	188	0	0
T8	13189	114	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	496	0	0
T12	362617	495	0	0
T13	6392	40	0	0
T14	0	100	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	357789	0	0
T1	2648	4	0	0
T2	12942	7	0	0
T3	355958	12	0	0
T7	83170	211	0	0
T8	13189	133	0	0
T9	1035	0	0	0
T10	13475	55	0	0
T11	432281	48	0	0
T12	362617	793	0	0
T13	6392	27	0	0
T14	0	96	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4800790	0	0
T1	2648	8	0	0
T2	12942	50	0	0
T3	355958	3175	0	0
T7	83170	1148	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	131	0	0
T11	432281	2739	0	0
T12	362617	7331	0	0
T13	6392	64	0	0
T14	0	193	0	0

Line Coverage for Instance : tb.dut.u_sm1_54

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_54

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	280747	0	0
gen_host_fifo[1].idInRange	422133040	374079	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4280441	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	280747	0	0
T1	2648	2	0	0
T2	12942	11	0	0
T3	355958	3	0	0
T7	83170	146	0	0
T8	13189	162	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	170	0	0
T12	362617	16	0	0
T13	6392	31	0	0
T14	0	102	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	374079	0	0
T1	2648	9	0	0
T2	12942	5	0	0
T3	355958	5	0	0
T7	83170	189	0	0
T8	13189	101	0	0
T9	1035	0	0	0
T10	13475	23	0	0
T11	432281	448	0	0
T12	362617	8	0	0
T13	6392	33	0	0
T14	0	103	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4280441	0	0
T1	2648	11	0	0
T2	12942	57	0	0
T3	355958	1952	0	0
T7	83170	1062	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	135	0	0
T11	432281	3748	0	0
T12	362617	4810	0	0
T13	6392	64	0	0
T14	0	205	0	0

Line Coverage for Instance : tb.dut.u_sm1_55

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_55

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	300510	0	0
gen_host_fifo[1].idInRange	422133040	399508	0	0
maxM	900	900	0	0
rspIdInRange	422133040	4611987	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	300510	0	0
T1	2648	8	0	0
T2	12942	14	0	0
T3	355958	4	0	0
T7	83170	159	0	0
T8	13189	140	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	5	0	0
T12	362617	15	0	0
T13	6392	43	0	0
T14	0	104	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	399508	0	0
T1	2648	11	0	0
T2	12942	7	0	0
T3	355958	1	0	0
T7	83170	157	0	0
T8	13189	108	0	0
T9	1035	0	0	0
T10	13475	55	0	0
T11	432281	2	0	0
T12	362617	13	0	0
T13	6392	43	0	0
T14	0	91	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4611987	0	0
T1	2648	19	0	0
T2	12942	56	0	0
T3	355958	1102	0	0
T7	83170	1088	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	237	0	0
T11	432281	1604	0	0
T12	362617	5927	0	0
T13	6392	81	0	0
T14	0	192	0	0

Line Coverage for Instance : tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_56

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	322201	0	0
gen_host_fifo[1].idInRange	422133040	411287	0	0
maxM	900	900	0	0
rspIdInRange	422133040	3728843	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	322201	0	0
T1	2648	3	0	0
T2	12942	1	0	0
T3	355958	6	0	0
T7	83170	161	0	0
T8	13189	120	0	0
T9	1035	0	0	0
T10	13475	26	0	0
T11	432281	6	0	0
T12	362617	33	0	0
T13	6392	33	0	0
T14	0	130	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	411287	0	0
T1	2648	11	0	0
T2	12942	3	0	0
T3	355958	3	0	0
T7	83170	154	0	0
T8	13189	103	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	3	0	0
T12	362617	421	0	0
T13	6392	32	0	0
T14	0	106	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	3728843	0	0
T1	2648	14	0	0
T2	12942	11	0	0
T3	355958	1230	0	0
T7	83170	1108	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	132	0	0
T11	432281	2231	0	0
T12	362617	4536	0	0
T13	6392	63	0	0
T14	0	233	0	0

Line Coverage for Instance : tb.dut.u_sm1_30

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T11,T13,T25
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T11,T13,T25
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T11,T13,T25
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	422133040	9075122	0	0
gen_host_fifo[1].idInRange	422133040	1683375	0	0
gen_host_fifo[2].idInRange	422133040	1730155	0	0
maxM	900	900	0	0
rspIdInRange	422133040	20847267	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	9075122	0	0
T1	2648	32	0	0
T2	12942	308	0	0
T3	355958	248	0	0
T7	83170	5794	0	0
T8	13189	775	0	0
T9	1035	68	0	0
T10	13475	864	0	0
T11	432281	10797	0	0
T12	362617	23686	0	0
T13	6392	228	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1683375	0	0
T1	2648	7	0	0
T2	12942	71	0	0
T3	355958	28	0	0
T7	83170	855	0	0
T8	13189	140	0	0
T9	1035	0	0	0
T10	13475	136	0	0
T11	432281	640	0	0
T12	362617	5722	0	0
T13	6392	49	0	0
T14	0	114	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1730155	0	0
T1	2648	4	0	0
T2	12942	22	0	0
T3	355958	31	0	0
T7	83170	1048	0	0
T8	13189	142	0	0
T9	1035	0	0	0
T10	13475	190	0	0
T11	432281	1159	0	0
T12	362617	2906	0	0
T13	6392	50	0	0
T14	0	103	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	20847267	0	0
T1	2648	43	0	0
T2	12942	401	0	0
T3	355958	20921	0	0
T7	83170	6490	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	499	0	0
T11	432281	13275	0	0
T12	362617	13174	0	0
T13	6392	320	0	0