Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7933463	0	0
GntImpliesValid_A	2147483647	7933463	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7933463	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	446350815	0	0
ReadyAndValidImplyGrant_A	2147483647	7933463	0	0
ReqAndReadyImplyGrant_A	2147483647	7933463	0	0
ReqImpliesValid_A	2147483647	31736863	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	52048	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7933463	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	63552	61800	0	0
T2	310608	309456	0	0
T3	8542992	8540712	0	0
T7	1996080	1995600	0	0
T8	316536	316224	0	0
T9	24840	24456	0	0
T10	323400	322392	0	0
T11	10374744	10373736	0	0
T12	8702808	8702184	0	0
T13	153408	152208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7933463	0	0
T1	63552	416	0	0
T2	310608	435	0	0
T3	8542992	442	0	0
T7	1996080	8630	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	1325	0	0
T11	10374744	420	0	0
T12	8702808	906	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7933463	0	0
T1	63552	416	0	0
T2	310608	435	0	0
T3	8542992	442	0	0
T7	1996080	8630	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	1325	0	0
T11	10374744	420	0	0
T12	8702808	906	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	63552	61800	0	0
T2	310608	309456	0	0
T3	8542992	8540712	0	0
T7	1996080	1995600	0	0
T8	316536	316224	0	0
T9	24840	24456	0	0
T10	323400	322392	0	0
T11	10374744	10373736	0	0
T12	8702808	8702184	0	0
T13	153408	152208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	63552	61800	0	0
T2	310608	309456	0	0
T3	8542992	8540712	0	0
T7	1996080	1995600	0	0
T8	316536	316224	0	0
T9	24840	24456	0	0
T10	323400	322392	0	0
T11	10374744	10373736	0	0
T12	8702808	8702184	0	0
T13	153408	152208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7933463	0	0
T1	63552	416	0	0
T2	310608	435	0	0
T3	8542992	442	0	0
T7	1996080	8630	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	1325	0	0
T11	10374744	420	0	0
T12	8702808	906	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	446350815	0	0
T1	63552	855	0	0
T2	310608	14879	0	0
T3	8542992	298318	0	0
T7	1996080	127294	0	0
T8	316536	8862	0	0
T9	24840	154	0	0
T10	323400	21599	0	0
T11	10374744	530242	0	0
T12	8702808	569129	0	0
T13	153408	3171	0	0
T14	0	3672	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7933463	0	0
T1	63552	416	0	0
T2	310608	435	0	0
T3	8542992	442	0	0
T7	1996080	8630	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	1325	0	0
T11	10374744	420	0	0
T12	8702808	906	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7933463	0	0
T1	63552	416	0	0
T2	310608	435	0	0
T3	8542992	442	0	0
T7	1996080	8630	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	1325	0	0
T11	10374744	420	0	0
T12	8702808	906	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31736863	0	0
T1	63552	497	0	0
T2	310608	931	0	0
T3	8542992	773	0	0
T7	1996080	19734	0	0
T8	316536	9911	0	0
T9	24840	1252	0	0
T10	323400	3173	0	0
T11	10374744	21397	0	0
T12	8702808	46825	0	0
T13	153408	2883	0	0
T14	0	4020	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52048	0	21600
T7	166340	0	0	2
T8	26378	47	0	2
T9	2070	0	0	2
T10	26950	0	0	2
T11	864562	0	0	2
T12	725234	0	0	2
T13	12784	12	0	2
T14	38034	36	0	2
T15	16454	8	0	2
T16	0	13	0	0
T17	0	17	0	0
T18	0	25	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	6	0	0
T23	0	4	0	0
T24	4366	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	63552	61800	0	0
T2	310608	309456	0	0
T3	8542992	8540712	0	0
T7	1996080	1995600	0	0
T8	316536	316224	0	0
T9	24840	24456	0	0
T10	323400	322392	0	0
T11	10374744	10373736	0	0
T12	8702808	8702184	0	0
T13	153408	152208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7933463	0	0
T1	63552	416	0	0
T2	310608	435	0	0
T3	8542992	442	0	0
T7	1996080	8630	0	0
T8	316536	8777	0	0
T9	24840	761	0	0
T10	323400	1325	0	0
T11	10374744	420	0	0
T12	8702808	906	0	0
T13	153408	2625	0	0
T14	0	3897	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	877680	0	0
GntImpliesValid_A	422133040	877680	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	877680	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	10922131	0	0
ReadyAndValidImplyGrant_A	422133040	877680	0	0
ReqAndReadyImplyGrant_A	422133040	877680	0	0
ReqImpliesValid_A	422133040	2278476	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	877680	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	877680	0	0
T1	2648	36	0	0
T2	12942	49	0	0
T3	355958	55	0	0
T7	83170	961	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	148	0	0
T11	432281	50	0	0
T12	362617	91	0	0
T13	6392	296	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	877680	0	0
T1	2648	36	0	0
T2	12942	49	0	0
T3	355958	55	0	0
T7	83170	961	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	148	0	0
T11	432281	50	0	0
T12	362617	91	0	0
T13	6392	296	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	877680	0	0
T1	2648	36	0	0
T2	12942	49	0	0
T3	355958	55	0	0
T7	83170	961	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	148	0	0
T11	432281	50	0	0
T12	362617	91	0	0
T13	6392	296	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	10922131	0	0
T1	2648	30	0	0
T2	12942	349	0	0
T3	355958	225	0	0
T7	83170	7088	0	0
T8	13189	713	0	0
T9	1035	58	0	0
T10	13475	1105	0	0
T11	432281	16387	0	0
T12	362617	33411	0	0
T13	6392	250	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	877680	0	0
T1	2648	36	0	0
T2	12942	49	0	0
T3	355958	55	0	0
T7	83170	961	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	148	0	0
T11	432281	50	0	0
T12	362617	91	0	0
T13	6392	296	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	877680	0	0
T1	2648	36	0	0
T2	12942	49	0	0
T3	355958	55	0	0
T7	83170	961	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	148	0	0
T11	432281	50	0	0
T12	362617	91	0	0
T13	6392	296	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2278476	0	0
T1	2648	43	0	0
T2	12942	67	0	0
T3	355958	76	0	0
T7	83170	1784	0	0
T8	13189	1258	0	0
T9	1035	107	0	0
T10	13475	300	0	0
T11	432281	1162	0	0
T12	362617	3648	0	0
T13	6392	343	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	877680	0	0
T1	2648	36	0	0
T2	12942	49	0	0
T3	355958	55	0	0
T7	83170	961	0	0
T8	13189	985	0	0
T9	1035	82	0	0
T10	13475	148	0	0
T11	432281	50	0	0
T12	362617	91	0	0
T13	6392	296	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	865945	0	0
GntImpliesValid_A	422133040	865945	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	865945	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	10853296	0	0
ReadyAndValidImplyGrant_A	422133040	865945	0	0
ReqAndReadyImplyGrant_A	422133040	865945	0	0
ReqImpliesValid_A	422133040	2309650	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	865945	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	865945	0	0
T1	2648	33	0	0
T2	12942	39	0	0
T3	355958	49	0	0
T7	83170	957	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	157	0	0
T11	432281	44	0	0
T12	362617	88	0	0
T13	6392	272	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	865945	0	0
T1	2648	33	0	0
T2	12942	39	0	0
T3	355958	49	0	0
T7	83170	957	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	157	0	0
T11	432281	44	0	0
T12	362617	88	0	0
T13	6392	272	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	865945	0	0
T1	2648	33	0	0
T2	12942	39	0	0
T3	355958	49	0	0
T7	83170	957	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	157	0	0
T11	432281	44	0	0
T12	362617	88	0	0
T13	6392	272	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	10853296	0	0
T1	2648	33	0	0
T2	12942	347	0	0
T3	355958	192	0	0
T7	83170	7173	0	0
T8	13189	731	0	0
T9	1035	53	0	0
T10	13475	1113	0	0
T11	432281	13199	0	0
T12	362617	25709	0	0
T13	6392	241	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	865945	0	0
T1	2648	33	0	0
T2	12942	39	0	0
T3	355958	49	0	0
T7	83170	957	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	157	0	0
T11	432281	44	0	0
T12	362617	88	0	0
T13	6392	272	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	865945	0	0
T1	2648	33	0	0
T2	12942	39	0	0
T3	355958	49	0	0
T7	83170	957	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	157	0	0
T11	432281	44	0	0
T12	362617	88	0	0
T13	6392	272	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2309650	0	0
T1	2648	34	0	0
T2	12942	71	0	0
T3	355958	57	0	0
T7	83170	1830	0	0
T8	13189	1274	0	0
T9	1035	98	0	0
T10	13475	256	0	0
T11	432281	2653	0	0
T12	362617	1227	0	0
T13	6392	304	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	865945	0	0
T1	2648	33	0	0
T2	12942	39	0	0
T3	355958	49	0	0
T7	83170	957	0	0
T8	13189	1002	0	0
T9	1035	75	0	0
T10	13475	157	0	0
T11	432281	44	0	0
T12	362617	88	0	0
T13	6392	272	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	223032	0	0
GntImpliesValid_A	422133040	223032	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	223032	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2735665	0	0
ReadyAndValidImplyGrant_A	422133040	223032	0	0
ReqAndReadyImplyGrant_A	422133040	223032	0	0
ReqImpliesValid_A	422133040	584495	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	223032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223032	0	0
T1	2648	14	0	0
T2	12942	17	0	0
T3	355958	12	0	0
T7	83170	235	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	10	0	0
T12	362617	30	0	0
T13	6392	80	0	0
T14	0	232	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223032	0	0
T1	2648	14	0	0
T2	12942	17	0	0
T3	355958	12	0	0
T7	83170	235	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	10	0	0
T12	362617	30	0	0
T13	6392	80	0	0
T14	0	232	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223032	0	0
T1	2648	14	0	0
T2	12942	17	0	0
T3	355958	12	0	0
T7	83170	235	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	10	0	0
T12	362617	30	0	0
T13	6392	80	0	0
T14	0	232	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2735665	0	0
T1	2648	15	0	0
T2	12942	131	0	0
T3	355958	45	0	0
T7	83170	1710	0	0
T8	13189	239	0	0
T9	1035	1	0	0
T10	13475	268	0	0
T11	432281	2631	0	0
T12	362617	8680	0	0
T13	6392	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223032	0	0
T1	2648	14	0	0
T2	12942	17	0	0
T3	355958	12	0	0
T7	83170	235	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	10	0	0
T12	362617	30	0	0
T13	6392	80	0	0
T14	0	232	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223032	0	0
T1	2648	14	0	0
T2	12942	17	0	0
T3	355958	12	0	0
T7	83170	235	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	10	0	0
T12	362617	30	0	0
T13	6392	80	0	0
T14	0	232	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	584495	0	0
T1	2648	14	0	0
T2	12942	41	0	0
T3	355958	12	0	0
T7	83170	300	0	0
T8	13189	266	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	10	0	0
T12	362617	248	0	0
T13	6392	82	0	0
T14	0	235	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223032	0	0
T1	2648	14	0	0
T2	12942	17	0	0
T3	355958	12	0	0
T7	83170	235	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	10	0	0
T12	362617	30	0	0
T13	6392	80	0	0
T14	0	232	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	215911	0	0
GntImpliesValid_A	422133040	215911	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	215911	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2657769	0	0
ReadyAndValidImplyGrant_A	422133040	215911	0	0
ReqAndReadyImplyGrant_A	422133040	215911	0	0
ReqImpliesValid_A	422133040	536700	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	215911	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	215911	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	224	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	28	0	0
T13	6392	72	0	0
T14	0	195	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	215911	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	224	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	28	0	0
T13	6392	72	0	0
T14	0	195	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	215911	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	224	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	28	0	0
T13	6392	72	0	0
T14	0	195	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2657769	0	0
T1	2648	10	0	0
T2	12942	87	0	0
T3	355958	37	0	0
T7	83170	1659	0	0
T8	13189	252	0	0
T9	1035	1	0	0
T10	13475	279	0	0
T11	432281	3379	0	0
T12	362617	8425	0	0
T13	6392	71	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	215911	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	224	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	28	0	0
T13	6392	72	0	0
T14	0	195	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	215911	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	224	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	28	0	0
T13	6392	72	0	0
T14	0	195	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	536700	0	0
T1	2648	11	0	0
T2	12942	19	0	0
T3	355958	11	0	0
T7	83170	286	0	0
T8	13189	283	0	0
T9	1035	0	0	0
T10	13475	52	0	0
T11	432281	516	0	0
T12	362617	583	0	0
T13	6392	74	0	0
T14	0	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	215911	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	224	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	41	0	0
T11	432281	9	0	0
T12	362617	28	0	0
T13	6392	72	0	0
T14	0	195	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	223770	0	0
GntImpliesValid_A	422133040	223770	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	223770	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	4714494	0	0
ReadyAndValidImplyGrant_A	422133040	223770	0	0
ReqAndReadyImplyGrant_A	422133040	223770	0	0
ReqImpliesValid_A	422133040	1185432	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	223770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223770	0	0
T1	2648	12	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	218	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	35	0	0
T11	432281	8	0	0
T12	362617	28	0	0
T13	6392	73	0	0
T14	0	189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223770	0	0
T1	2648	12	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	218	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	35	0	0
T11	432281	8	0	0
T12	362617	28	0	0
T13	6392	73	0	0
T14	0	189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223770	0	0
T1	2648	12	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	218	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	35	0	0
T11	432281	8	0	0
T12	362617	28	0	0
T13	6392	73	0	0
T14	0	189	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4714494	0	0
T1	2648	185	0	0
T2	12942	183	0	0
T3	355958	133	0	0
T7	83170	1624	0	0
T8	13189	1058	0	0
T9	1035	0	0	0
T10	13475	1065	0	0
T11	432281	2404	0	0
T12	362617	2609	0	0
T13	6392	384	0	0
T14	0	717	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223770	0	0
T1	2648	12	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	218	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	35	0	0
T11	432281	8	0	0
T12	362617	28	0	0
T13	6392	73	0	0
T14	0	189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223770	0	0
T1	2648	12	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	218	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	35	0	0
T11	432281	8	0	0
T12	362617	28	0	0
T13	6392	73	0	0
T14	0	189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1185432	0	0
T1	2648	53	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	328	0	0
T8	13189	337	0	0
T9	1035	0	0	0
T10	13475	79	0	0
T11	432281	8	0	0
T12	362617	96	0	0
T13	6392	100	0	0
T14	0	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	223770	0	0
T1	2648	12	0	0
T2	12942	16	0	0
T3	355958	10	0	0
T7	83170	218	0	0
T8	13189	252	0	0
T9	1035	0	0	0
T10	13475	35	0	0
T11	432281	8	0	0
T12	362617	28	0	0
T13	6392	73	0	0
T14	0	189	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	213424	0	0
GntImpliesValid_A	422133040	213424	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	213424	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	3828131	0	0
ReadyAndValidImplyGrant_A	422133040	213424	0	0
ReqAndReadyImplyGrant_A	422133040	213424	0	0
ReqImpliesValid_A	422133040	909679	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	213424	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	213424	0	0
T1	2648	14	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	256	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	72	0	0
T14	0	226	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	213424	0	0
T1	2648	14	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	256	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	72	0	0
T14	0	226	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	213424	0	0
T1	2648	14	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	256	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	72	0	0
T14	0	226	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	3828131	0	0
T1	2648	76	0	0
T2	12942	478	0	0
T3	355958	205	0	0
T7	83170	1999	0	0
T8	13189	963	0	0
T9	1035	0	0	0
T10	13475	736	0	0
T11	432281	1390	0	0
T12	362617	3712	0	0
T13	6392	324	0	0
T14	0	805	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	213424	0	0
T1	2648	14	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	256	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	72	0	0
T14	0	226	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	213424	0	0
T1	2648	14	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	256	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	72	0	0
T14	0	226	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	909679	0	0
T1	2648	27	0	0
T2	12942	28	0	0
T3	355958	30	0	0
T7	83170	396	0	0
T8	13189	322	0	0
T9	1035	0	0	0
T10	13475	73	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	100	0	0
T14	0	236	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	213424	0	0
T1	2648	14	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	256	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	9	0	0
T12	362617	22	0	0
T13	6392	72	0	0
T14	0	226	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T7 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T7,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	218183	0	0
GntImpliesValid_A	422133040	218183	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	218183	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	4496025	0	0
ReadyAndValidImplyGrant_A	422133040	218183	0	0
ReqAndReadyImplyGrant_A	422133040	218183	0	0
ReqImpliesValid_A	422133040	1087635	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	218183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218183	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	246	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	64	0	0
T14	0	216	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218183	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	246	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	64	0	0
T14	0	216	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218183	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	246	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	64	0	0
T14	0	216	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4496025	0	0
T1	2648	244	0	0
T2	12942	171	0	0
T3	355958	105	0	0
T7	83170	1427	0	0
T8	13189	905	0	0
T9	1035	0	0	0
T10	13475	549	0	0
T11	432281	1655	0	0
T12	362617	2613	0	0
T13	6392	395	0	0
T14	0	883	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218183	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	246	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	64	0	0
T14	0	216	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218183	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	246	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	64	0	0
T14	0	216	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1087635	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	337	0	0
T8	13189	368	0	0
T9	1035	0	0	0
T10	13475	87	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	100	0	0
T14	0	227	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218183	0	0
T1	2648	12	0	0
T2	12942	6	0	0
T3	355958	7	0	0
T7	83170	246	0	0
T8	13189	240	0	0
T9	1035	0	0	0
T10	13475	36	0	0
T11	432281	9	0	0
T12	362617	26	0	0
T13	6392	64	0	0
T14	0	216	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	218754	0	0
GntImpliesValid_A	422133040	218754	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	218754	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	4245184	0	0
ReadyAndValidImplyGrant_A	422133040	218754	0	0
ReqAndReadyImplyGrant_A	422133040	218754	0	0
ReqImpliesValid_A	422133040	1059146	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	218754	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218754	0	0
T1	2648	13	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	220	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	20	0	0
T12	362617	21	0	0
T13	6392	79	0	0
T14	0	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218754	0	0
T1	2648	13	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	220	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	20	0	0
T12	362617	21	0	0
T13	6392	79	0	0
T14	0	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218754	0	0
T1	2648	13	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	220	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	20	0	0
T12	362617	21	0	0
T13	6392	79	0	0
T14	0	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	4245184	0	0
T1	2648	68	0	0
T2	12942	112	0	0
T3	355958	242	0	0
T7	83170	3933	0	0
T8	13189	906	0	0
T9	1035	0	0	0
T10	13475	506	0	0
T11	432281	3326	0	0
T12	362617	3917	0	0
T13	6392	438	0	0
T14	0	1267	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218754	0	0
T1	2648	13	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	220	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	20	0	0
T12	362617	21	0	0
T13	6392	79	0	0
T14	0	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218754	0	0
T1	2648	13	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	220	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	20	0	0
T12	362617	21	0	0
T13	6392	79	0	0
T14	0	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	1059146	0	0
T1	2648	25	0	0
T2	12942	25	0	0
T3	355958	10	0	0
T7	83170	597	0	0
T8	13189	284	0	0
T9	1035	0	0	0
T10	13475	63	0	0
T11	432281	916	0	0
T12	362617	21	0	0
T13	6392	111	0	0
T14	0	248	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218754	0	0
T1	2648	13	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	220	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	20	0	0
T12	362617	21	0	0
T13	6392	79	0	0
T14	0	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	224274	0	0
GntImpliesValid_A	422133040	224274	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	224274	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2702066	0	0
ReadyAndValidImplyGrant_A	422133040	224274	0	0
ReqAndReadyImplyGrant_A	422133040	224274	0	0
ReqImpliesValid_A	422133040	556772	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	224274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224274	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	9	0	0
T7	83170	240	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	28	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224274	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	9	0	0
T7	83170	240	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	28	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224274	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	9	0	0
T7	83170	240	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	28	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2702066	0	0
T1	2648	13	0	0
T2	12942	79	0	0
T3	355958	33	0	0
T7	83170	1819	0	0
T8	13189	249	0	0
T9	1035	26	0	0
T10	13475	184	0	0
T11	432281	5454	0	0
T12	362617	9650	0	0
T13	6392	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224274	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	9	0	0
T7	83170	240	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	28	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224274	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	9	0	0
T7	83170	240	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	28	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	556772	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	13	0	0
T7	83170	326	0	0
T8	13189	278	0	0
T9	1035	911	0	0
T10	13475	35	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224274	0	0
T1	2648	12	0	0
T2	12942	10	0	0
T3	355958	9	0	0
T7	83170	240	0	0
T8	13189	263	0	0
T9	1035	468	0	0
T10	13475	28	0	0
T11	432281	13	0	0
T12	362617	30	0	0
T13	6392	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	220554	0	0
GntImpliesValid_A	422133040	220554	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	220554	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2775409	0	0
ReadyAndValidImplyGrant_A	422133040	220554	0	0
ReqAndReadyImplyGrant_A	422133040	220554	0	0
ReqImpliesValid_A	422133040	521773	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	220554	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	220554	0	0
T1	2648	16	0	0
T2	12942	12	0	0
T3	355958	17	0	0
T7	83170	234	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	49	0	0
T11	432281	14	0	0
T12	362617	27	0	0
T13	6392	79	0	0
T14	0	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	220554	0	0
T1	2648	16	0	0
T2	12942	12	0	0
T3	355958	17	0	0
T7	83170	234	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	49	0	0
T11	432281	14	0	0
T12	362617	27	0	0
T13	6392	79	0	0
T14	0	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	220554	0	0
T1	2648	16	0	0
T2	12942	12	0	0
T3	355958	17	0	0
T7	83170	234	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	49	0	0
T11	432281	14	0	0
T12	362617	27	0	0
T13	6392	79	0	0
T14	0	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2775409	0	0
T1	2648	17	0	0
T2	12942	86	0	0
T3	355958	84	0	0
T7	83170	1705	0	0
T8	13189	201	0	0
T9	1035	1	0	0
T10	13475	398	0	0
T11	432281	6045	0	0
T12	362617	7505	0	0
T13	6392	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	220554	0	0
T1	2648	16	0	0
T2	12942	12	0	0
T3	355958	17	0	0
T7	83170	234	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	49	0	0
T11	432281	14	0	0
T12	362617	27	0	0
T13	6392	79	0	0
T14	0	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	220554	0	0
T1	2648	16	0	0
T2	12942	12	0	0
T3	355958	17	0	0
T7	83170	234	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	49	0	0
T11	432281	14	0	0
T12	362617	27	0	0
T13	6392	79	0	0
T14	0	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	521773	0	0
T1	2648	16	0	0
T2	12942	19	0	0
T3	355958	19	0	0
T7	83170	330	0	0
T8	13189	242	0	0
T9	1035	0	0	0
T10	13475	68	0	0
T11	432281	14	0	0
T12	362617	341	0	0
T13	6392	84	0	0
T14	0	225	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	220554	0	0
T1	2648	16	0	0
T2	12942	12	0	0
T3	355958	17	0	0
T7	83170	234	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	49	0	0
T11	432281	14	0	0
T12	362617	27	0	0
T13	6392	79	0	0
T14	0	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	212409	0	0
GntImpliesValid_A	422133040	212409	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	212409	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2730881	0	0
ReadyAndValidImplyGrant_A	422133040	212409	0	0
ReqAndReadyImplyGrant_A	422133040	212409	0	0
ReqImpliesValid_A	422133040	508038	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	212409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	212409	0	0
T1	2648	15	0	0
T2	12942	14	0	0
T3	355958	12	0	0
T7	83170	273	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	38	0	0
T11	432281	15	0	0
T12	362617	28	0	0
T13	6392	69	0	0
T14	0	199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	212409	0	0
T1	2648	15	0	0
T2	12942	14	0	0
T3	355958	12	0	0
T7	83170	273	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	38	0	0
T11	432281	15	0	0
T12	362617	28	0	0
T13	6392	69	0	0
T14	0	199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	212409	0	0
T1	2648	15	0	0
T2	12942	14	0	0
T3	355958	12	0	0
T7	83170	273	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	38	0	0
T11	432281	15	0	0
T12	362617	28	0	0
T13	6392	69	0	0
T14	0	199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2730881	0	0
T1	2648	14	0	0
T2	12942	142	0	0
T3	355958	66	0	0
T7	83170	1934	0	0
T8	13189	212	0	0
T9	1035	1	0	0
T10	13475	309	0	0
T11	432281	5128	0	0
T12	362617	9156	0	0
T13	6392	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	212409	0	0
T1	2648	15	0	0
T2	12942	14	0	0
T3	355958	12	0	0
T7	83170	273	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	38	0	0
T11	432281	15	0	0
T12	362617	28	0	0
T13	6392	69	0	0
T14	0	199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	212409	0	0
T1	2648	15	0	0
T2	12942	14	0	0
T3	355958	12	0	0
T7	83170	273	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	38	0	0
T11	432281	15	0	0
T12	362617	28	0	0
T13	6392	69	0	0
T14	0	199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	508038	0	0
T1	2648	17	0	0
T2	12942	14	0	0
T3	355958	15	0	0
T7	83170	414	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	43	0	0
T11	432281	15	0	0
T12	362617	1064	0	0
T13	6392	73	0	0
T14	0	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	212409	0	0
T1	2648	15	0	0
T2	12942	14	0	0
T3	355958	12	0	0
T7	83170	273	0	0
T8	13189	228	0	0
T9	1035	0	0	0
T10	13475	38	0	0
T11	432281	15	0	0
T12	362617	28	0	0
T13	6392	69	0	0
T14	0	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	222479	0	0
GntImpliesValid_A	422133040	222479	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	222479	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2750687	0	0
ReadyAndValidImplyGrant_A	422133040	222479	0	0
ReqAndReadyImplyGrant_A	422133040	222479	0	0
ReqImpliesValid_A	422133040	580692	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	222479	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	222479	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	10	0	0
T7	83170	248	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	11	0	0
T12	362617	29	0	0
T13	6392	72	0	0
T14	0	210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	222479	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	10	0	0
T7	83170	248	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	11	0	0
T12	362617	29	0	0
T13	6392	72	0	0
T14	0	210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	222479	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	10	0	0
T7	83170	248	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	11	0	0
T12	362617	29	0	0
T13	6392	72	0	0
T14	0	210	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2750687	0	0
T1	2648	10	0	0
T2	12942	100	0	0
T3	355958	35	0	0
T7	83170	1799	0	0
T8	13189	204	0	0
T9	1035	1	0	0
T10	13475	269	0	0
T11	432281	2851	0	0
T12	362617	6450	0	0
T13	6392	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	222479	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	10	0	0
T7	83170	248	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	11	0	0
T12	362617	29	0	0
T13	6392	72	0	0
T14	0	210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	222479	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	10	0	0
T7	83170	248	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	11	0	0
T12	362617	29	0	0
T13	6392	72	0	0
T14	0	210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	580692	0	0
T1	2648	11	0	0
T2	12942	14	0	0
T3	355958	19	0	0
T7	83170	362	0	0
T8	13189	221	0	0
T9	1035	0	0	0
T10	13475	44	0	0
T11	432281	11	0	0
T12	362617	1550	0	0
T13	6392	80	0	0
T14	0	212	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	222479	0	0
T1	2648	10	0	0
T2	12942	14	0	0
T3	355958	10	0	0
T7	83170	248	0	0
T8	13189	212	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	11	0	0
T12	362617	29	0	0
T13	6392	72	0	0
T14	0	210	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	216871	0	0
GntImpliesValid_A	422133040	216871	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	216871	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2749060	0	0
ReadyAndValidImplyGrant_A	422133040	216871	0	0
ReqAndReadyImplyGrant_A	422133040	216871	0	0
ReqImpliesValid_A	422133040	571870	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	216871	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	216871	0	0
T1	2648	9	0	0
T2	12942	17	0	0
T3	355958	8	0	0
T7	83170	256	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	78	0	0
T14	0	198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	216871	0	0
T1	2648	9	0	0
T2	12942	17	0	0
T3	355958	8	0	0
T7	83170	256	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	78	0	0
T14	0	198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	216871	0	0
T1	2648	9	0	0
T2	12942	17	0	0
T3	355958	8	0	0
T7	83170	256	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	78	0	0
T14	0	198	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2749060	0	0
T1	2648	10	0	0
T2	12942	162	0	0
T3	355958	32	0	0
T7	83170	1922	0	0
T8	13189	236	0	0
T9	1035	1	0	0
T10	13475	227	0	0
T11	432281	3961	0	0
T12	362617	5099	0	0
T13	6392	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	216871	0	0
T1	2648	9	0	0
T2	12942	17	0	0
T3	355958	8	0	0
T7	83170	256	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	78	0	0
T14	0	198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	216871	0	0
T1	2648	9	0	0
T2	12942	17	0	0
T3	355958	8	0	0
T7	83170	256	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	78	0	0
T14	0	198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	571870	0	0
T1	2648	9	0	0
T2	12942	26	0	0
T3	355958	14	0	0
T7	83170	316	0	0
T8	13189	255	0	0
T9	1035	0	0	0
T10	13475	43	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	82	0	0
T14	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	216871	0	0
T1	2648	9	0	0
T2	12942	17	0	0
T3	355958	8	0	0
T7	83170	256	0	0
T8	13189	245	0	0
T9	1035	0	0	0
T10	13475	32	0	0
T11	432281	13	0	0
T12	362617	19	0	0
T13	6392	78	0	0
T14	0	198	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	218919	0	0
GntImpliesValid_A	422133040	218919	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	218919	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2713834	0	0
ReadyAndValidImplyGrant_A	422133040	218919	0	0
ReqAndReadyImplyGrant_A	422133040	218919	0	0
ReqImpliesValid_A	422133040	529703	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	218919	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218919	0	0
T1	2648	17	0	0
T2	12942	17	0	0
T3	355958	9	0	0
T7	83170	228	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	31	0	0
T11	432281	17	0	0
T12	362617	35	0	0
T13	6392	73	0	0
T14	0	206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218919	0	0
T1	2648	17	0	0
T2	12942	17	0	0
T3	355958	9	0	0
T7	83170	228	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	31	0	0
T11	432281	17	0	0
T12	362617	35	0	0
T13	6392	73	0	0
T14	0	206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218919	0	0
T1	2648	17	0	0
T2	12942	17	0	0
T3	355958	9	0	0
T7	83170	228	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	31	0	0
T11	432281	17	0	0
T12	362617	35	0	0
T13	6392	73	0	0
T14	0	206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2713834	0	0
T1	2648	16	0	0
T2	12942	143	0	0
T3	355958	37	0	0
T7	83170	1642	0	0
T8	13189	229	0	0
T9	1035	1	0	0
T10	13475	254	0	0
T11	432281	5892	0	0
T12	362617	10184	0	0
T13	6392	71	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218919	0	0
T1	2648	17	0	0
T2	12942	17	0	0
T3	355958	9	0	0
T7	83170	228	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	31	0	0
T11	432281	17	0	0
T12	362617	35	0	0
T13	6392	73	0	0
T14	0	206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218919	0	0
T1	2648	17	0	0
T2	12942	17	0	0
T3	355958	9	0	0
T7	83170	228	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	31	0	0
T11	432281	17	0	0
T12	362617	35	0	0
T13	6392	73	0	0
T14	0	206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	529703	0	0
T1	2648	19	0	0
T2	12942	19	0	0
T3	355958	9	0	0
T7	83170	307	0	0
T8	13189	248	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	317	0	0
T12	362617	426	0	0
T13	6392	76	0	0
T14	0	209	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218919	0	0
T1	2648	17	0	0
T2	12942	17	0	0
T3	355958	9	0	0
T7	83170	228	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	31	0	0
T11	432281	17	0	0
T12	362617	35	0	0
T13	6392	73	0	0
T14	0	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	221534	0	0
GntImpliesValid_A	422133040	221534	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	221534	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2805258	0	0
ReadyAndValidImplyGrant_A	422133040	221534	0	0
ReqAndReadyImplyGrant_A	422133040	221534	0	0
ReqImpliesValid_A	422133040	525431	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	221534	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221534	0	0
T1	2648	16	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	232	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	11	0	0
T12	362617	25	0	0
T13	6392	60	0	0
T14	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221534	0	0
T1	2648	16	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	232	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	11	0	0
T12	362617	25	0	0
T13	6392	60	0	0
T14	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221534	0	0
T1	2648	16	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	232	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	11	0	0
T12	362617	25	0	0
T13	6392	60	0	0
T14	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2805258	0	0
T1	2648	17	0	0
T2	12942	58	0	0
T3	355958	30	0	0
T7	83170	1789	0	0
T8	13189	221	0	0
T9	1035	1	0	0
T10	13475	358	0	0
T11	432281	3479	0	0
T12	362617	6585	0	0
T13	6392	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221534	0	0
T1	2648	16	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	232	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	11	0	0
T12	362617	25	0	0
T13	6392	60	0	0
T14	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221534	0	0
T1	2648	16	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	232	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	11	0	0
T12	362617	25	0	0
T13	6392	60	0	0
T14	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	525431	0	0
T1	2648	16	0	0
T2	12942	14	0	0
T3	355958	8	0	0
T7	83170	390	0	0
T8	13189	242	0	0
T9	1035	0	0	0
T10	13475	60	0	0
T11	432281	11	0	0
T12	362617	876	0	0
T13	6392	61	0	0
T14	0	203	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221534	0	0
T1	2648	16	0	0
T2	12942	8	0	0
T3	355958	8	0	0
T7	83170	232	0	0
T8	13189	231	0	0
T9	1035	0	0	0
T10	13475	45	0	0
T11	432281	11	0	0
T12	362617	25	0	0
T13	6392	60	0	0
T14	0	200	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	228645	0	0
GntImpliesValid_A	422133040	228645	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	228645	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2694396	0	0
ReadyAndValidImplyGrant_A	422133040	228645	0	0
ReqAndReadyImplyGrant_A	422133040	228645	0	0
ReqImpliesValid_A	422133040	614200	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	228645	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	228645	0	0
T1	2648	17	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	235	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	50	0	0
T11	432281	16	0	0
T12	362617	31	0	0
T13	6392	85	0	0
T14	0	197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	228645	0	0
T1	2648	17	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	235	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	50	0	0
T11	432281	16	0	0
T12	362617	31	0	0
T13	6392	85	0	0
T14	0	197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	228645	0	0
T1	2648	17	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	235	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	50	0	0
T11	432281	16	0	0
T12	362617	31	0	0
T13	6392	85	0	0
T14	0	197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2694396	0	0
T1	2648	17	0	0
T2	12942	72	0	0
T3	355958	63	0	0
T7	83170	1656	0	0
T8	13189	197	0	0
T9	1035	1	0	0
T10	13475	291	0	0
T11	432281	5996	0	0
T12	362617	9430	0	0
T13	6392	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	228645	0	0
T1	2648	17	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	235	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	50	0	0
T11	432281	16	0	0
T12	362617	31	0	0
T13	6392	85	0	0
T14	0	197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	228645	0	0
T1	2648	17	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	235	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	50	0	0
T11	432281	16	0	0
T12	362617	31	0	0
T13	6392	85	0	0
T14	0	197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	614200	0	0
T1	2648	18	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	302	0	0
T8	13189	224	0	0
T9	1035	0	0	0
T10	13475	82	0	0
T11	432281	16	0	0
T12	362617	170	0	0
T13	6392	91	0	0
T14	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	228645	0	0
T1	2648	17	0	0
T2	12942	10	0	0
T3	355958	10	0	0
T7	83170	235	0	0
T8	13189	210	0	0
T9	1035	0	0	0
T10	13475	50	0	0
T11	432281	16	0	0
T12	362617	31	0	0
T13	6392	85	0	0
T14	0	197	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	240147	0	0
GntImpliesValid_A	422133040	240147	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	240147	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2828845	0	0
ReadyAndValidImplyGrant_A	422133040	240147	0	0
ReqAndReadyImplyGrant_A	422133040	240147	0	0
ReqImpliesValid_A	422133040	578245	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	240147	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	240147	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	13	0	0
T7	83170	254	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	15	0	0
T12	362617	23	0	0
T13	6392	107	0	0
T14	0	206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	240147	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	13	0	0
T7	83170	254	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	15	0	0
T12	362617	23	0	0
T13	6392	107	0	0
T14	0	206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	240147	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	13	0	0
T7	83170	254	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	15	0	0
T12	362617	23	0	0
T13	6392	107	0	0
T14	0	206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2828845	0	0
T1	2648	15	0	0
T2	12942	109	0	0
T3	355958	57	0	0
T7	83170	1966	0	0
T8	13189	235	0	0
T9	1035	1	0	0
T10	13475	249	0	0
T11	432281	5633	0	0
T12	362617	8341	0	0
T13	6392	101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	240147	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	13	0	0
T7	83170	254	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	15	0	0
T12	362617	23	0	0
T13	6392	107	0	0
T14	0	206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	240147	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	13	0	0
T7	83170	254	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	15	0	0
T12	362617	23	0	0
T13	6392	107	0	0
T14	0	206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	578245	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	15	0	0
T7	83170	356	0	0
T8	13189	264	0	0
T9	1035	0	0	0
T10	13475	89	0	0
T11	432281	242	0	0
T12	362617	23	0	0
T13	6392	114	0	0
T14	0	206	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	240147	0	0
T1	2648	14	0	0
T2	12942	15	0	0
T3	355958	13	0	0
T7	83170	254	0	0
T8	13189	249	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	15	0	0
T12	362617	23	0	0
T13	6392	107	0	0
T14	0	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	217523	0	0
GntImpliesValid_A	422133040	217523	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	217523	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2751255	0	0
ReadyAndValidImplyGrant_A	422133040	217523	0	0
ReqAndReadyImplyGrant_A	422133040	217523	0	0
ReqImpliesValid_A	422133040	561093	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	217523	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	217523	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	235	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	24	0	0
T11	432281	7	0	0
T12	362617	23	0	0
T13	6392	69	0	0
T14	0	193	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	217523	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	235	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	24	0	0
T11	432281	7	0	0
T12	362617	23	0	0
T13	6392	69	0	0
T14	0	193	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	217523	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	235	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	24	0	0
T11	432281	7	0	0
T12	362617	23	0	0
T13	6392	69	0	0
T14	0	193	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2751255	0	0
T1	2648	7	0	0
T2	12942	112	0	0
T3	355958	68	0	0
T7	83170	1671	0	0
T8	13189	240	0	0
T9	1035	1	0	0
T10	13475	181	0	0
T11	432281	2005	0	0
T12	362617	8202	0	0
T13	6392	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	217523	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	235	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	24	0	0
T11	432281	7	0	0
T12	362617	23	0	0
T13	6392	69	0	0
T14	0	193	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	217523	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	235	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	24	0	0
T11	432281	7	0	0
T12	362617	23	0	0
T13	6392	69	0	0
T14	0	193	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	561093	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	16	0	0
T7	83170	326	0	0
T8	13189	267	0	0
T9	1035	0	0	0
T10	13475	27	0	0
T11	432281	7	0	0
T12	362617	712	0	0
T13	6392	71	0	0
T14	0	195	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	217523	0	0
T1	2648	6	0	0
T2	12942	14	0	0
T3	355958	11	0	0
T7	83170	235	0	0
T8	13189	253	0	0
T9	1035	0	0	0
T10	13475	24	0	0
T11	432281	7	0	0
T12	362617	23	0	0
T13	6392	69	0	0
T14	0	193	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	224921	0	0
GntImpliesValid_A	422133040	224921	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	224921	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2795588	0	0
ReadyAndValidImplyGrant_A	422133040	224921	0	0
ReqAndReadyImplyGrant_A	422133040	224921	0	0
ReqImpliesValid_A	422133040	545662	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	224921	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224921	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	21	0	0
T7	83170	246	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	11	0	0
T12	362617	32	0	0
T13	6392	64	0	0
T14	0	193	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224921	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	21	0	0
T7	83170	246	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	11	0	0
T12	362617	32	0	0
T13	6392	64	0	0
T14	0	193	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224921	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	21	0	0
T7	83170	246	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	11	0	0
T12	362617	32	0	0
T13	6392	64	0	0
T14	0	193	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2795588	0	0
T1	2648	9	0	0
T2	12942	60	0	0
T3	355958	75	0	0
T7	83170	1951	0	0
T8	13189	230	0	0
T9	1035	1	0	0
T10	13475	305	0	0
T11	432281	3865	0	0
T12	362617	11347	0	0
T13	6392	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224921	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	21	0	0
T7	83170	246	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	11	0	0
T12	362617	32	0	0
T13	6392	64	0	0
T14	0	193	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224921	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	21	0	0
T7	83170	246	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	11	0	0
T12	362617	32	0	0
T13	6392	64	0	0
T14	0	193	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	545662	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	24	0	0
T7	83170	393	0	0
T8	13189	247	0	0
T9	1035	0	0	0
T10	13475	100	0	0
T11	432281	544	0	0
T12	362617	1288	0	0
T13	6392	67	0	0
T14	0	195	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	224921	0	0
T1	2648	8	0	0
T2	12942	10	0	0
T3	355958	21	0	0
T7	83170	246	0	0
T8	13189	238	0	0
T9	1035	0	0	0
T10	13475	37	0	0
T11	432281	11	0	0
T12	362617	32	0	0
T13	6392	64	0	0
T14	0	193	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	218115	0	0
GntImpliesValid_A	422133040	218115	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	218115	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2733256	0	0
ReadyAndValidImplyGrant_A	422133040	218115	0	0
ReqAndReadyImplyGrant_A	422133040	218115	0	0
ReqImpliesValid_A	422133040	549754	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	218115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218115	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	8	0	0
T7	83170	248	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	20	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218115	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	8	0	0
T7	83170	248	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	20	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218115	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	8	0	0
T7	83170	248	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	20	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2733256	0	0
T1	2648	12	0	0
T2	12942	90	0	0
T3	355958	50	0	0
T7	83170	1910	0	0
T8	13189	226	0	0
T9	1035	1	0	0
T10	13475	333	0	0
T11	432281	7132	0	0
T12	362617	6440	0	0
T13	6392	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218115	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	8	0	0
T7	83170	248	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	20	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218115	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	8	0	0
T7	83170	248	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	20	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	549754	0	0
T1	2648	11	0	0
T2	12942	16	0	0
T3	355958	8	0	0
T7	83170	335	0	0
T8	13189	263	0	0
T9	1035	0	0	0
T10	13475	55	0	0
T11	432281	618	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	218115	0	0
T1	2648	11	0	0
T2	12942	10	0	0
T3	355958	8	0	0
T7	83170	248	0	0
T8	13189	244	0	0
T9	1035	0	0	0
T10	13475	39	0	0
T11	432281	20	0	0
T12	362617	24	0	0
T13	6392	64	0	0
T14	0	205	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	225922	0	0
GntImpliesValid_A	422133040	225922	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	225922	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2760044	0	0
ReadyAndValidImplyGrant_A	422133040	225922	0	0
ReqAndReadyImplyGrant_A	422133040	225922	0	0
ReqImpliesValid_A	422133040	582368	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	225922	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	225922	0	0
T1	2648	19	0	0
T2	12942	15	0	0
T3	355958	5	0	0
T7	83170	221	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	58	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	81	0	0
T14	0	192	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	225922	0	0
T1	2648	19	0	0
T2	12942	15	0	0
T3	355958	5	0	0
T7	83170	221	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	58	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	81	0	0
T14	0	192	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	225922	0	0
T1	2648	19	0	0
T2	12942	15	0	0
T3	355958	5	0	0
T7	83170	221	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	58	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	81	0	0
T14	0	192	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2760044	0	0
T1	2648	20	0	0
T2	12942	103	0	0
T3	355958	30	0	0
T7	83170	1715	0	0
T8	13189	205	0	0
T9	1035	1	0	0
T10	13475	391	0	0
T11	432281	2007	0	0
T12	362617	9744	0	0
T13	6392	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	225922	0	0
T1	2648	19	0	0
T2	12942	15	0	0
T3	355958	5	0	0
T7	83170	221	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	58	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	81	0	0
T14	0	192	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	225922	0	0
T1	2648	19	0	0
T2	12942	15	0	0
T3	355958	5	0	0
T7	83170	221	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	58	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	81	0	0
T14	0	192	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	582368	0	0
T1	2648	19	0	0
T2	12942	21	0	0
T3	355958	5	0	0
T7	83170	316	0	0
T8	13189	246	0	0
T9	1035	0	0	0
T10	13475	96	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	86	0	0
T14	0	194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	225922	0	0
T1	2648	19	0	0
T2	12942	15	0	0
T3	355958	5	0	0
T7	83170	221	0	0
T8	13189	225	0	0
T9	1035	0	0	0
T10	13475	58	0	0
T11	432281	7	0	0
T12	362617	28	0	0
T13	6392	81	0	0
T14	0	192	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T7 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T7,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	221235	0	0
GntImpliesValid_A	422133040	221235	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	221235	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	2776840	0	0
ReadyAndValidImplyGrant_A	422133040	221235	0	0
ReqAndReadyImplyGrant_A	422133040	221235	0	0
ReqImpliesValid_A	422133040	605005	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	0	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	221235	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221235	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	254	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	9	0	0
T12	362617	25	0	0
T13	6392	63	0	0
T14	0	233	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221235	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	254	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	9	0	0
T12	362617	25	0	0
T13	6392	63	0	0
T14	0	233	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221235	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	254	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	9	0	0
T12	362617	25	0	0
T13	6392	63	0	0
T14	0	233	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2776840	0	0
T1	2648	15	0	0
T2	12942	24	0	0
T3	355958	41	0	0
T7	83170	2036	0	0
T8	13189	208	0	0
T9	1035	1	0	0
T10	13475	221	0	0
T11	432281	3840	0	0
T12	362617	8146	0	0
T13	6392	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221235	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	254	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	9	0	0
T12	362617	25	0	0
T13	6392	63	0	0
T14	0	233	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221235	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	254	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	9	0	0
T12	362617	25	0	0
T13	6392	63	0	0
T14	0	233	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	605005	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	315	0	0
T8	13189	223	0	0
T9	1035	0	0	0
T10	13475	60	0	0
T11	432281	9	0	0
T12	362617	454	0	0
T13	6392	65	0	0
T14	0	235	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	221235	0	0
T1	2648	14	0	0
T2	12942	4	0	0
T3	355958	9	0	0
T7	83170	254	0	0
T8	13189	215	0	0
T9	1035	0	0	0
T10	13475	34	0	0
T11	432281	9	0	0
T12	362617	25	0	0
T13	6392	63	0	0
T14	0	233	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	888722	0	0
GntImpliesValid_A	422133040	888722	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	888722	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	10075893	0	0
ReadyAndValidImplyGrant_A	422133040	888722	0	0
ReqAndReadyImplyGrant_A	422133040	888722	0	0
ReqImpliesValid_A	422133040	2078728	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	21895	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	888722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	888722	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	56	0	0
T7	83170	952	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	126	0	0
T11	432281	38	0	0
T12	362617	104	0	0
T13	6392	272	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	888722	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	56	0	0
T7	83170	952	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	126	0	0
T11	432281	38	0	0
T12	362617	104	0	0
T13	6392	272	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	888722	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	56	0	0
T7	83170	952	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	126	0	0
T11	432281	38	0	0
T12	362617	104	0	0
T13	6392	272	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	10075893	0	0
T1	2648	1	0	0
T2	12942	334	0	0
T3	355958	175	0	0
T7	83170	6031	0	0
T8	13189	1	0	0
T9	1035	1	0	0
T10	13475	794	0	0
T11	432281	12537	0	0
T12	362617	33550	0	0
T13	6392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	888722	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	56	0	0
T7	83170	952	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	126	0	0
T11	432281	38	0	0
T12	362617	104	0	0
T13	6392	272	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	888722	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	56	0	0
T7	83170	952	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	126	0	0
T11	432281	38	0	0
T12	362617	104	0	0
T13	6392	272	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	2078728	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	69	0	0
T7	83170	1650	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	234	0	0
T11	432281	1681	0	0
T12	362617	2215	0	0
T13	6392	272	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	21895	0	900
T7	83170	0	0	1
T8	13189	25	0	1
T9	1035	0	0	1
T10	13475	0	0	1
T11	432281	0	0	1
T12	362617	0	0	1
T13	6392	4	0	1
T14	19017	23	0	1
T15	8227	3	0	1
T16	0	5	0	0
T17	0	8	0	0
T18	0	25	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	3	0	0
T24	2183	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	888722	0	0
T1	2648	45	0	0
T2	12942	51	0	0
T3	355958	56	0	0
T7	83170	952	0	0
T8	13189	1016	0	0
T9	1035	68	0	0
T10	13475	126	0	0
T11	432281	38	0	0
T12	362617	104	0	0
T13	6392	272	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422133040	422011185	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422133040	874494	0	0
GntImpliesValid_A	422133040	874494	0	0
GrantKnown_A	422133040	422011185	0	0
IdxKnown_A	422133040	422011185	0	0
IndexIsCorrect_A	422133040	874494	0	0
LockArbDecision_A	422133040	0	0	0
NoReadyValidNoGrant_A	422133040	353254808	0	0
ReadyAndValidImplyGrant_A	422133040	874494	0	0
ReqAndReadyImplyGrant_A	422133040	874494	0	0
ReqImpliesValid_A	422133040	11876316	0	0
ReqStaysHighUntilGranted0_M	422133040	0	0	0
RoundRobin_A	422133040	30153	0	900
ValidKnown_A	422133040	422011185	0	0
gen_data_port_assertion.DataFlow_A	422133040	874494	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	874494	0	0
T1	2648	43	0	0
T2	12942	49	0	0
T3	355958	66	0	0
T7	83170	957	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	136	0	0
T11	432281	44	0	0
T12	362617	89	0	0
T13	6392	320	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	874494	0	0
T1	2648	43	0	0
T2	12942	49	0	0
T3	355958	66	0	0
T7	83170	957	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	136	0	0
T11	432281	44	0	0
T12	362617	89	0	0
T13	6392	320	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	874494	0	0
T1	2648	43	0	0
T2	12942	49	0	0
T3	355958	66	0	0
T7	83170	957	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	136	0	0
T11	432281	44	0	0
T12	362617	89	0	0
T13	6392	320	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	353254808	0	0
T1	2648	1	0	0
T2	12942	11347	0	0
T3	355958	296258	0	0
T7	83170	69135	0	0
T8	13189	1	0	0
T9	1035	1	0	0
T10	13475	11214	0	0
T11	432281	410046	0	0
T12	362617	330224	0	0
T13	6392	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	874494	0	0
T1	2648	43	0	0
T2	12942	49	0	0
T3	355958	66	0	0
T7	83170	957	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	136	0	0
T11	432281	44	0	0
T12	362617	89	0	0
T13	6392	320	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	874494	0	0
T1	2648	43	0	0
T2	12942	49	0	0
T3	355958	66	0	0
T7	83170	957	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	136	0	0
T11	432281	44	0	0
T12	362617	89	0	0
T13	6392	320	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	11876316	0	0
T1	2648	43	0	0
T2	12942	401	0	0
T3	355958	307	0	0
T7	83170	7438	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	1149	0	0
T11	432281	12596	0	0
T12	362617	31734	0	0
T13	6392	320	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	30153	0	900
T7	83170	0	0	1
T8	13189	22	0	1
T9	1035	0	0	1
T10	13475	0	0	1
T11	432281	0	0	1
T12	362617	0	0	1
T13	6392	8	0	1
T14	19017	13	0	1
T15	8227	5	0	1
T16	0	8	0	0
T17	0	9	0	0
T19	0	1	0	0
T21	0	7	0	0
T22	0	6	0	0
T23	0	4	0	0
T24	2183	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	422011185	0	0
T1	2648	2575	0	0
T2	12942	12894	0	0
T3	355958	355863	0	0
T7	83170	83150	0	0
T8	13189	13176	0	0
T9	1035	1019	0	0
T10	13475	13433	0	0
T11	432281	432239	0	0
T12	362617	362591	0	0
T13	6392	6342	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422133040	874494	0	0
T1	2648	43	0	0
T2	12942	49	0	0
T3	355958	66	0	0
T7	83170	957	0	0
T8	13189	1038	0	0
T9	1035	68	0	0
T10	13475	136	0	0
T11	432281	44	0	0
T12	362617	89	0	0
T13	6392	320	0	0