Unified Coverage Report :: Module :: tlul_socket_m1

Module : tlul_socket_m1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28	95.96	100.00	87.88				100.00
tb.dut.u_sm1_29	95.96	100.00	87.88				100.00
tb.dut.u_sm1_31	95.96	100.00	87.88				100.00
tb.dut.u_sm1_33	96.97	100.00	90.91				100.00
tb.dut.u_sm1_34	96.97	100.00	90.91				100.00
tb.dut.u_sm1_36	96.97	100.00	90.91				100.00
tb.dut.u_sm1_38	96.97	100.00	90.91				100.00
tb.dut.u_sm1_40	96.97	100.00	90.91				100.00
tb.dut.u_sm1_42	96.97	100.00	90.91				100.00
tb.dut.u_sm1_43	96.97	100.00	90.91				100.00
tb.dut.u_sm1_44	96.97	100.00	90.91				100.00
tb.dut.u_sm1_45	96.97	100.00	90.91				100.00
tb.dut.u_sm1_46	96.97	100.00	90.91				100.00
tb.dut.u_sm1_47	96.97	100.00	90.91				100.00
tb.dut.u_sm1_48	96.97	100.00	90.91				100.00
tb.dut.u_sm1_49	96.97	100.00	90.91				100.00
tb.dut.u_sm1_50	96.97	100.00	90.91				100.00
tb.dut.u_sm1_51	96.97	100.00	90.91				100.00
tb.dut.u_sm1_52	96.97	100.00	90.91				100.00
tb.dut.u_sm1_53	96.97	100.00	90.91				100.00
tb.dut.u_sm1_54	96.97	100.00	90.91				100.00
tb.dut.u_sm1_55	96.97	100.00	90.91				100.00
tb.dut.u_sm1_56	96.97	100.00	90.91				100.00
tb.dut.u_sm1_30	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sm1_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.51	98.68	85.92			92.73	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	92.21	97.50	82.14			89.19	100.00

---

Module Instance : tb.dut.u_sm1_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	98.68	85.07			92.59	95.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.90	100.00	93.62			100.00	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.43	98.54	84.87			92.31	94.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78	100.00	98.39			100.00	96.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_28

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_29

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_33

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_34

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_36

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_38

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_40

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_42

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_43

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_44

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_45

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_46

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_47

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_48

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_49

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_50

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_51

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_52

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_53

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_54

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_55

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
95.96	87.88

tb.dut.u_sm1_28

SCORE	COND
95.96	87.88

tb.dut.u_sm1_29

SCORE	COND
95.96	87.88

tb.dut.u_sm1_31

SCORE	COND
100.00	100.00

tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T11,T13
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T11,T13
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.97	90.91

tb.dut.u_sm1_33

SCORE	COND
96.97	90.91

tb.dut.u_sm1_34

SCORE	COND
96.97	90.91

tb.dut.u_sm1_43

SCORE	COND
96.97	90.91

tb.dut.u_sm1_44

SCORE	COND
96.97	90.91

tb.dut.u_sm1_45

SCORE	COND
96.97	90.91

tb.dut.u_sm1_46

SCORE	COND
96.97	90.91

tb.dut.u_sm1_47

SCORE	COND
96.97	90.91

tb.dut.u_sm1_48

SCORE	COND
96.97	90.91

tb.dut.u_sm1_49

SCORE	COND
96.97	90.91

tb.dut.u_sm1_50

SCORE	COND
96.97	90.91

tb.dut.u_sm1_51

SCORE	COND
96.97	90.91

tb.dut.u_sm1_52

SCORE	COND
96.97	90.91

tb.dut.u_sm1_53

SCORE	COND
96.97	90.91

tb.dut.u_sm1_54

SCORE	COND
96.97	90.91

tb.dut.u_sm1_55

SCORE	COND
96.97	90.91

tb.dut.u_sm1_56

SCORE	COND
96.97	90.91

tb.dut.u_sm1_36

SCORE	COND
96.97	90.91

tb.dut.u_sm1_38

SCORE	COND
96.97	90.91

tb.dut.u_sm1_40

SCORE	COND
96.97	90.91

tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_m1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	2147483647	21640673	0	0
gen_host_fifo[1].idInRange	2147483647	11956708	0	0
gen_host_fifo[2].idInRange	1762920812	3452394	0	0
maxM	21600	21600	0	0
rspIdInRange	2147483647	174338058	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21640673	0	0
T1	50400	326	0	0
T2	266808	700	0	0
T3	31008	347	0	0
T7	215088	733	0	0
T8	274224	567	0	0
T9	67608	276	0	0
T10	57288	304	0	0
T11	1029240	20213	0	0
T12	287592	1101	0	0
T13	67560	345	0	0
T14	0	65	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11956708	0	0
T1	50400	130	0	0
T2	266808	229	0	0
T3	31008	239	0	0
T7	215088	126	0	0
T8	274224	220	0	0
T9	67608	243	0	0
T10	57288	227	0	0
T11	1029240	18408	0	0
T12	287592	447	0	0
T13	67560	159	0	0
T14	0	121	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	1762920812	3452394	0	0
T1	8400	26	0	0
T2	44468	42	0	0
T3	5168	26	0	0
T7	35848	39	0	0
T8	45704	80	0	0
T9	11268	29	0	0
T10	9548	32	0	0
T11	171540	1880	0	0
T12	47932	118	0	0
T13	11260	33	0	0
T14	0	48	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	174338058	0	0
T1	50400	433	0	0
T2	266808	1869	0	0
T3	31008	506	0	0
T7	215088	1455	0	0
T8	274224	2528	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	21164	0	0
T12	287592	4444	0	0
T13	67560	500	0	0
T14	0	650	0	0

Line Coverage for Instance : tb.dut.u_sm1_28

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	1632469	0	0
gen_host_fifo[1].idInRange	440730203	396365	0	0
gen_host_fifo[2].idInRange	440730203	506883	0	0
maxM	900	900	0	0
rspIdInRange	440730203	21461622	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1632469	0	0
T1	2100	47	0	0
T2	11117	70	0	0
T3	1292	41	0	0
T7	8962	85	0	0
T8	11426	77	0	0
T9	2817	24	0	0
T10	2387	34	0	0
T11	42885	284	0	0
T12	11983	90	0	0
T13	2815	56	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	396365	0	0
T1	2100	5	0	0
T2	11117	9	0	0
T3	1292	9	0	0
T7	8962	3	0	0
T8	11426	3	0	0
T9	2817	3	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	11	0	0
T13	2815	5	0	0
T14	0	2	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	506883	0	0
T1	2100	3	0	0
T2	11117	7	0	0
T3	1292	6	0	0
T7	8962	5	0	0
T8	11426	11	0	0
T9	2817	12	0	0
T10	2387	10	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	9	0	0
T14	0	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	21461622	0	0
T1	2100	55	0	0
T2	11117	174	0	0
T3	1292	54	0	0
T7	8962	102	0	0
T8	11426	327	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	1700	0	0
T12	11983	699	0	0
T13	2815	70	0	0

Line Coverage for Instance : tb.dut.u_sm1_29

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_29

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T12,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	1794438	0	0
gen_host_fifo[1].idInRange	440730203	471507	0	0
gen_host_fifo[2].idInRange	440730203	588883	0	0
maxM	900	900	0	0
rspIdInRange	440730203	19875169	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1794438	0	0
T1	2100	52	0	0
T2	11117	77	0	0
T3	1292	45	0	0
T7	8962	45	0	0
T8	11426	54	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	394	0	0
T12	11983	89	0	0
T13	2815	65	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	471507	0	0
T1	2100	2	0	0
T2	11117	17	0	0
T3	1292	13	0	0
T7	8962	2	0	0
T8	11426	6	0	0
T9	2817	8	0	0
T10	2387	15	0	0
T11	42885	0	0	0
T12	11983	6	0	0
T13	2815	9	0	0
T14	0	11	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	588883	0	0
T1	2100	8	0	0
T2	11117	4	0	0
T3	1292	4	0	0
T7	8962	4	0	0
T8	11426	7	0	0
T9	2817	8	0	0
T10	2387	3	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	10	0	0
T14	0	23	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	19875169	0	0
T1	2100	53	0	0
T2	11117	191	0	0
T3	1292	50	0	0
T7	8962	105	0	0
T8	11426	335	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	1704	0	0
T12	11983	545	0	0
T13	2815	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_31

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T12,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	1833251	0	0
gen_host_fifo[1].idInRange	440730203	515405	0	0
gen_host_fifo[2].idInRange	440730203	610596	0	0
maxM	900	900	0	0
rspIdInRange	440730203	20644107	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1833251	0	0
T1	2100	54	0	0
T2	11117	58	0	0
T3	1292	41	0	0
T7	8962	101	0	0
T8	11426	53	0	0
T9	2817	35	0	0
T10	2387	37	0	0
T11	42885	362	0	0
T12	11983	89	0	0
T13	2815	41	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	515405	0	0
T1	2100	7	0	0
T2	11117	18	0	0
T3	1292	6	0	0
T7	8962	5	0	0
T8	11426	4	0	0
T9	2817	4	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	10	0	0
T13	2815	6	0	0
T14	0	3	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	610596	0	0
T1	2100	8	0	0
T2	11117	17	0	0
T3	1292	12	0	0
T7	8962	5	0	0
T8	11426	16	0	0
T9	2817	6	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	4	0	0
T13	2815	9	0	0
T14	0	17	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	20644107	0	0
T1	2100	57	0	0
T2	11117	169	0	0
T3	1292	46	0	0
T7	8962	172	0	0
T8	11426	334	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	1842	0	0
T12	11983	574	0	0
T13	2815	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_33

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_33

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	303025	0	0
gen_host_fifo[1].idInRange	440730203	379447	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4422546	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	303025	0	0
T1	2100	3	0	0
T2	11117	9	0	0
T3	1292	2	0	0
T7	8962	5	0	0
T8	11426	11	0	0
T9	2817	10	0	0
T10	2387	15	0	0
T11	42885	0	0	0
T12	11983	8	0	0
T13	2815	6	0	0
T14	0	4	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	379447	0	0
T1	2100	5	0	0
T2	11117	6	0	0
T3	1292	9	0	0
T7	8962	9	0	0
T8	11426	5	0	0
T9	2817	9	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	11	0	0
T13	2815	11	0	0
T14	0	3	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4422546	0	0
T1	2100	8	0	0
T2	11117	117	0	0
T3	1292	11	0	0
T7	8962	67	0	0
T8	11426	102	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	105	0	0
T13	2815	16	0	0
T14	0	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_34

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_34

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	288059	0	0
gen_host_fifo[1].idInRange	440730203	374215	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4942921	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	288059	0	0
T1	2100	5	0	0
T2	11117	4	0	0
T3	1292	5	0	0
T7	8962	11	0	0
T8	11426	2	0	0
T9	2817	7	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	7	0	0
T14	0	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	374215	0	0
T1	2100	3	0	0
T2	11117	5	0	0
T3	1292	7	0	0
T7	8962	2	0	0
T8	11426	8	0	0
T9	2817	4	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	15	0	0
T13	2815	7	0	0
T14	0	3	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4942921	0	0
T1	2100	8	0	0
T2	11117	55	0	0
T3	1292	12	0	0
T7	8962	97	0	0
T8	11426	32	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	118	0	0
T13	2815	14	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_36

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_36

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	685213	0	0
gen_host_fifo[1].idInRange	440730203	824011	0	0
maxM	900	900	0	0
rspIdInRange	440730203	5241894	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	685213	0	0
T1	2100	2	0	0
T2	11117	12	0	0
T3	1292	21	0	0
T7	8962	4	0	0
T8	11426	6	0	0
T9	2817	5	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	8	0	0
T13	2815	3	0	0
T14	0	7	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	824011	0	0
T1	2100	14	0	0
T2	11117	6	0	0
T3	1292	37	0	0
T7	8962	4	0	0
T8	11426	9	0	0
T9	2817	7	0	0
T10	2387	13	0	0
T11	42885	0	0	0
T12	11983	10	0	0
T13	2815	4	0	0
T14	0	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	5241894	0	0
T1	2100	10	0	0
T2	11117	52	0	0
T3	1292	12	0	0
T7	8962	36	0	0
T8	11426	43	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	81	0	0
T13	2815	7	0	0
T14	0	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_38

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_38

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	561594	0	0
gen_host_fifo[1].idInRange	440730203	663606	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4849224	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	561594	0	0
T1	2100	3	0	0
T2	11117	26	0	0
T3	1292	9	0	0
T7	8962	2	0	0
T8	11426	10	0	0
T9	2817	5	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	10	0	0
T13	2815	25	0	0
T14	0	3	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	663606	0	0
T1	2100	6	0	0
T2	11117	6	0	0
T3	1292	5	0	0
T7	8962	4	0	0
T8	11426	6	0	0
T9	2817	56	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	8	0	0
T14	0	6	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4849224	0	0
T1	2100	9	0	0
T2	11117	44	0	0
T3	1292	14	0	0
T7	8962	26	0	0
T8	11426	73	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	107	0	0
T13	2815	18	0	0
T14	0	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_40

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_40

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T11
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	596879	0	0
gen_host_fifo[1].idInRange	440730203	712745	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4517978	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	596879	0	0
T1	2100	10	0	0
T2	11117	10	0	0
T3	1292	12	0	0
T7	8962	5	0	0
T8	11426	17	0	0
T9	2817	7	0	0
T10	2387	3	0	0
T11	42885	6656	0	0
T12	11983	3	0	0
T13	2815	6	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	712745	0	0
T1	2100	3	0	0
T2	11117	21	0	0
T3	1292	16	0	0
T7	8962	4	0	0
T8	11426	36	0	0
T9	2817	7	0	0
T10	2387	33	0	0
T11	42885	6560	0	0
T12	11983	16	0	0
T13	2815	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4517978	0	0
T1	2100	9	0	0
T2	11117	71	0	0
T3	1292	16	0	0
T7	8962	43	0	0
T8	11426	101	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	2007	0	0
T12	11983	40	0	0
T13	2815	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_42

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T27,T29
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	648428	0	0
gen_host_fifo[1].idInRange	440730203	783473	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4863179	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	648428	0	0
T1	2100	6	0	0
T2	11117	4	0	0
T3	1292	16	0	0
T7	8962	5	0	0
T8	11426	7	0	0
T9	2817	3	0	0
T10	2387	13	0	0
T11	42885	0	0	0
T12	11983	8	0	0
T13	2815	7	0	0
T14	0	4	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	783473	0	0
T1	2100	17	0	0
T2	11117	10	0	0
T3	1292	7	0	0
T7	8962	4	0	0
T8	11426	1	0	0
T9	2817	32	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	9	0	0
T13	2815	4	0	0
T14	0	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4863179	0	0
T1	2100	13	0	0
T2	11117	41	0	0
T3	1292	16	0	0
T7	8962	49	0	0
T8	11426	54	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	57	0	0
T13	2815	11	0	0
T14	0	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_43

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_43

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T22,T29
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	284325	0	0
gen_host_fifo[1].idInRange	440730203	358737	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4846447	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	284325	0	0
T1	2100	10	0	0
T2	11117	5	0	0
T3	1292	9	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	8	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	12	0	0
T13	2815	10	0	0
T14	0	7	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	358737	0	0
T1	2100	2	0	0
T2	11117	3	0	0
T3	1292	20	0	0
T7	8962	12	0	0
T8	11426	9	0	0
T9	2817	4	0	0
T10	2387	2	0	0
T11	42885	0	0	0
T12	11983	12	0	0
T13	2815	6	0	0
T14	0	3	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4846447	0	0
T1	2100	10	0	0
T2	11117	62	0	0
T3	1292	29	0	0
T7	8962	42	0	0
T8	11426	81	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	81	0	0
T13	2815	15	0	0
T14	0	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_44

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_44

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T11,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	265082	0	0
gen_host_fifo[1].idInRange	440730203	345218	0	0
maxM	900	900	0	0
rspIdInRange	440730203	3742329	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	265082	0	0
T1	2100	4	0	0
T2	11117	4	0	0
T3	1292	8	0	0
T7	8962	9	0	0
T8	11426	4	0	0
T9	2817	8	0	0
T10	2387	11	0	0
T11	42885	2613	0	0
T12	11983	21	0	0
T13	2815	6	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	345218	0	0
T1	2100	2	0	0
T2	11117	5	0	0
T3	1292	10	0	0
T7	8962	9	0	0
T8	11426	9	0	0
T9	2817	6	0	0
T10	2387	2	0	0
T11	42885	2973	0	0
T12	11983	22	0	0
T13	2815	7	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	3742329	0	0
T1	2100	6	0	0
T2	11117	34	0	0
T3	1292	17	0	0
T7	8962	67	0	0
T8	11426	16	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	2251	0	0
T12	11983	140	0	0
T13	2815	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_45

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	271735	0	0
gen_host_fifo[1].idInRange	440730203	337122	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4362707	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	271735	0	0
T1	2100	6	0	0
T2	11117	6	0	0
T3	1292	10	0	0
T7	8962	5	0	0
T8	11426	13	0	0
T9	2817	5	0	0
T10	2387	10	0	0
T11	42885	0	0	0
T12	11983	8	0	0
T13	2815	5	0	0
T14	0	9	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	337122	0	0
T1	2100	4	0	0
T2	11117	15	0	0
T3	1292	8	0	0
T7	8962	9	0	0
T8	11426	7	0	0
T9	2817	11	0	0
T10	2387	5	0	0
T11	42885	0	0	0
T12	11983	6	0	0
T13	2815	4	0	0
T14	0	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4362707	0	0
T1	2100	10	0	0
T2	11117	75	0	0
T3	1292	17	0	0
T7	8962	46	0	0
T8	11426	90	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	104	0	0
T13	2815	9	0	0
T14	0	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_46

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_46

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T29,T30
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	272576	0	0
gen_host_fifo[1].idInRange	440730203	339700	0	0
maxM	900	900	0	0
rspIdInRange	440730203	5076769	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	272576	0	0
T1	2100	10	0	0
T2	11117	6	0	0
T3	1292	6	0	0
T7	8962	24	0	0
T8	11426	2	0	0
T9	2817	4	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	7	0	0
T13	2815	1	0	0
T14	0	3	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	339700	0	0
T1	2100	4	0	0
T2	11117	6	0	0
T3	1292	9	0	0
T7	8962	2	0	0
T8	11426	6	0	0
T9	2817	8	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	9	0	0
T13	2815	5	0	0
T14	0	7	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	5076769	0	0
T1	2100	13	0	0
T2	11117	50	0	0
T3	1292	15	0	0
T7	8962	50	0	0
T8	11426	21	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	82	0	0
T13	2815	6	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_47

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_47

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T27,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	292615	0	0
gen_host_fifo[1].idInRange	440730203	373615	0	0
maxM	900	900	0	0
rspIdInRange	440730203	5824229	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	292615	0	0
T1	2100	3	0	0
T2	11117	9	0	0
T3	1292	4	0	0
T7	8962	8	0	0
T8	11426	15	0	0
T9	2817	11	0	0
T10	2387	6	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	5	0	0
T14	0	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	373615	0	0
T1	2100	4	0	0
T2	11117	3	0	0
T3	1292	6	0	0
T7	8962	2	0	0
T8	11426	6	0	0
T9	2817	7	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	8	0	0
T14	0	6	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	5824229	0	0
T1	2100	7	0	0
T2	11117	78	0	0
T3	1292	10	0	0
T7	8962	71	0	0
T8	11426	46	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	106	0	0
T13	2815	13	0	0
T14	0	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_48

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_48

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T11,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	280078	0	0
gen_host_fifo[1].idInRange	440730203	373692	0	0
maxM	900	900	0	0
rspIdInRange	440730203	3716905	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	280078	0	0
T1	2100	4	0	0
T2	11117	6	0	0
T3	1292	4	0	0
T7	8962	3	0	0
T8	11426	12	0	0
T9	2817	13	0	0
T10	2387	4	0	0
T11	42885	2897	0	0
T12	11983	8	0	0
T13	2815	9	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	373692	0	0
T1	2100	5	0	0
T2	11117	3	0	0
T3	1292	6	0	0
T7	8962	3	0	0
T8	11426	7	0	0
T9	2817	6	0	0
T10	2387	10	0	0
T11	42885	3444	0	0
T12	11983	11	0	0
T13	2815	6	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	3716905	0	0
T1	2100	9	0	0
T2	11117	67	0	0
T3	1292	10	0	0
T7	8962	26	0	0
T8	11426	109	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	2456	0	0
T12	11983	88	0	0
T13	2815	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_49

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_49

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T26,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	287101	0	0
gen_host_fifo[1].idInRange	440730203	371638	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4313198	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	287101	0	0
T1	2100	11	0	0
T2	11117	2	0	0
T3	1292	5	0	0
T7	8962	5	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	4	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	7	0	0
T14	0	3	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	371638	0	0
T1	2100	7	0	0
T2	11117	5	0	0
T3	1292	4	0	0
T7	8962	8	0	0
T8	11426	3	0	0
T9	2817	9	0	0
T10	2387	4	0	0
T11	42885	0	0	0
T12	11983	13	0	0
T13	2815	7	0	0
T14	0	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4313198	0	0
T1	2100	16	0	0
T2	11117	14	0	0
T3	1292	9	0	0
T7	8962	25	0	0
T8	11426	39	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	107	0	0
T13	2815	13	0	0
T14	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_50

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_50

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	304458	0	0
gen_host_fifo[1].idInRange	440730203	385452	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4625321	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	304458	0	0
T1	2100	9	0	0
T2	11117	5	0	0
T3	1292	12	0	0
T7	8962	5	0	0
T8	11426	5	0	0
T9	2817	14	0	0
T10	2387	3	0	0
T11	42885	0	0	0
T12	11983	7	0	0
T13	2815	5	0	0
T14	0	5	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	385452	0	0
T1	2100	5	0	0
T2	11117	10	0	0
T3	1292	4	0	0
T7	8962	5	0	0
T8	11426	6	0	0
T9	2817	4	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	46	0	0
T13	2815	9	0	0
T14	0	32	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4625321	0	0
T1	2100	12	0	0
T2	11117	51	0	0
T3	1292	15	0	0
T7	8962	35	0	0
T8	11426	43	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	101	0	0
T13	2815	14	0	0
T14	0	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_51

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_51

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T27,T29
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	322469	0	0
gen_host_fifo[1].idInRange	440730203	395147	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4662027	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	322469	0	0
T1	2100	4	0	0
T2	11117	5	0	0
T3	1292	9	0	0
T7	8962	11	0	0
T8	11426	7	0	0
T9	2817	13	0	0
T10	2387	13	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	5	0	0
T14	0	4	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	395147	0	0
T1	2100	4	0	0
T2	11117	3	0	0
T3	1292	5	0	0
T7	8962	3	0	0
T8	11426	4	0	0
T9	2817	9	0	0
T10	2387	7	0	0
T11	42885	0	0	0
T12	11983	26	0	0
T13	2815	7	0	0
T14	0	2	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4662027	0	0
T1	2100	8	0	0
T2	11117	58	0	0
T3	1292	13	0	0
T7	8962	69	0	0
T8	11426	49	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	170	0	0
T13	2815	12	0	0
T14	0	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_52

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_52

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	295752	0	0
gen_host_fifo[1].idInRange	440730203	393494	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4332818	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	295752	0	0
T1	2100	7	0	0
T2	11117	2	0	0
T3	1292	13	0	0
T7	8962	3	0	0
T8	11426	10	0	0
T9	2817	7	0	0
T10	2387	3	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	6	0	0
T14	0	3	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	393494	0	0
T1	2100	7	0	0
T2	11117	2	0	0
T3	1292	10	0	0
T7	8962	4	0	0
T8	11426	13	0	0
T9	2817	3	0	0
T10	2387	9	0	0
T11	42885	0	0	0
T12	11983	41	0	0
T13	2815	6	0	0
T14	0	10	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4332818	0	0
T1	2100	13	0	0
T2	11117	31	0	0
T3	1292	20	0	0
T7	8962	36	0	0
T8	11426	67	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	115	0	0
T13	2815	12	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_53

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_53

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T20,T29
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	297074	0	0
gen_host_fifo[1].idInRange	440730203	381464	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4267111	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	297074	0	0
T1	2100	9	0	0
T2	11117	5	0	0
T3	1292	7	0	0
T7	8962	6	0	0
T8	11426	4	0	0
T9	2817	6	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	22	0	0
T13	2815	3	0	0
T14	0	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	381464	0	0
T1	2100	5	0	0
T2	11117	6	0	0
T3	1292	9	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	6	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	9	0	0
T13	2815	8	0	0
T14	0	4	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4267111	0	0
T1	2100	14	0	0
T2	11117	55	0	0
T3	1292	16	0	0
T7	8962	74	0	0
T8	11426	43	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	188	0	0
T13	2815	11	0	0
T14	0	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_54

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_54

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T12,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	308515	0	0
gen_host_fifo[1].idInRange	440730203	388413	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4673544	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	308515	0	0
T1	2100	9	0	0
T2	11117	10	0	0
T3	1292	13	0	0
T7	8962	4	0	0
T8	11426	2	0	0
T9	2817	8	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	31	0	0
T13	2815	7	0	0
T14	0	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	388413	0	0
T1	2100	3	0	0
T2	11117	43	0	0
T3	1292	14	0	0
T7	8962	4	0	0
T8	11426	4	0	0
T9	2817	8	0	0
T10	2387	6	0	0
T11	42885	0	0	0
T12	11983	32	0	0
T13	2815	9	0	0
T14	0	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4673544	0	0
T1	2100	12	0	0
T2	11117	57	0	0
T3	1292	25	0	0
T7	8962	24	0	0
T8	11426	36	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	123	0	0
T13	2815	16	0	0
T14	0	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_55

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_55

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T26,T27,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	294132	0	0
gen_host_fifo[1].idInRange	440730203	376365	0	0
maxM	900	900	0	0
rspIdInRange	440730203	5082067	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	294132	0	0
T1	2100	8	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	11	0	0
T8	11426	5	0	0
T9	2817	9	0	0
T10	2387	4	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	6	0	0
T14	0	5	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	376365	0	0
T1	2100	7	0	0
T2	11117	3	0	0
T3	1292	13	0	0
T7	8962	2	0	0
T8	11426	4	0	0
T9	2817	10	0	0
T10	2387	4	0	0
T11	42885	0	0	0
T12	11983	11	0	0
T13	2815	4	0	0
T14	0	4	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	5082067	0	0
T1	2100	15	0	0
T2	11117	66	0	0
T3	1292	22	0	0
T7	8962	26	0	0
T8	11426	45	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	85	0	0
T13	2815	10	0	0
T14	0	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_56

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	273150	0	0
gen_host_fifo[1].idInRange	440730203	351706	0	0
maxM	900	900	0	0
rspIdInRange	440730203	4411657	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	273150	0	0
T1	2100	4	0	0
T2	11117	7	0	0
T3	1292	11	0	0
T7	8962	7	0	0
T8	11426	7	0	0
T9	2817	8	0	0
T10	2387	5	0	0
T11	42885	2779	0	0
T12	11983	9	0	0
T13	2815	7	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	351706	0	0
T1	2100	4	0	0
T2	11117	4	0	0
T3	1292	8	0	0
T7	8962	3	0	0
T8	11426	6	0	0
T9	2817	15	0	0
T10	2387	6	0	0
T11	42885	3393	0	0
T12	11983	9	0	0
T13	2815	6	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4411657	0	0
T1	2100	8	0	0
T2	11117	50	0	0
T3	1292	17	0	0
T7	8962	33	0	0
T8	11426	85	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	2640	0	0
T12	11983	79	0	0
T13	2815	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_30

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T3,T9
1	1	0	Covered	T3,T11,T13
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T11,T13
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T11,T13
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	440730203	9248255	0	0
gen_host_fifo[1].idInRange	440730203	1664171	0	0
gen_host_fifo[2].idInRange	440730203	1746032	0	0
maxM	900	900	0	0
rspIdInRange	440730203	19582289	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	9248255	0	0
T1	2100	46	0	0
T2	11117	345	0	0
T3	1292	32	0	0
T7	8962	364	0	0
T8	11426	227	0	0
T9	2817	32	0	0
T10	2387	28	0	0
T11	42885	4228	0	0
T12	11983	547	0	0
T13	2815	47	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1664171	0	0
T1	2100	5	0	0
T2	11117	20	0	0
T3	1292	4	0	0
T7	8962	18	0	0
T8	11426	49	0	0
T9	2817	7	0	0
T10	2387	11	0	0
T11	42885	2038	0	0
T12	11983	75	0	0
T13	2815	8	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1746032	0	0
T1	2100	7	0	0
T2	11117	14	0	0
T3	1292	4	0	0
T7	8962	25	0	0
T8	11426	46	0	0
T9	2817	3	0	0
T10	2387	5	0	0
T11	42885	1880	0	0
T12	11983	79	0	0
T13	2815	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	19582289	0	0
T1	2100	58	0	0
T2	11117	207	0	0
T3	1292	40	0	0
T7	8962	134	0	0
T8	11426	357	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	6564	0	0
T12	11983	549	0	0
T13	2815	60	0	0