Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7923524	0	0
GntImpliesValid_A	2147483647	7923524	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7923524	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	463204196	0	0
ReadyAndValidImplyGrant_A	2147483647	7923524	0	0
ReqAndReadyImplyGrant_A	2147483647	7923524	0	0
ReqImpliesValid_A	2147483647	32016374	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51522	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7923524	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50400	49008	0	0
T2	266808	265368	0	0
T3	31008	30024	0	0
T7	215088	214488	0	0
T8	274224	273096	0	0
T9	67608	65688	0	0
T10	57288	56736	0	0
T11	1029240	1027368	0	0
T12	287592	286872	0	0
T13	67560	66072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7923524	0	0
T1	50400	433	0	0
T2	266808	445	0	0
T3	31008	506	0	0
T7	215088	395	0	0
T8	274224	446	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	3546	0	0
T12	287592	789	0	0
T13	67560	500	0	0
T14	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7923524	0	0
T1	50400	433	0	0
T2	266808	445	0	0
T3	31008	506	0	0
T7	215088	395	0	0
T8	274224	446	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	3546	0	0
T12	287592	789	0	0
T13	67560	500	0	0
T14	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50400	49008	0	0
T2	266808	265368	0	0
T3	31008	30024	0	0
T7	215088	214488	0	0
T8	274224	273096	0	0
T9	67608	65688	0	0
T10	57288	56736	0	0
T11	1029240	1027368	0	0
T12	287592	286872	0	0
T13	67560	66072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50400	49008	0	0
T2	266808	265368	0	0
T3	31008	30024	0	0
T7	215088	214488	0	0
T8	274224	273096	0	0
T9	67608	65688	0	0
T10	57288	56736	0	0
T11	1029240	1027368	0	0
T12	287592	286872	0	0
T13	67560	66072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7923524	0	0
T1	50400	433	0	0
T2	266808	445	0	0
T3	31008	506	0	0
T7	215088	395	0	0
T8	274224	446	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	3546	0	0
T12	287592	789	0	0
T13	67560	500	0	0
T14	0	146	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	463204196	0	0
T1	50400	520	0	0
T2	266808	12962	0	0
T3	31008	730	0	0
T7	215088	10341	0	0
T8	274224	13251	0	0
T9	67608	897	0	0
T10	57288	768	0	0
T11	1029240	41265	0	0
T12	287592	15889	0	0
T13	67560	844	0	0
T14	0	410	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7923524	0	0
T1	50400	433	0	0
T2	266808	445	0	0
T3	31008	506	0	0
T7	215088	395	0	0
T8	274224	446	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	3546	0	0
T12	287592	789	0	0
T13	67560	500	0	0
T14	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7923524	0	0
T1	50400	433	0	0
T2	266808	445	0	0
T3	31008	506	0	0
T7	215088	395	0	0
T8	274224	446	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	3546	0	0
T12	287592	789	0	0
T13	67560	500	0	0
T14	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32016374	0	0
T1	50400	482	0	0
T2	266808	971	0	0
T3	31008	603	0	0
T7	215088	898	0	0
T8	274224	867	0	0
T9	67608	548	0	0
T10	57288	563	0	0
T11	1029240	28433	0	0
T12	287592	1648	0	0
T13	67560	537	0	0
T14	0	170	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51522	0	21600
T11	42885	52	0	1
T12	11983	0	0	1
T13	2815	0	0	1
T14	8775	0	0	1
T15	9260	9	0	2
T16	34106	12	0	2
T17	6316	9	0	2
T18	19764	28	0	2
T19	14699	32	0	1
T20	149865	109	0	1
T21	5967	7	0	1
T22	19219	7	0	1
T23	0	10	0	0
T24	0	6	0	0
T25	0	6	0	0
T26	17347	0	0	1
T27	41970	0	0	2
T28	261236	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50400	49008	0	0
T2	266808	265368	0	0
T3	31008	30024	0	0
T7	215088	214488	0	0
T8	274224	273096	0	0
T9	67608	65688	0	0
T10	57288	56736	0	0
T11	1029240	1027368	0	0
T12	287592	286872	0	0
T13	67560	66072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7923524	0	0
T1	50400	433	0	0
T2	266808	445	0	0
T3	31008	506	0	0
T7	215088	395	0	0
T8	274224	446	0	0
T9	67608	462	0	0
T10	57288	488	0	0
T11	1029240	3546	0	0
T12	287592	789	0	0
T13	67560	500	0	0
T14	0	146	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	874124	0	0
GntImpliesValid_A	440730203	874124	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	874124	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	11090965	0	0
ReadyAndValidImplyGrant_A	440730203	874124	0	0
ReqAndReadyImplyGrant_A	440730203	874124	0	0
ReqImpliesValid_A	440730203	2366136	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	874124	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	874124	0	0
T1	2100	53	0	0
T2	11117	62	0	0
T3	1292	50	0	0
T7	8962	42	0	0
T8	11426	48	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	229	0	0
T12	11983	86	0	0
T13	2815	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	874124	0	0
T1	2100	53	0	0
T2	11117	62	0	0
T3	1292	50	0	0
T7	8962	42	0	0
T8	11426	48	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	229	0	0
T12	11983	86	0	0
T13	2815	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	874124	0	0
T1	2100	53	0	0
T2	11117	62	0	0
T3	1292	50	0	0
T7	8962	42	0	0
T8	11426	48	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	229	0	0
T12	11983	86	0	0
T13	2815	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	11090965	0	0
T1	2100	45	0	0
T2	11117	455	0	0
T3	1292	39	0	0
T7	8962	344	0	0
T8	11426	339	0	0
T9	2817	30	0	0
T10	2387	28	0	0
T11	42885	1688	0	0
T12	11983	629	0	0
T13	2815	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	874124	0	0
T1	2100	53	0	0
T2	11117	62	0	0
T3	1292	50	0	0
T7	8962	42	0	0
T8	11426	48	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	229	0	0
T12	11983	86	0	0
T13	2815	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	874124	0	0
T1	2100	53	0	0
T2	11117	62	0	0
T3	1292	50	0	0
T7	8962	42	0	0
T8	11426	48	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	229	0	0
T12	11983	86	0	0
T13	2815	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2366136	0	0
T1	2100	62	0	0
T2	11117	98	0	0
T3	1292	62	0	0
T7	8962	51	0	0
T8	11426	67	0	0
T9	2817	35	0	0
T10	2387	39	0	0
T11	42885	394	0	0
T12	11983	111	0	0
T13	2815	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	874124	0	0
T1	2100	53	0	0
T2	11117	62	0	0
T3	1292	50	0	0
T7	8962	42	0	0
T8	11426	48	0	0
T9	2817	32	0	0
T10	2387	33	0	0
T11	42885	229	0	0
T12	11983	86	0	0
T13	2815	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	896737	0	0
GntImpliesValid_A	440730203	896737	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	896737	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	11211437	0	0
ReadyAndValidImplyGrant_A	440730203	896737	0	0
ReqAndReadyImplyGrant_A	440730203	896737	0	0
ReqImpliesValid_A	440730203	2422738	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	896737	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	896737	0	0
T1	2100	57	0	0
T2	11117	54	0	0
T3	1292	46	0	0
T7	8962	63	0	0
T8	11426	53	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	229	0	0
T12	11983	80	0	0
T13	2815	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	896737	0	0
T1	2100	57	0	0
T2	11117	54	0	0
T3	1292	46	0	0
T7	8962	63	0	0
T8	11426	53	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	229	0	0
T12	11983	80	0	0
T13	2815	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	896737	0	0
T1	2100	57	0	0
T2	11117	54	0	0
T3	1292	46	0	0
T7	8962	63	0	0
T8	11426	53	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	229	0	0
T12	11983	80	0	0
T13	2815	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	11211437	0	0
T1	2100	46	0	0
T2	11117	412	0	0
T3	1292	36	0	0
T7	8962	519	0	0
T8	11426	422	0	0
T9	2817	30	0	0
T10	2387	42	0	0
T11	42885	1874	0	0
T12	11983	598	0	0
T13	2815	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	896737	0	0
T1	2100	57	0	0
T2	11117	54	0	0
T3	1292	46	0	0
T7	8962	63	0	0
T8	11426	53	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	229	0	0
T12	11983	80	0	0
T13	2815	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	896737	0	0
T1	2100	57	0	0
T2	11117	54	0	0
T3	1292	46	0	0
T7	8962	63	0	0
T8	11426	53	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	229	0	0
T12	11983	80	0	0
T13	2815	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2422738	0	0
T1	2100	69	0	0
T2	11117	93	0	0
T3	1292	57	0	0
T7	8962	111	0	0
T8	11426	73	0	0
T9	2817	45	0	0
T10	2387	59	0	0
T11	42885	362	0	0
T12	11983	103	0	0
T13	2815	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	896737	0	0
T1	2100	57	0	0
T2	11117	54	0	0
T3	1292	46	0	0
T7	8962	63	0	0
T8	11426	53	0	0
T9	2817	37	0	0
T10	2387	50	0	0
T11	42885	229	0	0
T12	11983	80	0	0
T13	2815	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T9 T7 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T7,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	223104	0	0
GntImpliesValid_A	440730203	223104	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	223104	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2768514	0	0
ReadyAndValidImplyGrant_A	440730203	223104	0	0
ReqAndReadyImplyGrant_A	440730203	223104	0	0
ReqImpliesValid_A	440730203	564197	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	223104	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223104	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	13	0	0
T8	11426	16	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	16	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223104	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	13	0	0
T8	11426	16	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	16	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223104	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	13	0	0
T8	11426	16	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	16	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2768514	0	0
T1	2100	9	0	0
T2	11117	76	0	0
T3	1292	12	0	0
T7	8962	81	0	0
T8	11426	115	0	0
T9	2817	16	0	0
T10	2387	21	0	0
T11	42885	1	0	0
T12	11983	131	0	0
T13	2815	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223104	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	13	0	0
T8	11426	16	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	16	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223104	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	13	0	0
T8	11426	16	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	16	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	564197	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	14	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	24	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	17	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223104	0	0
T1	2100	8	0	0
T2	11117	15	0	0
T3	1292	11	0	0
T7	8962	13	0	0
T8	11426	16	0	0
T9	2817	17	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	16	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T9 T7 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T7,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	226704	0	0
GntImpliesValid_A	440730203	226704	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	226704	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2788721	0	0
ReadyAndValidImplyGrant_A	440730203	226704	0	0
ReqAndReadyImplyGrant_A	440730203	226704	0	0
ReqImpliesValid_A	440730203	555226	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	226704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	226704	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	12	0	0
T8	11426	10	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	226704	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	12	0	0
T8	11426	10	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	226704	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	12	0	0
T8	11426	10	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2788721	0	0
T1	2100	9	0	0
T2	11117	79	0	0
T3	1292	13	0	0
T7	8962	102	0	0
T8	11426	38	0	0
T9	2817	10	0	0
T10	2387	19	0	0
T11	42885	1	0	0
T12	11983	161	0	0
T13	2815	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	226704	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	12	0	0
T8	11426	10	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	226704	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	12	0	0
T8	11426	10	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	555226	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	13	0	0
T8	11426	10	0	0
T9	2817	11	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	38	0	0
T13	2815	14	0	0
T14	0	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	226704	0	0
T1	2100	8	0	0
T2	11117	9	0	0
T3	1292	12	0	0
T7	8962	12	0	0
T8	11426	10	0	0
T9	2817	10	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	215993	0	0
GntImpliesValid_A	440730203	215993	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	215993	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	4337771	0	0
ReadyAndValidImplyGrant_A	440730203	215993	0	0
ReqAndReadyImplyGrant_A	440730203	215993	0	0
ReqImpliesValid_A	440730203	1119804	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	215993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215993	0	0
T1	2100	10	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	7	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215993	0	0
T1	2100	10	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	7	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215993	0	0
T1	2100	10	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	7	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4337771	0	0
T1	2100	55	0	0
T2	11117	223	0	0
T3	1292	103	0	0
T7	8962	41	0	0
T8	11426	221	0	0
T9	2817	73	0	0
T10	2387	58	0	0
T11	42885	0	0	0
T12	11983	503	0	0
T13	2815	82	0	0
T14	0	114	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215993	0	0
T1	2100	10	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	7	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215993	0	0
T1	2100	10	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	7	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1119804	0	0
T1	2100	16	0	0
T2	11117	18	0	0
T3	1292	55	0	0
T7	8962	8	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	34	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215993	0	0
T1	2100	10	0	0
T2	11117	13	0	0
T3	1292	12	0	0
T7	8962	7	0	0
T8	11426	15	0	0
T9	2817	12	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	18	0	0
T13	2815	7	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T9,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	215889	0	0
GntImpliesValid_A	440730203	215889	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	215889	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	4389702	0	0
ReadyAndValidImplyGrant_A	440730203	215889	0	0
ReqAndReadyImplyGrant_A	440730203	215889	0	0
ReqImpliesValid_A	440730203	938914	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	215889	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215889	0	0
T1	2100	9	0	0
T2	11117	12	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	18	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215889	0	0
T1	2100	9	0	0
T2	11117	12	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	18	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215889	0	0
T1	2100	9	0	0
T2	11117	12	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	18	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4389702	0	0
T1	2100	66	0	0
T2	11117	296	0	0
T3	1292	81	0	0
T7	8962	53	0	0
T8	11426	163	0	0
T9	2817	349	0	0
T10	2387	191	0	0
T11	42885	0	0	0
T12	11983	122	0	0
T13	2815	125	0	0
T14	0	102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215889	0	0
T1	2100	9	0	0
T2	11117	12	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	18	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215889	0	0
T1	2100	9	0	0
T2	11117	12	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	18	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	938914	0	0
T1	2100	9	0	0
T2	11117	32	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	61	0	0
T10	2387	29	0	0
T11	42885	0	0	0
T12	11983	29	0	0
T13	2815	33	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215889	0	0
T1	2100	9	0	0
T2	11117	12	0	0
T3	1292	14	0	0
T7	8962	6	0	0
T8	11426	16	0	0
T9	2817	19	0	0
T10	2387	21	0	0
T11	42885	0	0	0
T12	11983	19	0	0
T13	2815	18	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	208579	0	0
GntImpliesValid_A	440730203	208579	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	208579	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	4321526	0	0
ReadyAndValidImplyGrant_A	440730203	208579	0	0
ReqAndReadyImplyGrant_A	440730203	208579	0	0
ReqImpliesValid_A	440730203	992562	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	208579	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	208579	0	0
T1	2100	9	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	451	0	0
T12	11983	13	0	0
T13	2815	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	208579	0	0
T1	2100	9	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	451	0	0
T12	11983	13	0	0
T13	2815	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	208579	0	0
T1	2100	9	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	451	0	0
T12	11983	13	0	0
T13	2815	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4321526	0	0
T1	2100	46	0	0
T2	11117	175	0	0
T3	1292	119	0	0
T7	8962	56	0	0
T8	11426	237	0	0
T9	2817	87	0	0
T10	2387	102	0	0
T11	42885	1880	0	0
T12	11983	116	0	0
T13	2815	196	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	208579	0	0
T1	2100	9	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	451	0	0
T12	11983	13	0	0
T13	2815	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	208579	0	0
T1	2100	9	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	451	0	0
T12	11983	13	0	0
T13	2815	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	992562	0	0
T1	2100	13	0	0
T2	11117	31	0	0
T3	1292	28	0	0
T7	8962	9	0	0
T8	11426	53	0	0
T9	2817	14	0	0
T10	2387	36	0	0
T11	42885	8791	0	0
T12	11983	19	0	0
T13	2815	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	208579	0	0
T1	2100	9	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	14	0	0
T10	2387	14	0	0
T11	42885	451	0	0
T12	11983	13	0	0
T13	2815	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	215064	0	0
GntImpliesValid_A	440730203	215064	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	215064	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	4553928	0	0
ReadyAndValidImplyGrant_A	440730203	215064	0	0
ReqAndReadyImplyGrant_A	440730203	215064	0	0
ReqImpliesValid_A	440730203	1081670	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	215064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215064	0	0
T1	2100	13	0	0
T2	11117	10	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215064	0	0
T1	2100	13	0	0
T2	11117	10	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215064	0	0
T1	2100	13	0	0
T2	11117	10	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	4553928	0	0
T1	2100	83	0	0
T2	11117	85	0	0
T3	1292	88	0	0
T7	8962	88	0	0
T8	11426	85	0	0
T9	2817	71	0	0
T10	2387	96	0	0
T11	42885	0	0	0
T12	11983	155	0	0
T13	2815	120	0	0
T14	0	194	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215064	0	0
T1	2100	13	0	0
T2	11117	10	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215064	0	0
T1	2100	13	0	0
T2	11117	10	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	1081670	0	0
T1	2100	23	0	0
T2	11117	14	0	0
T3	1292	23	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	35	0	0
T10	2387	22	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215064	0	0
T1	2100	13	0	0
T2	11117	10	0	0
T3	1292	16	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	15	0	0
T10	2387	16	0	0
T11	42885	0	0	0
T12	11983	17	0	0
T13	2815	11	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	217239	0	0
GntImpliesValid_A	440730203	217239	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	217239	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2787029	0	0
ReadyAndValidImplyGrant_A	440730203	217239	0	0
ReqAndReadyImplyGrant_A	440730203	217239	0	0
ReqImpliesValid_A	440730203	537643	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	217239	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	217239	0	0
T1	2100	10	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	13	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	21	0	0
T13	2815	15	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	217239	0	0
T1	2100	10	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	13	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	21	0	0
T13	2815	15	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	217239	0	0
T1	2100	10	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	13	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	21	0	0
T13	2815	15	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2787029	0	0
T1	2100	9	0	0
T2	11117	53	0	0
T3	1292	30	0	0
T7	8962	113	0	0
T8	11426	168	0	0
T9	2817	13	0	0
T10	2387	12	0	0
T11	42885	1	0	0
T12	11983	165	0	0
T13	2815	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	217239	0	0
T1	2100	10	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	13	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	21	0	0
T13	2815	15	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	217239	0	0
T1	2100	10	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	13	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	21	0	0
T13	2815	15	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	537643	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	17	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	16	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	217239	0	0
T1	2100	10	0	0
T2	11117	8	0	0
T3	1292	29	0	0
T7	8962	13	0	0
T8	11426	18	0	0
T9	2817	12	0	0
T10	2387	11	0	0
T11	42885	0	0	0
T12	11983	21	0	0
T13	2815	15	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	207928	0	0
GntImpliesValid_A	440730203	207928	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	207928	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2758423	0	0
ReadyAndValidImplyGrant_A	440730203	207928	0	0
ReqAndReadyImplyGrant_A	440730203	207928	0	0
ReqImpliesValid_A	440730203	513013	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	207928	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	207928	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	17	0	0
T7	8962	15	0	0
T8	11426	6	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	437	0	0
T12	11983	28	0	0
T13	2815	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	207928	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	17	0	0
T7	8962	15	0	0
T8	11426	6	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	437	0	0
T12	11983	28	0	0
T13	2815	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	207928	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	17	0	0
T7	8962	15	0	0
T8	11426	6	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	437	0	0
T12	11983	28	0	0
T13	2815	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2758423	0	0
T1	2100	7	0	0
T2	11117	55	0	0
T3	1292	17	0	0
T7	8962	131	0	0
T8	11426	55	0	0
T9	2817	15	0	0
T10	2387	14	0	0
T11	42885	1232	0	0
T12	11983	207	0	0
T13	2815	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	207928	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	17	0	0
T7	8962	15	0	0
T8	11426	6	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	437	0	0
T12	11983	28	0	0
T13	2815	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	207928	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	17	0	0
T7	8962	15	0	0
T8	11426	6	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	437	0	0
T12	11983	28	0	0
T13	2815	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	513013	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	18	0	0
T7	8962	18	0	0
T8	11426	13	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	3873	0	0
T12	11983	43	0	0
T13	2815	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	207928	0	0
T1	2100	6	0	0
T2	11117	9	0	0
T3	1292	17	0	0
T7	8962	15	0	0
T8	11426	6	0	0
T9	2817	14	0	0
T10	2387	13	0	0
T11	42885	437	0	0
T12	11983	28	0	0
T13	2815	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	218177	0	0
GntImpliesValid_A	440730203	218177	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	218177	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2794462	0	0
ReadyAndValidImplyGrant_A	440730203	218177	0	0
ReqAndReadyImplyGrant_A	440730203	218177	0	0
ReqImpliesValid_A	440730203	513797	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	218177	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218177	0	0
T1	2100	10	0	0
T2	11117	14	0	0
T3	1292	17	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218177	0	0
T1	2100	10	0	0
T2	11117	14	0	0
T3	1292	17	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218177	0	0
T1	2100	10	0	0
T2	11117	14	0	0
T3	1292	17	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2794462	0	0
T1	2100	11	0	0
T2	11117	81	0	0
T3	1292	17	0	0
T7	8962	59	0	0
T8	11426	110	0	0
T9	2817	17	0	0
T10	2387	14	0	0
T11	42885	1	0	0
T12	11983	93	0	0
T13	2815	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218177	0	0
T1	2100	10	0	0
T2	11117	14	0	0
T3	1292	17	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218177	0	0
T1	2100	10	0	0
T2	11117	14	0	0
T3	1292	17	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	513797	0	0
T1	2100	10	0	0
T2	11117	21	0	0
T3	1292	18	0	0
T7	8962	14	0	0
T8	11426	20	0	0
T9	2817	16	0	0
T10	2387	15	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218177	0	0
T1	2100	10	0	0
T2	11117	14	0	0
T3	1292	17	0	0
T7	8962	9	0	0
T8	11426	15	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	14	0	0
T13	2815	9	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T15 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T15
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T15

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T15
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	218403	0	0
GntImpliesValid_A	440730203	218403	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	218403	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2732852	0	0
ReadyAndValidImplyGrant_A	440730203	218403	0	0
ReqAndReadyImplyGrant_A	440730203	218403	0	0
ReqImpliesValid_A	440730203	515801	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	218403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218403	0	0
T1	2100	13	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218403	0	0
T1	2100	13	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218403	0	0
T1	2100	13	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2732852	0	0
T1	2100	13	0	0
T2	11117	69	0	0
T3	1292	16	0	0
T7	8962	51	0	0
T8	11426	57	0	0
T9	2817	13	0	0
T10	2387	19	0	0
T11	42885	1	0	0
T12	11983	133	0	0
T13	2815	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218403	0	0
T1	2100	13	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218403	0	0
T1	2100	13	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	515801	0	0
T1	2100	14	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	26	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	218403	0	0
T1	2100	13	0	0
T2	11117	12	0	0
T3	1292	15	0	0
T7	8962	9	0	0
T8	11426	8	0	0
T9	2817	12	0	0
T10	2387	18	0	0
T11	42885	0	0	0
T12	11983	16	0	0
T13	2815	6	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T12 T27 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T27
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T12,T27

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T12,T27
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	225019	0	0
GntImpliesValid_A	440730203	225019	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	225019	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2828144	0	0
ReadyAndValidImplyGrant_A	440730203	225019	0	0
ReqAndReadyImplyGrant_A	440730203	225019	0	0
ReqImpliesValid_A	440730203	555645	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	225019	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	225019	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	10	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	13	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	225019	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	10	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	13	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	225019	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	10	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	13	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2828144	0	0
T1	2100	8	0	0
T2	11117	87	0	0
T3	1292	11	0	0
T7	8962	51	0	0
T8	11426	63	0	0
T9	2817	19	0	0
T10	2387	18	0	0
T11	42885	1	0	0
T12	11983	217	0	0
T13	2815	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	225019	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	10	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	13	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	225019	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	10	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	13	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	555645	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	21	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	41	0	0
T13	2815	13	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	225019	0	0
T1	2100	7	0	0
T2	11117	12	0	0
T3	1292	10	0	0
T7	8962	10	0	0
T8	11426	10	0	0
T9	2817	18	0	0
T10	2387	17	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	13	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T9 T11 T15 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T15
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T15

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T11,T15
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	219507	0	0
GntImpliesValid_A	440730203	219507	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	219507	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2756139	0	0
ReadyAndValidImplyGrant_A	440730203	219507	0	0
ReqAndReadyImplyGrant_A	440730203	219507	0	0
ReqImpliesValid_A	440730203	550029	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	219507	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219507	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	491	0	0
T12	11983	19	0	0
T13	2815	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219507	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	491	0	0
T12	11983	19	0	0
T13	2815	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219507	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	491	0	0
T12	11983	19	0	0
T13	2815	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2756139	0	0
T1	2100	10	0	0
T2	11117	86	0	0
T3	1292	11	0	0
T7	8962	34	0	0
T8	11426	110	0	0
T9	2817	18	0	0
T10	2387	15	0	0
T11	42885	1111	0	0
T12	11983	114	0	0
T13	2815	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219507	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	491	0	0
T12	11983	19	0	0
T13	2815	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219507	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	491	0	0
T12	11983	19	0	0
T13	2815	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	550029	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	19	0	0
T10	2387	14	0	0
T11	42885	4277	0	0
T12	11983	19	0	0
T13	2815	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219507	0	0
T1	2100	9	0	0
T2	11117	9	0	0
T3	1292	10	0	0
T7	8962	6	0	0
T8	11426	19	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	491	0	0
T12	11983	19	0	0
T13	2815	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T9 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	219455	0	0
GntImpliesValid_A	440730203	219455	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	219455	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2807615	0	0
ReadyAndValidImplyGrant_A	440730203	219455	0	0
ReqAndReadyImplyGrant_A	440730203	219455	0	0
ReqImpliesValid_A	440730203	549117	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	219455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219455	0	0
T1	2100	16	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	8	0	0
T8	11426	10	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	13	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219455	0	0
T1	2100	16	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	8	0	0
T8	11426	10	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	13	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219455	0	0
T1	2100	16	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	8	0	0
T8	11426	10	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	13	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2807615	0	0
T1	2100	15	0	0
T2	11117	70	0	0
T3	1292	10	0	0
T7	8962	59	0	0
T8	11426	44	0	0
T9	2817	21	0	0
T10	2387	9	0	0
T11	42885	1	0	0
T12	11983	214	0	0
T13	2815	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219455	0	0
T1	2100	16	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	8	0	0
T8	11426	10	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	13	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219455	0	0
T1	2100	16	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	8	0	0
T8	11426	10	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	13	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	549117	0	0
T1	2100	18	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	13	0	0
T8	11426	11	0	0
T9	2817	24	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	14	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	219455	0	0
T1	2100	16	0	0
T2	11117	7	0	0
T3	1292	9	0	0
T7	8962	8	0	0
T8	11426	10	0	0
T9	2817	22	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	24	0	0
T13	2815	13	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	220716	0	0
GntImpliesValid_A	440730203	220716	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	220716	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2787730	0	0
ReadyAndValidImplyGrant_A	440730203	220716	0	0
ReqAndReadyImplyGrant_A	440730203	220716	0	0
ReqImpliesValid_A	440730203	569482	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	220716	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	220716	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	15	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	220716	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	15	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	220716	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	15	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2787730	0	0
T1	2100	11	0	0
T2	11117	53	0	0
T3	1292	15	0	0
T7	8962	101	0	0
T8	11426	104	0	0
T9	2817	15	0	0
T10	2387	15	0	0
T11	42885	1	0	0
T12	11983	181	0	0
T13	2815	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	220716	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	15	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	220716	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	15	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	569482	0	0
T1	2100	14	0	0
T2	11117	15	0	0
T3	1292	16	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	18	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	53	0	0
T13	2815	14	0	0
T14	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	220716	0	0
T1	2100	12	0	0
T2	11117	8	0	0
T3	1292	15	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	14	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	242950	0	0
GntImpliesValid_A	440730203	242950	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	242950	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2824704	0	0
ReadyAndValidImplyGrant_A	440730203	242950	0	0
ReqAndReadyImplyGrant_A	440730203	242950	0	0
ReqImpliesValid_A	440730203	592386	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	242950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	242950	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	13	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	12	0	0
T14	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	242950	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	13	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	12	0	0
T14	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	242950	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	13	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	12	0	0
T14	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2824704	0	0
T1	2100	9	0	0
T2	11117	73	0	0
T3	1292	13	0	0
T7	8962	78	0	0
T8	11426	90	0	0
T9	2817	17	0	0
T10	2387	19	0	0
T11	42885	1	0	0
T12	11983	209	0	0
T13	2815	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	242950	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	13	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	12	0	0
T14	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	242950	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	13	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	12	0	0
T14	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	592386	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	14	0	0
T7	8962	14	0	0
T8	11426	11	0	0
T9	2817	22	0	0
T10	2387	20	0	0
T11	42885	0	0	0
T12	11983	42	0	0
T13	2815	12	0	0
T14	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	242950	0	0
T1	2100	8	0	0
T2	11117	8	0	0
T3	1292	13	0	0
T7	8962	10	0	0
T8	11426	11	0	0
T9	2817	19	0	0
T10	2387	19	0	0
T11	42885	0	0	0
T12	11983	30	0	0
T13	2815	12	0	0
T14	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	222432	0	0
GntImpliesValid_A	440730203	222432	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	222432	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2774203	0	0
ReadyAndValidImplyGrant_A	440730203	222432	0	0
ReqAndReadyImplyGrant_A	440730203	222432	0	0
ReqImpliesValid_A	440730203	573814	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	222432	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	222432	0	0
T1	2100	13	0	0
T2	11117	4	0	0
T3	1292	20	0	0
T7	8962	7	0	0
T8	11426	16	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	12	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	222432	0	0
T1	2100	13	0	0
T2	11117	4	0	0
T3	1292	20	0	0
T7	8962	7	0	0
T8	11426	16	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	12	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	222432	0	0
T1	2100	13	0	0
T2	11117	4	0	0
T3	1292	20	0	0
T7	8962	7	0	0
T8	11426	16	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	12	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2774203	0	0
T1	2100	13	0	0
T2	11117	38	0	0
T3	1292	18	0	0
T7	8962	74	0	0
T8	11426	84	0	0
T9	2817	11	0	0
T10	2387	13	0	0
T11	42885	1	0	0
T12	11983	233	0	0
T13	2815	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	222432	0	0
T1	2100	13	0	0
T2	11117	4	0	0
T3	1292	20	0	0
T7	8962	7	0	0
T8	11426	16	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	12	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	222432	0	0
T1	2100	13	0	0
T2	11117	4	0	0
T3	1292	20	0	0
T7	8962	7	0	0
T8	11426	16	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	12	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	573814	0	0
T1	2100	14	0	0
T2	11117	4	0	0
T3	1292	23	0	0
T7	8962	7	0	0
T8	11426	23	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	69	0	0
T13	2815	12	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	222432	0	0
T1	2100	13	0	0
T2	11117	4	0	0
T3	1292	20	0	0
T7	8962	7	0	0
T8	11426	16	0	0
T9	2817	10	0	0
T10	2387	12	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	12	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T10 T12 T15 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T12,T15
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T12,T15

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T12,T15
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	214825	0	0
GntImpliesValid_A	440730203	214825	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	214825	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2791804	0	0
ReadyAndValidImplyGrant_A	440730203	214825	0	0
ReqAndReadyImplyGrant_A	440730203	214825	0	0
ReqImpliesValid_A	440730203	561479	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	214825	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	214825	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	11	0	0
T14	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	214825	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	11	0	0
T14	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	214825	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	11	0	0
T14	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2791804	0	0
T1	2100	15	0	0
T2	11117	77	0	0
T3	1292	17	0	0
T7	8962	77	0	0
T8	11426	104	0	0
T9	2817	13	0	0
T10	2387	25	0	0
T11	42885	1	0	0
T12	11983	223	0	0
T13	2815	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	214825	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	11	0	0
T14	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	214825	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	11	0	0
T14	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	561479	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	28	0	0
T11	42885	0	0	0
T12	11983	31	0	0
T13	2815	11	0	0
T14	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	214825	0	0
T1	2100	14	0	0
T2	11117	11	0	0
T3	1292	16	0	0
T7	8962	11	0	0
T8	11426	13	0	0
T9	2817	12	0	0
T10	2387	26	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	11	0	0
T14	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	223983	0	0
GntImpliesValid_A	440730203	223983	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	223983	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2814384	0	0
ReadyAndValidImplyGrant_A	440730203	223983	0	0
ReqAndReadyImplyGrant_A	440730203	223983	0	0
ReqImpliesValid_A	440730203	579813	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	223983	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223983	0	0
T1	2100	12	0	0
T2	11117	20	0	0
T3	1292	25	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	16	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223983	0	0
T1	2100	12	0	0
T2	11117	20	0	0
T3	1292	25	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	16	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223983	0	0
T1	2100	12	0	0
T2	11117	20	0	0
T3	1292	25	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	16	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2814384	0	0
T1	2100	13	0	0
T2	11117	118	0	0
T3	1292	24	0	0
T7	8962	70	0	0
T8	11426	50	0	0
T9	2817	17	0	0
T10	2387	15	0	0
T11	42885	1	0	0
T12	11983	207	0	0
T13	2815	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223983	0	0
T1	2100	12	0	0
T2	11117	20	0	0
T3	1292	25	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	16	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223983	0	0
T1	2100	12	0	0
T2	11117	20	0	0
T3	1292	25	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	16	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	579813	0	0
T1	2100	12	0	0
T2	11117	53	0	0
T3	1292	27	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	55	0	0
T13	2815	16	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	223983	0	0
T1	2100	12	0	0
T2	11117	20	0	0
T3	1292	25	0	0
T7	8962	8	0	0
T8	11426	6	0	0
T9	2817	16	0	0
T10	2387	14	0	0
T11	42885	0	0	0
T12	11983	25	0	0
T13	2815	16	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	224844	0	0
GntImpliesValid_A	440730203	224844	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	224844	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2847798	0	0
ReadyAndValidImplyGrant_A	440730203	224844	0	0
ReqAndReadyImplyGrant_A	440730203	224844	0	0
ReqImpliesValid_A	440730203	559170	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	224844	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	224844	0	0
T1	2100	15	0	0
T2	11117	12	0	0
T3	1292	22	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	10	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	224844	0	0
T1	2100	15	0	0
T2	11117	12	0	0
T3	1292	22	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	10	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	224844	0	0
T1	2100	15	0	0
T2	11117	12	0	0
T3	1292	22	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	10	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2847798	0	0
T1	2100	16	0	0
T2	11117	117	0	0
T3	1292	21	0	0
T7	8962	28	0	0
T8	11426	54	0	0
T9	2817	18	0	0
T10	2387	9	0	0
T11	42885	1	0	0
T12	11983	140	0	0
T13	2815	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	224844	0	0
T1	2100	15	0	0
T2	11117	12	0	0
T3	1292	22	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	10	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	224844	0	0
T1	2100	15	0	0
T2	11117	12	0	0
T3	1292	22	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	10	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	559170	0	0
T1	2100	15	0	0
T2	11117	16	0	0
T3	1292	24	0	0
T7	8962	13	0	0
T8	11426	9	0	0
T9	2817	19	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	28	0	0
T13	2815	10	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	224844	0	0
T1	2100	15	0	0
T2	11117	12	0	0
T3	1292	22	0	0
T7	8962	5	0	0
T8	11426	9	0	0
T9	2817	18	0	0
T10	2387	8	0	0
T11	42885	0	0	0
T12	11983	23	0	0
T13	2815	10	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	215689	0	0
GntImpliesValid_A	440730203	215689	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	215689	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	2780495	0	0
ReadyAndValidImplyGrant_A	440730203	215689	0	0
ReqAndReadyImplyGrant_A	440730203	215689	0	0
ReqImpliesValid_A	440730203	526100	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	0	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	215689	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215689	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	17	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	494	0	0
T12	11983	18	0	0
T13	2815	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215689	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	17	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	494	0	0
T12	11983	18	0	0
T13	2815	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215689	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	17	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	494	0	0
T12	11983	18	0	0
T13	2815	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2780495	0	0
T1	2100	9	0	0
T2	11117	77	0	0
T3	1292	17	0	0
T7	8962	88	0	0
T8	11426	109	0	0
T9	2817	22	0	0
T10	2387	12	0	0
T11	42885	1254	0	0
T12	11983	135	0	0
T13	2815	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215689	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	17	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	494	0	0
T12	11983	18	0	0
T13	2815	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215689	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	17	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	494	0	0
T12	11983	18	0	0
T13	2815	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	526100	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	18	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	23	0	0
T10	2387	11	0	0
T11	42885	4263	0	0
T12	11983	18	0	0
T13	2815	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	215689	0	0
T1	2100	8	0	0
T2	11117	11	0	0
T3	1292	17	0	0
T7	8962	10	0	0
T8	11426	13	0	0
T9	2817	22	0	0
T10	2387	11	0	0
T11	42885	494	0	0
T12	11983	18	0	0
T13	2815	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	892784	0	0
GntImpliesValid_A	440730203	892784	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	892784	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	10431201	0	0
ReadyAndValidImplyGrant_A	440730203	892784	0	0
ReqAndReadyImplyGrant_A	440730203	892784	0	0
ReqImpliesValid_A	440730203	2200991	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	22894	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	892784	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	892784	0	0
T1	2100	55	0	0
T2	11117	61	0	0
T3	1292	54	0	0
T7	8962	48	0	0
T8	11426	52	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	217	0	0
T12	11983	105	0	0
T13	2815	70	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	892784	0	0
T1	2100	55	0	0
T2	11117	61	0	0
T3	1292	54	0	0
T7	8962	48	0	0
T8	11426	52	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	217	0	0
T12	11983	105	0	0
T13	2815	70	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	892784	0	0
T1	2100	55	0	0
T2	11117	61	0	0
T3	1292	54	0	0
T7	8962	48	0	0
T8	11426	52	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	217	0	0
T12	11983	105	0	0
T13	2815	70	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	10431201	0	0
T1	2100	1	0	0
T2	11117	375	0	0
T3	1292	1	0	0
T7	8962	273	0	0
T8	11426	334	0	0
T9	2817	1	0	0
T10	2387	1	0	0
T11	42885	1264	0	0
T12	11983	733	0	0
T13	2815	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	892784	0	0
T1	2100	55	0	0
T2	11117	61	0	0
T3	1292	54	0	0
T7	8962	48	0	0
T8	11426	52	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	217	0	0
T12	11983	105	0	0
T13	2815	70	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	892784	0	0
T1	2100	55	0	0
T2	11117	61	0	0
T3	1292	54	0	0
T7	8962	48	0	0
T8	11426	52	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	217	0	0
T12	11983	105	0	0
T13	2815	70	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	2200991	0	0
T1	2100	55	0	0
T2	11117	86	0	0
T3	1292	54	0	0
T7	8962	93	0	0
T8	11426	91	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	284	0	0
T12	11983	120	0	0
T13	2815	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	22894	0	900
T15	4630	3	0	1
T16	17053	6	0	1
T17	3158	6	0	1
T18	9882	13	0	1
T19	14699	8	0	1
T20	149865	69	0	1
T21	5967	3	0	1
T22	19219	0	0	1
T23	0	6	0	0
T24	0	6	0	0
T25	0	6	0	0
T27	20985	0	0	1
T28	261236	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	892784	0	0
T1	2100	55	0	0
T2	11117	61	0	0
T3	1292	54	0	0
T7	8962	48	0	0
T8	11426	52	0	0
T9	2817	39	0	0
T10	2387	55	0	0
T11	42885	217	0	0
T12	11983	105	0	0
T13	2815	70	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440730203	440615128	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	440730203	863379	0	0
GntImpliesValid_A	440730203	863379	0	0
GrantKnown_A	440730203	440615128	0	0
IdxKnown_A	440730203	440615128	0	0
IndexIsCorrect_A	440730203	863379	0	0
LockArbDecision_A	440730203	0	0	0
NoReadyValidNoGrant_A	440730203	368224649	0	0
ReadyAndValidImplyGrant_A	440730203	863379	0	0
ReqAndReadyImplyGrant_A	440730203	863379	0	0
ReqImpliesValid_A	440730203	12076847	0	0
ReqStaysHighUntilGranted0_M	440730203	0	0	0
RoundRobin_A	440730203	28628	0	900
ValidKnown_A	440730203	440615128	0	0
gen_data_port_assertion.DataFlow_A	440730203	863379	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	863379	0	0
T1	2100	58	0	0
T2	11117	49	0	0
T3	1292	40	0	0
T7	8962	55	0	0
T8	11426	48	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	998	0	0
T12	11983	83	0	0
T13	2815	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	863379	0	0
T1	2100	58	0	0
T2	11117	49	0	0
T3	1292	40	0	0
T7	8962	55	0	0
T8	11426	48	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	998	0	0
T12	11983	83	0	0
T13	2815	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	863379	0	0
T1	2100	58	0	0
T2	11117	49	0	0
T3	1292	40	0	0
T7	8962	55	0	0
T8	11426	48	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	998	0	0
T12	11983	83	0	0
T13	2815	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	368224649	0	0
T1	2100	1	0	0
T2	11117	9732	0	0
T3	1292	1	0	0
T7	8962	7770	0	0
T8	11426	10095	0	0
T9	2817	1	0	0
T10	2387	1	0	0
T11	42885	30949	0	0
T12	11983	10270	0	0
T13	2815	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	863379	0	0
T1	2100	58	0	0
T2	11117	49	0	0
T3	1292	40	0	0
T7	8962	55	0	0
T8	11426	48	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	998	0	0
T12	11983	83	0	0
T13	2815	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	863379	0	0
T1	2100	58	0	0
T2	11117	49	0	0
T3	1292	40	0	0
T7	8962	55	0	0
T8	11426	48	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	998	0	0
T12	11983	83	0	0
T13	2815	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	12076847	0	0
T1	2100	58	0	0
T2	11117	379	0	0
T3	1292	40	0	0
T7	8962	407	0	0
T8	11426	322	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	6189	0	0
T12	11983	691	0	0
T13	2815	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	28628	0	900
T11	42885	52	0	1
T12	11983	0	0	1
T13	2815	0	0	1
T14	8775	0	0	1
T15	4630	6	0	1
T16	17053	6	0	1
T17	3158	3	0	1
T18	9882	15	0	1
T19	0	24	0	0
T20	0	40	0	0
T21	0	4	0	0
T22	0	7	0	0
T23	0	4	0	0
T26	17347	0	0	1
T27	20985	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	440615128	0	0
T1	2100	2042	0	0
T2	11117	11057	0	0
T3	1292	1251	0	0
T7	8962	8937	0	0
T8	11426	11379	0	0
T9	2817	2737	0	0
T10	2387	2364	0	0
T11	42885	42807	0	0
T12	11983	11953	0	0
T13	2815	2753	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440730203	863379	0	0
T1	2100	58	0	0
T2	11117	49	0	0
T3	1292	40	0	0
T7	8962	55	0	0
T8	11426	48	0	0
T9	2817	42	0	0
T10	2387	44	0	0
T11	42885	998	0	0
T12	11983	83	0	0
T13	2815	60	0	0