Unified Coverage Report :: Module :: tlul_socket_m1

Module : tlul_socket_m1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28	95.96	100.00	87.88				100.00
tb.dut.u_sm1_29	95.96	100.00	87.88				100.00
tb.dut.u_sm1_31	95.96	100.00	87.88				100.00
tb.dut.u_sm1_33	96.97	100.00	90.91				100.00
tb.dut.u_sm1_34	96.97	100.00	90.91				100.00
tb.dut.u_sm1_36	96.97	100.00	90.91				100.00
tb.dut.u_sm1_38	96.97	100.00	90.91				100.00
tb.dut.u_sm1_40	96.97	100.00	90.91				100.00
tb.dut.u_sm1_42	96.97	100.00	90.91				100.00
tb.dut.u_sm1_43	96.97	100.00	90.91				100.00
tb.dut.u_sm1_44	96.97	100.00	90.91				100.00
tb.dut.u_sm1_45	96.97	100.00	90.91				100.00
tb.dut.u_sm1_46	96.97	100.00	90.91				100.00
tb.dut.u_sm1_47	96.97	100.00	90.91				100.00
tb.dut.u_sm1_48	96.97	100.00	90.91				100.00
tb.dut.u_sm1_49	96.97	100.00	90.91				100.00
tb.dut.u_sm1_50	96.97	100.00	90.91				100.00
tb.dut.u_sm1_51	96.97	100.00	90.91				100.00
tb.dut.u_sm1_52	96.97	100.00	90.91				100.00
tb.dut.u_sm1_53	96.97	100.00	90.91				100.00
tb.dut.u_sm1_54	96.97	100.00	90.91				100.00
tb.dut.u_sm1_55	96.97	100.00	90.91				100.00
tb.dut.u_sm1_56	96.97	100.00	90.91				100.00
tb.dut.u_sm1_30	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sm1_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.61	98.68	85.92			92.73	97.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	92.21	97.50	82.14			89.19	100.00

---

Module Instance : tb.dut.u_sm1_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	98.68	85.07			92.59	95.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	98.68	85.07			92.59	95.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.87	100.00	98.39			100.00	97.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_28

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_29

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_33

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_34

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_36

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_38

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_40

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_42

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_43

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_44

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_45

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_46

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_47

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_48

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_49

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_50

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_51

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_52

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_53

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_54

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_55

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
95.96	87.88

tb.dut.u_sm1_28

SCORE	COND
95.96	87.88

tb.dut.u_sm1_29

SCORE	COND
95.96	87.88

tb.dut.u_sm1_31

SCORE	COND
100.00	100.00

tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T11,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T11,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.97	90.91

tb.dut.u_sm1_33

SCORE	COND
96.97	90.91

tb.dut.u_sm1_34

SCORE	COND
96.97	90.91

tb.dut.u_sm1_43

SCORE	COND
96.97	90.91

tb.dut.u_sm1_44

SCORE	COND
96.97	90.91

tb.dut.u_sm1_45

SCORE	COND
96.97	90.91

tb.dut.u_sm1_46

SCORE	COND
96.97	90.91

tb.dut.u_sm1_47

SCORE	COND
96.97	90.91

tb.dut.u_sm1_48

SCORE	COND
96.97	90.91

tb.dut.u_sm1_49

SCORE	COND
96.97	90.91

tb.dut.u_sm1_50

SCORE	COND
96.97	90.91

tb.dut.u_sm1_51

SCORE	COND
96.97	90.91

tb.dut.u_sm1_52

SCORE	COND
96.97	90.91

tb.dut.u_sm1_53

SCORE	COND
96.97	90.91

tb.dut.u_sm1_54

SCORE	COND
96.97	90.91

tb.dut.u_sm1_55

SCORE	COND
96.97	90.91

tb.dut.u_sm1_56

SCORE	COND
96.97	90.91

tb.dut.u_sm1_36

SCORE	COND
96.97	90.91

tb.dut.u_sm1_38

SCORE	COND
96.97	90.91

tb.dut.u_sm1_40

SCORE	COND
96.97	90.91

tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_m1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	2147483647	22196150	0	0
gen_host_fifo[1].idInRange	2147483647	12553730	0	0
gen_host_fifo[2].idInRange	1663560036	3573436	0	0
maxM	21600	21600	0	0
rspIdInRange	2147483647	161551576	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22196150	0	0
T1	65112	351	0	0
T2	53568	329	0	0
T3	1111056	7038	0	0
T7	252744	621	0	0
T8	646056	2792	0	0
T9	211944	3574	0	0
T10	53304	307	0	0
T11	386040	3461	0	0
T12	202560	2312	0	0
T13	6650616	583	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12553730	0	0
T1	65112	161	0	0
T2	53568	193	0	0
T3	1111056	3701	0	0
T7	252744	228	0	0
T8	646056	1159	0	0
T9	211944	2011	0	0
T10	53304	150	0	0
T11	386040	1962	0	0
T12	202560	1162	0	0
T13	6650616	261	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663560036	3573436	0	0
T1	10852	31	0	0
T2	8928	21	0	0
T3	185176	966	0	0
T7	42124	93	0	0
T8	107676	437	0	0
T9	35324	326	0	0
T10	8884	28	0	0
T11	64340	327	0	0
T12	33760	197	0	0
T13	1108436	63	0	0
T14	0	20	0	0
T22	0	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	161551576	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	15158	0	0
T7	252744	1836	0	0
T8	646056	5358	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	874	0	0

Line Coverage for Instance : tb.dut.u_sm1_28

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T13
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	1677066	0	0
gen_host_fifo[1].idInRange	415890009	436344	0	0
gen_host_fifo[2].idInRange	415890009	548360	0	0
maxM	900	900	0	0
rspIdInRange	415890009	20188530	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1677066	0	0
T1	2713	44	0	0
T2	2232	27	0	0
T3	46294	567	0	0
T7	10531	72	0	0
T8	26919	270	0	0
T9	8831	421	0	0
T10	2221	42	0	0
T11	16085	432	0	0
T12	8440	281	0	0
T13	277109	73	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	436344	0	0
T1	2713	9	0	0
T2	2232	7	0	0
T3	46294	98	0	0
T7	10531	3	0	0
T8	26919	49	0	0
T9	8831	73	0	0
T10	2221	10	0	0
T11	16085	73	0	0
T12	8440	39	0	0
T13	277109	7	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	548360	0	0
T1	2713	2	0	0
T2	2232	4	0	0
T3	46294	149	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	73	0	0
T10	2221	9	0	0
T11	16085	89	0	0
T12	8440	56	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	20188530	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	2928	0	0
T7	10531	329	0	0
T8	26919	692	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_29

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_29

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

---

Assert Coverage for Instance : tb.dut.u_sm1_29

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	1826563	0	0
gen_host_fifo[1].idInRange	415890009	530543	0	0
gen_host_fifo[2].idInRange	415890009	630630	0	0
maxM	900	900	0	0
rspIdInRange	415890009	19469896	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1826563	0	0
T1	2713	55	0	0
T2	2232	34	0	0
T3	46294	632	0	0
T7	10531	76	0	0
T8	26919	196	0	0
T9	8831	480	0	0
T10	2221	43	0	0
T11	16085	459	0	0
T12	8440	299	0	0
T13	277109	53	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	530543	0	0
T1	2713	3	0	0
T2	2232	6	0	0
T3	46294	106	0	0
T7	10531	2	0	0
T8	26919	75	0	0
T9	8831	99	0	0
T10	2221	5	0	0
T11	16085	91	0	0
T12	8440	52	0	0
T13	277109	5	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	630630	0	0
T1	2713	7	0	0
T2	2232	0	0	0
T3	46294	160	0	0
T7	10531	0	0	0
T8	26919	30	0	0
T9	8831	72	0	0
T10	2221	7	0	0
T11	16085	84	0	0
T12	8440	46	0	0
T13	277109	7	0	0
T14	0	20	0	0
T22	0	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	19469896	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	2717	0	0
T7	10531	290	0	0
T8	26919	623	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_31

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	1820159	0	0
gen_host_fifo[1].idInRange	415890009	507064	0	0
gen_host_fifo[2].idInRange	415890009	660787	0	0
maxM	900	900	0	0
rspIdInRange	415890009	20570738	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1820159	0	0
T1	2713	53	0	0
T2	2232	29	0	0
T3	46294	736	0	0
T7	10531	58	0	0
T8	26919	280	0	0
T9	8831	546	0	0
T10	2221	45	0	0
T11	16085	474	0	0
T12	8440	314	0	0
T13	277109	66	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	507064	0	0
T1	2713	4	0	0
T2	2232	13	0	0
T3	46294	94	0	0
T7	10531	9	0	0
T8	26919	47	0	0
T9	8831	92	0	0
T10	2221	6	0	0
T11	16085	60	0	0
T12	8440	39	0	0
T13	277109	12	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	660787	0	0
T1	2713	10	0	0
T2	2232	9	0	0
T3	46294	125	0	0
T7	10531	12	0	0
T8	26919	34	0	0
T9	8831	100	0	0
T10	2221	4	0	0
T11	16085	82	0	0
T12	8440	42	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	20570738	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	2992	0	0
T7	10531	253	0	0
T8	26919	696	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	353	0	0

Line Coverage for Instance : tb.dut.u_sm1_33

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_33

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	294316	0	0
gen_host_fifo[1].idInRange	415890009	391754	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3502397	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	294316	0	0
T1	2713	5	0	0
T2	2232	13	0	0
T3	46294	68	0	0
T7	10531	4	0	0
T8	26919	43	0	0
T9	8831	82	0	0
T10	2221	12	0	0
T11	16085	77	0	0
T12	8440	36	0	0
T13	277109	10	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	391754	0	0
T1	2713	8	0	0
T2	2232	10	0	0
T3	46294	93	0	0
T7	10531	6	0	0
T8	26919	40	0	0
T9	8831	63	0	0
T10	2221	5	0	0
T11	16085	72	0	0
T12	8440	39	0	0
T13	277109	9	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3502397	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	189	0	0
T7	10531	40	0	0
T8	26919	132	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_34

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_34

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	335518	0	0
gen_host_fifo[1].idInRange	415890009	437846	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3948313	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	335518	0	0
T1	2713	8	0	0
T2	2232	12	0	0
T3	46294	122	0	0
T7	10531	3	0	0
T8	26919	38	0	0
T9	8831	63	0	0
T10	2221	7	0	0
T11	16085	75	0	0
T12	8440	45	0	0
T13	277109	5	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	437846	0	0
T1	2713	8	0	0
T2	2232	6	0	0
T3	46294	98	0	0
T7	10531	5	0	0
T8	26919	33	0	0
T9	8831	67	0	0
T10	2221	3	0	0
T11	16085	86	0	0
T12	8440	42	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3948313	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	192	0	0
T7	10531	29	0	0
T8	26919	124	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_36

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T23,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	603028	0	0
gen_host_fifo[1].idInRange	415890009	726467	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4276998	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	603028	0	0
T1	2713	16	0	0
T2	2232	14	0	0
T3	46294	444	0	0
T7	10531	5	0	0
T8	26919	26	0	0
T9	8831	109	0	0
T10	2221	1	0	0
T11	16085	118	0	0
T12	8440	102	0	0
T13	277109	10	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	726467	0	0
T1	2713	7	0	0
T2	2232	25	0	0
T3	46294	616	0	0
T7	10531	31	0	0
T8	26919	22	0	0
T9	8831	94	0	0
T10	2221	12	0	0
T11	16085	85	0	0
T12	8440	100	0	0
T13	277109	3	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4276998	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	41	0	0
T8	26919	104	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_38

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	779024	0	0
gen_host_fifo[1].idInRange	415890009	905078	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4148891	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	779024	0	0
T1	2713	3	0	0
T2	2232	24	0	0
T3	46294	159	0	0
T7	10531	1	0	0
T8	26919	31	0	0
T9	8831	149	0	0
T10	2221	4	0	0
T11	16085	90	0	0
T12	8440	51	0	0
T13	277109	9	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	905078	0	0
T1	2713	11	0	0
T2	2232	18	0	0
T3	46294	176	0	0
T7	10531	37	0	0
T8	26919	38	0	0
T9	8831	166	0	0
T10	2221	6	0	0
T11	16085	97	0	0
T12	8440	54	0	0
T13	277109	57	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4148891	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	145	0	0
T7	10531	12	0	0
T8	26919	107	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_40

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_40

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T24,T26
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	746299	0	0
gen_host_fifo[1].idInRange	415890009	926705	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4426599	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	746299	0	0
T1	2713	5	0	0
T2	2232	13	0	0
T3	46294	116	0	0
T7	10531	3	0	0
T8	26919	29	0	0
T9	8831	80	0	0
T10	2221	4	0	0
T11	16085	74	0	0
T12	8440	83	0	0
T13	277109	32	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	926705	0	0
T1	2713	9	0	0
T2	2232	4	0	0
T3	46294	201	0	0
T7	10531	7	0	0
T8	26919	26	0	0
T9	8831	111	0	0
T10	2221	15	0	0
T11	16085	96	0	0
T12	8440	54	0	0
T13	277109	10	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4426599	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	131	0	0
T7	10531	26	0	0
T8	26919	89	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_42

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	623696	0	0
gen_host_fifo[1].idInRange	415890009	734189	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3925442	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	623696	0	0
T1	2713	40	0	0
T2	2232	13	0	0
T3	46294	169	0	0
T7	10531	7	0	0
T8	26919	41	0	0
T9	8831	104	0	0
T10	2221	11	0	0
T11	16085	88	0	0
T12	8440	69	0	0
T13	277109	28	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	734189	0	0
T1	2713	5	0	0
T2	2232	11	0	0
T3	46294	235	0	0
T7	10531	6	0	0
T8	26919	30	0	0
T9	8831	124	0	0
T10	2221	4	0	0
T11	16085	83	0	0
T12	8440	61	0	0
T13	277109	10	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3925442	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	149	0	0
T7	10531	53	0	0
T8	26919	193	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_43

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_43

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	260440	0	0
gen_host_fifo[1].idInRange	415890009	337302	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4344611	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	260440	0	0
T1	2713	3	0	0
T2	2232	9	0	0
T3	46294	62	0	0
T7	10531	4	0	0
T8	26919	56	0	0
T9	8831	88	0	0
T10	2221	5	0	0
T11	16085	89	0	0
T12	8440	54	0	0
T13	277109	3	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	337302	0	0
T1	2713	6	0	0
T2	2232	7	0	0
T3	46294	70	0	0
T7	10531	3	0	0
T8	26919	69	0	0
T9	8831	71	0	0
T10	2221	7	0	0
T11	16085	74	0	0
T12	8440	39	0	0
T13	277109	3	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4344611	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	171	0	0
T7	10531	47	0	0
T8	26919	164	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_44

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_44

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	278034	0	0
gen_host_fifo[1].idInRange	415890009	353145	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3614012	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	278034	0	0
T1	2713	9	0	0
T2	2232	10	0	0
T3	46294	83	0	0
T7	10531	3	0	0
T8	26919	46	0	0
T9	8831	70	0	0
T10	2221	15	0	0
T11	16085	73	0	0
T12	8440	39	0	0
T13	277109	3	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	353145	0	0
T1	2713	2	0	0
T2	2232	9	0	0
T3	46294	83	0	0
T7	10531	5	0	0
T8	26919	51	0	0
T9	8831	88	0	0
T10	2221	11	0	0
T11	16085	79	0	0
T12	8440	53	0	0
T13	277109	13	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3614012	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	216	0	0
T7	10531	9	0	0
T8	26919	88	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_45

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_45

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	315499	0	0
gen_host_fifo[1].idInRange	415890009	414903	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3943577	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	315499	0	0
T1	2713	5	0	0
T2	2232	11	0	0
T3	46294	78	0	0
T7	10531	7	0	0
T8	26919	28	0	0
T9	8831	72	0	0
T10	2221	10	0	0
T11	16085	81	0	0
T12	8440	54	0	0
T13	277109	6	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	414903	0	0
T1	2713	11	0	0
T2	2232	8	0	0
T3	46294	89	0	0
T7	10531	5	0	0
T8	26919	36	0	0
T9	8831	74	0	0
T10	2221	6	0	0
T11	16085	84	0	0
T12	8440	52	0	0
T13	277109	7	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3943577	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	225	0	0
T7	10531	66	0	0
T8	26919	114	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_46

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	269941	0	0
gen_host_fifo[1].idInRange	415890009	353133	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4268851	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	269941	0	0
T1	2713	4	0	0
T2	2232	7	0	0
T3	46294	55	0	0
T7	10531	2	0	0
T8	26919	36	0	0
T9	8831	100	0	0
T10	2221	10	0	0
T11	16085	82	0	0
T12	8440	55	0	0
T13	277109	6	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	353133	0	0
T1	2713	4	0	0
T2	2232	6	0	0
T3	46294	116	0	0
T7	10531	5	0	0
T8	26919	45	0	0
T9	8831	74	0	0
T10	2221	2	0	0
T11	16085	75	0	0
T12	8440	44	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4268851	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	193	0	0
T7	10531	13	0	0
T8	26919	107	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_47

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_47

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	268189	0	0
gen_host_fifo[1].idInRange	415890009	342670	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3687927	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	268189	0	0
T1	2713	6	0	0
T2	2232	6	0	0
T3	46294	97	0	0
T7	10531	4	0	0
T8	26919	21	0	0
T9	8831	95	0	0
T10	2221	5	0	0
T11	16085	66	0	0
T12	8440	50	0	0
T13	277109	9	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	342670	0	0
T1	2713	9	0	0
T2	2232	3	0	0
T3	46294	116	0	0
T7	10531	3	0	0
T8	26919	57	0	0
T9	8831	64	0	0
T10	2221	5	0	0
T11	16085	87	0	0
T12	8440	49	0	0
T13	277109	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3687927	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	226	0	0
T7	10531	20	0	0
T8	26919	134	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_48

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	295764	0	0
gen_host_fifo[1].idInRange	415890009	375441	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4000995	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	295764	0	0
T1	2713	5	0	0
T2	2232	8	0	0
T3	46294	72	0	0
T7	10531	2	0	0
T8	26919	38	0	0
T9	8831	77	0	0
T10	2221	9	0	0
T11	16085	85	0	0
T12	8440	73	0	0
T13	277109	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	375441	0	0
T1	2713	7	0	0
T2	2232	11	0	0
T3	46294	74	0	0
T7	10531	4	0	0
T8	26919	32	0	0
T9	8831	90	0	0
T10	2221	6	0	0
T11	16085	85	0	0
T12	8440	37	0	0
T13	277109	5	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4000995	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	215	0	0
T7	10531	13	0	0
T8	26919	154	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_49

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_49

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T23,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	324992	0	0
gen_host_fifo[1].idInRange	415890009	406012	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4013065	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	324992	0	0
T1	2713	6	0	0
T2	2232	12	0	0
T3	46294	88	0	0
T7	10531	5	0	0
T8	26919	42	0	0
T9	8831	75	0	0
T10	2221	4	0	0
T11	16085	67	0	0
T12	8440	44	0	0
T13	277109	5	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	406012	0	0
T1	2713	6	0	0
T2	2232	4	0	0
T3	46294	83	0	0
T7	10531	4	0	0
T8	26919	19	0	0
T9	8831	82	0	0
T10	2221	2	0	0
T11	16085	87	0	0
T12	8440	41	0	0
T13	277109	11	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4013065	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	176	0	0
T7	10531	26	0	0
T8	26919	101	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_50

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_50

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	289304	0	0
gen_host_fifo[1].idInRange	415890009	381487	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3228079	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	289304	0	0
T1	2713	7	0	0
T2	2232	7	0	0
T3	46294	70	0	0
T7	10531	4	0	0
T8	26919	46	0	0
T9	8831	94	0	0
T10	2221	5	0	0
T11	16085	69	0	0
T12	8440	47	0	0
T13	277109	1	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	381487	0	0
T1	2713	8	0	0
T2	2232	4	0	0
T3	46294	149	0	0
T7	10531	6	0	0
T8	26919	37	0	0
T9	8831	77	0	0
T10	2221	3	0	0
T11	16085	80	0	0
T12	8440	44	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3228079	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	200	0	0
T7	10531	43	0	0
T8	26919	164	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_51

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_51

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T23,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	319690	0	0
gen_host_fifo[1].idInRange	415890009	402856	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4243020	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	319690	0	0
T1	2713	3	0	0
T2	2232	10	0	0
T3	46294	86	0	0
T7	10531	3	0	0
T8	26919	63	0	0
T9	8831	90	0	0
T10	2221	3	0	0
T11	16085	69	0	0
T12	8440	98	0	0
T13	277109	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	402856	0	0
T1	2713	5	0	0
T2	2232	5	0	0
T3	46294	111	0	0
T7	10531	7	0	0
T8	26919	50	0	0
T9	8831	81	0	0
T10	2221	8	0	0
T11	16085	73	0	0
T12	8440	71	0	0
T13	277109	4	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4243020	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	200	0	0
T7	10531	19	0	0
T8	26919	198	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_52

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_52

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	257634	0	0
gen_host_fifo[1].idInRange	415890009	340895	0	0
maxM	900	900	0	0
rspIdInRange	415890009	4020010	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	257634	0	0
T1	2713	8	0	0
T2	2232	7	0	0
T3	46294	91	0	0
T7	10531	4	0	0
T8	26919	50	0	0
T9	8831	101	0	0
T10	2221	3	0	0
T11	16085	86	0	0
T12	8440	57	0	0
T13	277109	11	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	340895	0	0
T1	2713	5	0	0
T2	2232	8	0	0
T3	46294	100	0	0
T7	10531	6	0	0
T8	26919	60	0	0
T9	8831	79	0	0
T10	2221	6	0	0
T11	16085	77	0	0
T12	8440	43	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4020010	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	267	0	0
T7	10531	21	0	0
T8	26919	134	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_53

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	282711	0	0
gen_host_fifo[1].idInRange	415890009	374130	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3877486	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	282711	0	0
T1	2713	6	0	0
T2	2232	10	0	0
T3	46294	69	0	0
T7	10531	8	0	0
T8	26919	31	0	0
T9	8831	65	0	0
T10	2221	7	0	0
T11	16085	88	0	0
T12	8440	43	0	0
T13	277109	1	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	374130	0	0
T1	2713	7	0	0
T2	2232	3	0	0
T3	46294	76	0	0
T7	10531	6	0	0
T8	26919	57	0	0
T9	8831	81	0	0
T10	2221	4	0	0
T11	16085	80	0	0
T12	8440	43	0	0
T13	277109	20	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3877486	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	156	0	0
T7	10531	67	0	0
T8	26919	148	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_54

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	272774	0	0
gen_host_fifo[1].idInRange	415890009	344913	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3536793	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	272774	0	0
T1	2713	10	0	0
T2	2232	7	0	0
T3	46294	104	0	0
T7	10531	19	0	0
T8	26919	39	0	0
T9	8831	75	0	0
T10	2221	12	0	0
T11	16085	71	0	0
T12	8440	39	0	0
T13	277109	5	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	344913	0	0
T1	2713	2	0	0
T2	2232	2	0	0
T3	46294	99	0	0
T7	10531	3	0	0
T8	26919	34	0	0
T9	8831	59	0	0
T10	2221	9	0	0
T11	16085	85	0	0
T12	8440	40	0	0
T13	277109	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3536793	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	220	0	0
T7	10531	25	0	0
T8	26919	117	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_55

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	279374	0	0
gen_host_fifo[1].idInRange	415890009	388132	0	0
maxM	900	900	0	0
rspIdInRange	415890009	5092401	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	279374	0	0
T1	2713	7	0	0
T2	2232	7	0	0
T3	46294	54	0	0
T7	10531	4	0	0
T8	26919	27	0	0
T9	8831	72	0	0
T10	2221	11	0	0
T11	16085	79	0	0
T12	8440	58	0	0
T13	277109	7	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	388132	0	0
T1	2713	7	0	0
T2	2232	9	0	0
T3	46294	94	0	0
T7	10531	4	0	0
T8	26919	37	0	0
T9	8831	54	0	0
T10	2221	2	0	0
T11	16085	72	0	0
T12	8440	37	0	0
T13	277109	7	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	5092401	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	227	0	0
T7	10531	41	0	0
T8	26919	95	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_56

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	330803	0	0
gen_host_fifo[1].idInRange	415890009	427533	0	0
maxM	900	900	0	0
rspIdInRange	415890009	3717434	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	330803	0	0
T1	2713	9	0	0
T2	2232	8	0	0
T3	46294	94	0	0
T7	10531	3	0	0
T8	26919	49	0	0
T9	8831	75	0	0
T10	2221	10	0	0
T11	16085	93	0	0
T12	8440	41	0	0
T13	277109	2	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	427533	0	0
T1	2713	7	0	0
T2	2232	8	0	0
T3	46294	140	0	0
T7	10531	1	0	0
T8	26919	39	0	0
T9	8831	73	0	0
T10	2221	4	0	0
T11	16085	87	0	0
T12	8440	49	0	0
T13	277109	7	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	3717434	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	287	0	0
T7	10531	21	0	0
T8	26919	137	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_30

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T11,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T11,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T11,T8
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	415890009	9445332	0	0
gen_host_fifo[1].idInRange	415890009	1715188	0	0
gen_host_fifo[2].idInRange	415890009	1733659	0	0
maxM	900	900	0	0
rspIdInRange	415890009	21505511	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	9445332	0	0
T1	2713	34	0	0
T2	2232	31	0	0
T3	46294	2922	0	0
T7	10531	320	0	0
T8	26919	1266	0	0
T9	8831	391	0	0
T10	2221	29	0	0
T11	16085	476	0	0
T12	8440	280	0	0
T13	277109	234	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1715188	0	0
T1	2713	11	0	0
T2	2232	6	0	0
T3	46294	584	0	0
T7	10531	60	0	0
T8	26919	176	0	0
T9	8831	75	0	0
T10	2221	9	0	0
T11	16085	94	0	0
T12	8440	40	0	0
T13	277109	26	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1733659	0	0
T1	2713	12	0	0
T2	2232	8	0	0
T3	46294	532	0	0
T7	10531	70	0	0
T8	26919	325	0	0
T9	8831	81	0	0
T10	2221	8	0	0
T11	16085	72	0	0
T12	8440	53	0	0
T13	277109	40	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	21505511	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	2600	0	0
T7	10531	332	0	0
T8	26919	743	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	68	0	0