Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7727478	0	0
GntImpliesValid_A	2147483647	7727478	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7727478	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	447761438	0	0
ReadyAndValidImplyGrant_A	2147483647	7727478	0	0
ReqAndReadyImplyGrant_A	2147483647	7727478	0	0
ReqImpliesValid_A	2147483647	33047653	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40573	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7727478	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65112	63048	0	0
T2	53568	52848	0	0
T3	1111056	1109040	0	0
T7	252744	250968	0	0
T8	646056	645288	0	0
T9	211944	211200	0	0
T10	53304	51600	0	0
T11	386040	385440	0	0
T12	202560	201288	0	0
T13	6650616	6648624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727478	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	4576	0	0
T7	252744	382	0	0
T8	646056	2192	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727478	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	4576	0	0
T7	252744	382	0	0
T8	646056	2192	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65112	63048	0	0
T2	53568	52848	0	0
T3	1111056	1109040	0	0
T7	252744	250968	0	0
T8	646056	645288	0	0
T9	211944	211200	0	0
T10	53304	51600	0	0
T11	386040	385440	0	0
T12	202560	201288	0	0
T13	6650616	6648624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65112	63048	0	0
T2	53568	52848	0	0
T3	1111056	1109040	0	0
T7	252744	250968	0	0
T8	646056	645288	0	0
T9	211944	211200	0	0
T10	53304	51600	0	0
T11	386040	385440	0	0
T12	202560	201288	0	0
T13	6650616	6648624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727478	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	4576	0	0
T7	252744	382	0	0
T8	646056	2192	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	482	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447761438	0	0
T1	65112	825	0	0
T2	53568	697	0	0
T3	1111056	75736	0	0
T7	252744	11874	0	0
T8	646056	36727	0	0
T9	211944	6289	0	0
T10	53304	591	0	0
T11	386040	7619	0	0
T12	202560	4227	0	0
T13	6650616	232814	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727478	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	4576	0	0
T7	252744	382	0	0
T8	646056	2192	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727478	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	4576	0	0
T7	252744	382	0	0
T8	646056	2192	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33047653	0	0
T1	65112	543	0	0
T2	53568	543	0	0
T3	1111056	11505	0	0
T7	252744	942	0	0
T8	646056	4296	0	0
T9	211944	5845	0	0
T10	53304	485	0	0
T11	386040	5721	0	0
T12	202560	3651	0	0
T13	6650616	907	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40573	0	21600
T3	46294	1	0	1
T7	21062	0	0	2
T8	53838	0	0	2
T9	17662	26	0	2
T10	4442	0	0	2
T11	32170	22	0	2
T12	16880	7	0	2
T13	554218	0	0	2
T14	7890	6	0	2
T15	3512	6	0	1
T16	0	25	0	0
T17	0	11	0	0
T18	0	1	0	0
T19	0	14	0	0
T20	0	21	0	0
T21	0	52	0	0
T22	813472	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65112	63048	0	0
T2	53568	52848	0	0
T3	1111056	1109040	0	0
T7	252744	250968	0	0
T8	646056	645288	0	0
T9	211944	211200	0	0
T10	53304	51600	0	0
T11	386040	385440	0	0
T12	202560	201288	0	0
T13	6650616	6648624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727478	0	0
T1	65112	478	0	0
T2	53568	464	0	0
T3	1111056	4576	0	0
T7	252744	382	0	0
T8	646056	2192	0	0
T9	211944	5034	0	0
T10	53304	445	0	0
T11	386040	5564	0	0
T12	202560	3235	0	0
T13	6650616	482	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	865523	0	0
GntImpliesValid_A	415890009	865523	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	865523	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	11358429	0	0
ReadyAndValidImplyGrant_A	415890009	865523	0	0
ReqAndReadyImplyGrant_A	415890009	865523	0	0
ReqImpliesValid_A	415890009	2442322	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	865523	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	865523	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	502	0	0
T7	10531	45	0	0
T8	26919	213	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	865523	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	502	0	0
T7	10531	45	0	0
T8	26919	213	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	865523	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	502	0	0
T7	10531	45	0	0
T8	26919	213	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	11358429	0	0
T1	2713	40	0	0
T2	2232	33	0	0
T3	46294	3337	0	0
T7	10531	322	0	0
T8	26919	1529	0	0
T9	8831	388	0	0
T10	2221	42	0	0
T11	16085	590	0	0
T12	8440	293	0	0
T13	277109	192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	865523	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	502	0	0
T7	10531	45	0	0
T8	26919	213	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	865523	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	502	0	0
T7	10531	45	0	0
T8	26919	213	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2442322	0	0
T1	2713	65	0	0
T2	2232	40	0	0
T3	46294	880	0	0
T7	10531	78	0	0
T8	26919	301	0	0
T9	8831	643	0	0
T10	2221	55	0	0
T11	16085	627	0	0
T12	8440	396	0	0
T13	277109	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	865523	0	0
T1	2713	52	0	0
T2	2232	36	0	0
T3	46294	502	0	0
T7	10531	45	0	0
T8	26919	213	0	0
T9	8831	515	0	0
T10	2221	48	0	0
T11	16085	608	0	0
T12	8440	344	0	0
T13	277109	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	879506	0	0
GntImpliesValid_A	415890009	879506	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	879506	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	11377428	0	0
ReadyAndValidImplyGrant_A	415890009	879506	0	0
ReqAndReadyImplyGrant_A	415890009	879506	0	0
ReqImpliesValid_A	415890009	2449971	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	879506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	879506	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	490	0	0
T7	10531	50	0	0
T8	26919	251	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	879506	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	490	0	0
T7	10531	50	0	0
T8	26919	251	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	879506	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	490	0	0
T7	10531	50	0	0
T8	26919	251	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	11377428	0	0
T1	2713	42	0	0
T2	2232	42	0	0
T3	46294	3613	0	0
T7	10531	323	0	0
T8	26919	1917	0	0
T9	8831	418	0	0
T10	2221	40	0	0
T11	16085	587	0	0
T12	8440	288	0	0
T13	277109	254	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	879506	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	490	0	0
T7	10531	50	0	0
T8	26919	251	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	879506	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	490	0	0
T7	10531	50	0	0
T8	26919	251	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2449971	0	0
T1	2713	67	0	0
T2	2232	51	0	0
T3	46294	955	0	0
T7	10531	79	0	0
T8	26919	361	0	0
T9	8831	715	0	0
T10	2221	55	0	0
T11	16085	610	0	0
T12	8440	391	0	0
T13	277109	86	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	879506	0	0
T1	2713	54	0	0
T2	2232	46	0	0
T3	46294	490	0	0
T7	10531	50	0	0
T8	26919	251	0	0
T9	8831	566	0	0
T10	2221	47	0	0
T11	16085	598	0	0
T12	8440	339	0	0
T13	277109	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	204245	0	0
GntImpliesValid_A	415890009	204245	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	204245	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2786001	0	0
ReadyAndValidImplyGrant_A	415890009	204245	0	0
ReqAndReadyImplyGrant_A	415890009	204245	0	0
ReqImpliesValid_A	415890009	561368	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	204245	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	204245	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	130	0	0
T7	10531	10	0	0
T8	26919	63	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	204245	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	130	0	0
T7	10531	10	0	0
T8	26919	63	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	204245	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	130	0	0
T7	10531	10	0	0
T8	26919	63	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2786001	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	974	0	0
T7	10531	62	0	0
T8	26919	446	0	0
T9	8831	134	0	0
T10	2221	16	0	0
T11	16085	143	0	0
T12	8440	76	0	0
T13	277109	81	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	204245	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	130	0	0
T7	10531	10	0	0
T8	26919	63	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	204245	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	130	0	0
T7	10531	10	0	0
T8	26919	63	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	561368	0	0
T1	2713	13	0	0
T2	2232	23	0	0
T3	46294	160	0	0
T7	10531	10	0	0
T8	26919	83	0	0
T9	8831	145	0	0
T10	2221	17	0	0
T11	16085	148	0	0
T12	8440	75	0	0
T13	277109	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	204245	0	0
T1	2713	12	0	0
T2	2232	20	0	0
T3	46294	130	0	0
T7	10531	10	0	0
T8	26919	63	0	0
T9	8831	139	0	0
T10	2221	16	0	0
T11	16085	145	0	0
T12	8440	75	0	0
T13	277109	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	220979	0	0
GntImpliesValid_A	415890009	220979	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	220979	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2862105	0	0
ReadyAndValidImplyGrant_A	415890009	220979	0	0
ReqAndReadyImplyGrant_A	415890009	220979	0	0
ReqImpliesValid_A	415890009	636481	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	220979	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220979	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	131	0	0
T7	10531	8	0	0
T8	26919	58	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220979	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	131	0	0
T7	10531	8	0	0
T8	26919	58	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220979	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	131	0	0
T7	10531	8	0	0
T8	26919	58	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2862105	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	991	0	0
T7	10531	51	0	0
T8	26919	419	0	0
T9	8831	127	0	0
T10	2221	11	0	0
T11	16085	157	0	0
T12	8440	82	0	0
T13	277109	69	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220979	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	131	0	0
T7	10531	8	0	0
T8	26919	58	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220979	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	131	0	0
T7	10531	8	0	0
T8	26919	58	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	636481	0	0
T1	2713	16	0	0
T2	2232	18	0	0
T3	46294	215	0	0
T7	10531	8	0	0
T8	26919	71	0	0
T9	8831	130	0	0
T10	2221	10	0	0
T11	16085	160	0	0
T12	8440	87	0	0
T13	277109	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220979	0	0
T1	2713	15	0	0
T2	2232	17	0	0
T3	46294	131	0	0
T7	10531	8	0	0
T8	26919	58	0	0
T9	8831	128	0	0
T10	2221	10	0	0
T11	16085	158	0	0
T12	8440	84	0	0
T13	277109	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	214620	0	0
GntImpliesValid_A	415890009	214620	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	214620	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	4567509	0	0
ReadyAndValidImplyGrant_A	415890009	214620	0	0
ReqAndReadyImplyGrant_A	415890009	214620	0	0
ReqImpliesValid_A	415890009	1021495	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	214620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	214620	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	214620	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	214620	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4567509	0	0
T1	2713	93	0	0
T2	2232	75	0	0
T3	46294	4462	0	0
T7	10531	134	0	0
T8	26919	630	0	0
T9	8831	735	0	0
T10	2221	36	0	0
T11	16085	1421	0	0
T12	8440	490	0	0
T13	277109	181	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	214620	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	214620	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1021495	0	0
T1	2713	23	0	0
T2	2232	39	0	0
T3	46294	1024	0	0
T7	10531	36	0	0
T8	26919	48	0	0
T9	8831	203	0	0
T10	2221	13	0	0
T11	16085	203	0	0
T12	8440	201	0	0
T13	277109	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	214620	0	0
T1	2713	15	0	0
T2	2232	18	0	0
T3	46294	136	0	0
T7	10531	11	0	0
T8	26919	48	0	0
T9	8831	136	0	0
T10	2221	7	0	0
T11	16085	149	0	0
T12	8440	92	0	0
T13	277109	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	215613	0	0
GntImpliesValid_A	415890009	215613	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	215613	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	5658745	0	0
ReadyAndValidImplyGrant_A	415890009	215613	0	0
ReqAndReadyImplyGrant_A	415890009	215613	0	0
ReqImpliesValid_A	415890009	1311494	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	215613	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215613	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	119	0	0
T7	10531	4	0	0
T8	26919	54	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215613	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	119	0	0
T7	10531	4	0	0
T8	26919	54	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215613	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	119	0	0
T7	10531	4	0	0
T8	26919	54	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	5658745	0	0
T1	2713	61	0	0
T2	2232	173	0	0
T3	46294	2027	0	0
T7	10531	92	0	0
T8	26919	424	0	0
T9	8831	1161	0	0
T10	2221	121	0	0
T11	16085	1041	0	0
T12	8440	424	0	0
T13	277109	227	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215613	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	119	0	0
T7	10531	4	0	0
T8	26919	54	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215613	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	119	0	0
T7	10531	4	0	0
T8	26919	54	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1311494	0	0
T1	2713	14	0	0
T2	2232	42	0	0
T3	46294	335	0	0
T7	10531	38	0	0
T8	26919	69	0	0
T9	8831	315	0	0
T10	2221	10	0	0
T11	16085	187	0	0
T12	8440	105	0	0
T13	277109	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215613	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	119	0	0
T7	10531	4	0	0
T8	26919	54	0	0
T9	8831	145	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	69	0	0
T13	277109	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	215876	0	0
GntImpliesValid_A	415890009	215876	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	215876	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	5626975	0	0
ReadyAndValidImplyGrant_A	415890009	215876	0	0
ReqAndReadyImplyGrant_A	415890009	215876	0	0
ReqImpliesValid_A	415890009	1281806	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	215876	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215876	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	124	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215876	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	124	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215876	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	124	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	5626975	0	0
T1	2713	250	0	0
T2	2232	59	0	0
T3	46294	2685	0	0
T7	10531	291	0	0
T8	26919	357	0	0
T9	8831	517	0	0
T10	2221	41	0	0
T11	16085	791	0	0
T12	8440	562	0	0
T13	277109	235	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215876	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	124	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215876	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	124	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1281806	0	0
T1	2713	14	0	0
T2	2232	17	0	0
T3	46294	317	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	191	0	0
T10	2221	19	0	0
T11	16085	169	0	0
T12	8440	137	0	0
T13	277109	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	215876	0	0
T1	2713	14	0	0
T2	2232	13	0	0
T3	46294	124	0	0
T7	10531	10	0	0
T8	26919	55	0	0
T9	8831	118	0	0
T10	2221	9	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	208711	0	0
GntImpliesValid_A	415890009	208711	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	208711	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	4425503	0	0
ReadyAndValidImplyGrant_A	415890009	208711	0	0
ReqAndReadyImplyGrant_A	415890009	208711	0	0
ReqImpliesValid_A	415890009	1032972	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	208711	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208711	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	134	0	0
T7	10531	13	0	0
T8	26919	54	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208711	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	134	0	0
T7	10531	13	0	0
T8	26919	54	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208711	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	134	0	0
T7	10531	13	0	0
T8	26919	54	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	4425503	0	0
T1	2713	126	0	0
T2	2232	74	0	0
T3	46294	2621	0	0
T7	10531	187	0	0
T8	26919	317	0	0
T9	8831	833	0	0
T10	2221	100	0	0
T11	16085	686	0	0
T12	8440	736	0	0
T13	277109	219	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208711	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	134	0	0
T7	10531	13	0	0
T8	26919	54	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208711	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	134	0	0
T7	10531	13	0	0
T8	26919	54	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	1032972	0	0
T1	2713	45	0	0
T2	2232	24	0	0
T3	46294	404	0	0
T7	10531	13	0	0
T8	26919	71	0	0
T9	8831	227	0	0
T10	2221	15	0	0
T11	16085	170	0	0
T12	8440	130	0	0
T13	277109	38	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208711	0	0
T1	2713	22	0	0
T2	2232	18	0	0
T3	46294	134	0	0
T7	10531	13	0	0
T8	26919	54	0	0
T9	8831	120	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	84	0	0
T13	277109	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	213999	0	0
GntImpliesValid_A	415890009	213999	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	213999	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2859458	0	0
ReadyAndValidImplyGrant_A	415890009	213999	0	0
ReqAndReadyImplyGrant_A	415890009	213999	0	0
ReqImpliesValid_A	415890009	508893	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	213999	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	213999	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	101	0	0
T7	10531	7	0	0
T8	26919	81	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	213999	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	101	0	0
T7	10531	7	0	0
T8	26919	81	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	213999	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	101	0	0
T7	10531	7	0	0
T8	26919	81	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2859458	0	0
T1	2713	10	0	0
T2	2232	15	0	0
T3	46294	798	0	0
T7	10531	62	0	0
T8	26919	567	0	0
T9	8831	138	0	0
T10	2221	13	0	0
T11	16085	162	0	0
T12	8440	80	0	0
T13	277109	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	213999	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	101	0	0
T7	10531	7	0	0
T8	26919	81	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	213999	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	101	0	0
T7	10531	7	0	0
T8	26919	81	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	508893	0	0
T1	2713	9	0	0
T2	2232	16	0	0
T3	46294	131	0	0
T7	10531	7	0	0
T8	26919	125	0	0
T9	8831	157	0	0
T10	2221	12	0	0
T11	16085	163	0	0
T12	8440	93	0	0
T13	277109	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	213999	0	0
T1	2713	9	0	0
T2	2232	15	0	0
T3	46294	101	0	0
T7	10531	7	0	0
T8	26919	81	0	0
T9	8831	147	0	0
T10	2221	12	0	0
T11	16085	162	0	0
T12	8440	86	0	0
T13	277109	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	207534	0	0
GntImpliesValid_A	415890009	207534	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	207534	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2795131	0	0
ReadyAndValidImplyGrant_A	415890009	207534	0	0
ReqAndReadyImplyGrant_A	415890009	207534	0	0
ReqImpliesValid_A	415890009	529525	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	207534	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	207534	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	138	0	0
T7	10531	8	0	0
T8	26919	59	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	207534	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	138	0	0
T7	10531	8	0	0
T8	26919	59	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	207534	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	138	0	0
T7	10531	8	0	0
T8	26919	59	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2795131	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	1087	0	0
T7	10531	56	0	0
T8	26919	456	0	0
T9	8831	148	0	0
T10	2221	23	0	0
T11	16085	149	0	0
T12	8440	91	0	0
T13	277109	26	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	207534	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	138	0	0
T7	10531	8	0	0
T8	26919	59	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	207534	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	138	0	0
T7	10531	8	0	0
T8	26919	59	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	529525	0	0
T1	2713	11	0	0
T2	2232	19	0	0
T3	46294	166	0	0
T7	10531	8	0	0
T8	26919	97	0	0
T9	8831	157	0	0
T10	2221	26	0	0
T11	16085	152	0	0
T12	8440	92	0	0
T13	277109	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	207534	0	0
T1	2713	10	0	0
T2	2232	18	0	0
T3	46294	138	0	0
T7	10531	8	0	0
T8	26919	59	0	0
T9	8831	152	0	0
T10	2221	24	0	0
T11	16085	150	0	0
T12	8440	91	0	0
T13	277109	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	220432	0	0
GntImpliesValid_A	415890009	220432	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	220432	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2853642	0	0
ReadyAndValidImplyGrant_A	415890009	220432	0	0
ReqAndReadyImplyGrant_A	415890009	220432	0	0
ReqImpliesValid_A	415890009	602498	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	220432	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220432	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	146	0	0
T7	10531	12	0	0
T8	26919	61	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220432	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	146	0	0
T7	10531	12	0	0
T8	26919	61	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220432	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	146	0	0
T7	10531	12	0	0
T8	26919	61	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2853642	0	0
T1	2713	17	0	0
T2	2232	16	0	0
T3	46294	1038	0	0
T7	10531	83	0	0
T8	26919	460	0	0
T9	8831	134	0	0
T10	2221	15	0	0
T11	16085	160	0	0
T12	8440	99	0	0
T13	277109	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220432	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	146	0	0
T7	10531	12	0	0
T8	26919	61	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220432	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	146	0	0
T7	10531	12	0	0
T8	26919	61	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	602498	0	0
T1	2713	16	0	0
T2	2232	19	0	0
T3	46294	167	0	0
T7	10531	12	0	0
T8	26919	64	0	0
T9	8831	145	0	0
T10	2221	16	0	0
T11	16085	165	0	0
T12	8440	106	0	0
T13	277109	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	220432	0	0
T1	2713	16	0	0
T2	2232	17	0	0
T3	46294	146	0	0
T7	10531	12	0	0
T8	26919	61	0	0
T9	8831	139	0	0
T10	2221	15	0	0
T11	16085	162	0	0
T12	8440	102	0	0
T13	277109	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	208417	0	0
GntImpliesValid_A	415890009	208417	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	208417	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2860672	0	0
ReadyAndValidImplyGrant_A	415890009	208417	0	0
ReqAndReadyImplyGrant_A	415890009	208417	0	0
ReqImpliesValid_A	415890009	526778	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	208417	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208417	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	128	0	0
T7	10531	6	0	0
T8	26919	53	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208417	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	128	0	0
T7	10531	6	0	0
T8	26919	53	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208417	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	128	0	0
T7	10531	6	0	0
T8	26919	53	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2860672	0	0
T1	2713	9	0	0
T2	2232	14	0	0
T3	46294	973	0	0
T7	10531	41	0	0
T8	26919	410	0	0
T9	8831	153	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	86	0	0
T13	277109	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208417	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	128	0	0
T7	10531	6	0	0
T8	26919	53	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208417	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	128	0	0
T7	10531	6	0	0
T8	26919	53	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	526778	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	171	0	0
T7	10531	7	0	0
T8	26919	78	0	0
T9	8831	174	0	0
T10	2221	12	0	0
T11	16085	156	0	0
T12	8440	97	0	0
T13	277109	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	208417	0	0
T1	2713	8	0	0
T2	2232	13	0	0
T3	46294	128	0	0
T7	10531	6	0	0
T8	26919	53	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	153	0	0
T12	8440	91	0	0
T13	277109	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	205334	0	0
GntImpliesValid_A	415890009	205334	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	205334	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2741335	0	0
ReadyAndValidImplyGrant_A	415890009	205334	0	0
ReqAndReadyImplyGrant_A	415890009	205334	0	0
ReqImpliesValid_A	415890009	514723	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	205334	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205334	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	142	0	0
T7	10531	7	0	0
T8	26919	55	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205334	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	142	0	0
T7	10531	7	0	0
T8	26919	55	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205334	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	142	0	0
T7	10531	7	0	0
T8	26919	55	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2741335	0	0
T1	2713	16	0	0
T2	2232	10	0	0
T3	46294	1023	0	0
T7	10531	73	0	0
T8	26919	367	0	0
T9	8831	144	0	0
T10	2221	11	0	0
T11	16085	149	0	0
T12	8440	90	0	0
T13	277109	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205334	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	142	0	0
T7	10531	7	0	0
T8	26919	55	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205334	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	142	0	0
T7	10531	7	0	0
T8	26919	55	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	514723	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	213	0	0
T7	10531	7	0	0
T8	26919	78	0	0
T9	8831	159	0	0
T10	2221	10	0	0
T11	16085	152	0	0
T12	8440	99	0	0
T13	277109	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205334	0	0
T1	2713	15	0	0
T2	2232	9	0	0
T3	46294	142	0	0
T7	10531	7	0	0
T8	26919	55	0	0
T9	8831	151	0	0
T10	2221	10	0	0
T11	16085	150	0	0
T12	8440	94	0	0
T13	277109	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	212100	0	0
GntImpliesValid_A	415890009	212100	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	212100	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2814759	0	0
ReadyAndValidImplyGrant_A	415890009	212100	0	0
ReqAndReadyImplyGrant_A	415890009	212100	0	0
ReqImpliesValid_A	415890009	561494	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	212100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	212100	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	112	0	0
T7	10531	6	0	0
T8	26919	61	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	212100	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	112	0	0
T7	10531	6	0	0
T8	26919	61	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	212100	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	112	0	0
T7	10531	6	0	0
T8	26919	61	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2814759	0	0
T1	2713	13	0	0
T2	2232	18	0	0
T3	46294	801	0	0
T7	10531	66	0	0
T8	26919	506	0	0
T9	8831	152	0	0
T10	2221	16	0	0
T11	16085	169	0	0
T12	8440	97	0	0
T13	277109	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	212100	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	112	0	0
T7	10531	6	0	0
T8	26919	61	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	212100	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	112	0	0
T7	10531	6	0	0
T8	26919	61	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	561494	0	0
T1	2713	12	0	0
T2	2232	19	0	0
T3	46294	146	0	0
T7	10531	6	0	0
T8	26919	70	0	0
T9	8831	167	0	0
T10	2221	15	0	0
T11	16085	170	0	0
T12	8440	110	0	0
T13	277109	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	212100	0	0
T1	2713	12	0	0
T2	2232	18	0	0
T3	46294	112	0	0
T7	10531	6	0	0
T8	26919	61	0	0
T9	8831	159	0	0
T10	2221	15	0	0
T11	16085	169	0	0
T12	8440	103	0	0
T13	277109	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	222327	0	0
GntImpliesValid_A	415890009	222327	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	222327	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2814748	0	0
ReadyAndValidImplyGrant_A	415890009	222327	0	0
ReqAndReadyImplyGrant_A	415890009	222327	0	0
ReqImpliesValid_A	415890009	596421	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	222327	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	222327	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	124	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	222327	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	124	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	222327	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	124	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2814748	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	872	0	0
T7	10531	87	0	0
T8	26919	452	0	0
T9	8831	143	0	0
T10	2221	7	0	0
T11	16085	155	0	0
T12	8440	84	0	0
T13	277109	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	222327	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	124	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	222327	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	124	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	596421	0	0
T1	2713	12	0	0
T2	2232	16	0	0
T3	46294	171	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	156	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	85	0	0
T13	277109	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	222327	0	0
T1	2713	12	0	0
T2	2232	15	0	0
T3	46294	124	0	0
T7	10531	9	0	0
T8	26919	61	0	0
T9	8831	149	0	0
T10	2221	6	0	0
T11	16085	154	0	0
T12	8440	84	0	0
T13	277109	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	211903	0	0
GntImpliesValid_A	415890009	211903	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	211903	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2800072	0	0
ReadyAndValidImplyGrant_A	415890009	211903	0	0
ReqAndReadyImplyGrant_A	415890009	211903	0	0
ReqImpliesValid_A	415890009	552746	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	211903	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	211903	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	145	0	0
T7	10531	10	0	0
T8	26919	74	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	211903	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	145	0	0
T7	10531	10	0	0
T8	26919	74	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	211903	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	145	0	0
T7	10531	10	0	0
T8	26919	74	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2800072	0	0
T1	2713	16	0	0
T2	2232	12	0	0
T3	46294	1224	0	0
T7	10531	76	0	0
T8	26919	548	0	0
T9	8831	152	0	0
T10	2221	9	0	0
T11	16085	148	0	0
T12	8440	84	0	0
T13	277109	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	211903	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	145	0	0
T7	10531	10	0	0
T8	26919	74	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	211903	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	145	0	0
T7	10531	10	0	0
T8	26919	74	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	552746	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	219	0	0
T7	10531	10	0	0
T8	26919	83	0	0
T9	8831	171	0	0
T10	2221	8	0	0
T11	16085	149	0	0
T12	8440	91	0	0
T13	277109	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	211903	0	0
T1	2713	15	0	0
T2	2232	11	0	0
T3	46294	145	0	0
T7	10531	10	0	0
T8	26919	74	0	0
T9	8831	161	0	0
T10	2221	8	0	0
T11	16085	148	0	0
T12	8440	87	0	0
T13	277109	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	242665	0	0
GntImpliesValid_A	415890009	242665	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	242665	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2899725	0	0
ReadyAndValidImplyGrant_A	415890009	242665	0	0
ReqAndReadyImplyGrant_A	415890009	242665	0	0
ReqImpliesValid_A	415890009	609836	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	242665	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	242665	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	133	0	0
T7	10531	10	0	0
T8	26919	104	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	242665	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	133	0	0
T7	10531	10	0	0
T8	26919	104	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	242665	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	133	0	0
T7	10531	10	0	0
T8	26919	104	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2899725	0	0
T1	2713	9	0	0
T2	2232	14	0	0
T3	46294	936	0	0
T7	10531	79	0	0
T8	26919	770	0	0
T9	8831	140	0	0
T10	2221	12	0	0
T11	16085	143	0	0
T12	8440	140	0	0
T13	277109	23	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	242665	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	133	0	0
T7	10531	10	0	0
T8	26919	104	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	242665	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	133	0	0
T7	10531	10	0	0
T8	26919	104	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	609836	0	0
T1	2713	8	0	0
T2	2232	15	0	0
T3	46294	197	0	0
T7	10531	10	0	0
T8	26919	113	0	0
T9	8831	163	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	169	0	0
T13	277109	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	242665	0	0
T1	2713	8	0	0
T2	2232	14	0	0
T3	46294	133	0	0
T7	10531	10	0	0
T8	26919	104	0	0
T9	8831	151	0	0
T10	2221	11	0	0
T11	16085	142	0	0
T12	8440	154	0	0
T13	277109	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	200934	0	0
GntImpliesValid_A	415890009	200934	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	200934	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2778960	0	0
ReadyAndValidImplyGrant_A	415890009	200934	0	0
ReqAndReadyImplyGrant_A	415890009	200934	0	0
ReqImpliesValid_A	415890009	515283	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	200934	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	200934	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	128	0	0
T7	10531	10	0	0
T8	26919	82	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	200934	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	128	0	0
T7	10531	10	0	0
T8	26919	82	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	200934	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	128	0	0
T7	10531	10	0	0
T8	26919	82	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2778960	0	0
T1	2713	14	0	0
T2	2232	16	0	0
T3	46294	967	0	0
T7	10531	78	0	0
T8	26919	564	0	0
T9	8831	165	0	0
T10	2221	10	0	0
T11	16085	162	0	0
T12	8440	95	0	0
T13	277109	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	200934	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	128	0	0
T7	10531	10	0	0
T8	26919	82	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	200934	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	128	0	0
T7	10531	10	0	0
T8	26919	82	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	515283	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	191	0	0
T7	10531	10	0	0
T8	26919	110	0	0
T9	8831	180	0	0
T10	2221	9	0	0
T11	16085	163	0	0
T12	8440	100	0	0
T13	277109	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	200934	0	0
T1	2713	13	0	0
T2	2232	15	0	0
T3	46294	128	0	0
T7	10531	10	0	0
T8	26919	82	0	0
T9	8831	172	0	0
T10	2221	9	0	0
T11	16085	162	0	0
T12	8440	97	0	0
T13	277109	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	210475	0	0
GntImpliesValid_A	415890009	210475	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	210475	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2806940	0	0
ReadyAndValidImplyGrant_A	415890009	210475	0	0
ReqAndReadyImplyGrant_A	415890009	210475	0	0
ReqImpliesValid_A	415890009	553517	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	210475	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210475	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	105	0	0
T7	10531	14	0	0
T8	26919	60	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210475	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	105	0	0
T7	10531	14	0	0
T8	26919	60	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210475	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	105	0	0
T7	10531	14	0	0
T8	26919	60	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2806940	0	0
T1	2713	14	0	0
T2	2232	14	0	0
T3	46294	856	0	0
T7	10531	102	0	0
T8	26919	390	0	0
T9	8831	134	0	0
T10	2221	12	0	0
T11	16085	165	0	0
T12	8440	79	0	0
T13	277109	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210475	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	105	0	0
T7	10531	14	0	0
T8	26919	60	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210475	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	105	0	0
T7	10531	14	0	0
T8	26919	60	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	553517	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	145	0	0
T7	10531	14	0	0
T8	26919	88	0	0
T9	8831	143	0	0
T10	2221	11	0	0
T11	16085	168	0	0
T12	8440	86	0	0
T13	277109	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210475	0	0
T1	2713	13	0	0
T2	2232	13	0	0
T3	46294	105	0	0
T7	10531	14	0	0
T8	26919	60	0	0
T9	8831	138	0	0
T10	2221	11	0	0
T11	16085	166	0	0
T12	8440	82	0	0
T13	277109	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	205170	0	0
GntImpliesValid_A	415890009	205170	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	205170	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2823152	0	0
ReadyAndValidImplyGrant_A	415890009	205170	0	0
ReqAndReadyImplyGrant_A	415890009	205170	0	0
ReqImpliesValid_A	415890009	514331	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	205170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205170	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	147	0	0
T7	10531	9	0	0
T8	26919	63	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205170	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	147	0	0
T7	10531	9	0	0
T8	26919	63	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205170	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	147	0	0
T7	10531	9	0	0
T8	26919	63	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2823152	0	0
T1	2713	11	0	0
T2	2232	10	0	0
T3	46294	1204	0	0
T7	10531	77	0	0
T8	26919	443	0	0
T9	8831	119	0	0
T10	2221	18	0	0
T11	16085	155	0	0
T12	8440	73	0	0
T13	277109	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205170	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	147	0	0
T7	10531	9	0	0
T8	26919	63	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205170	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	147	0	0
T7	10531	9	0	0
T8	26919	63	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	514331	0	0
T1	2713	12	0	0
T2	2232	9	0	0
T3	46294	203	0	0
T7	10531	22	0	0
T8	26919	73	0	0
T9	8831	132	0	0
T10	2221	21	0	0
T11	16085	156	0	0
T12	8440	78	0	0
T13	277109	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	205170	0	0
T1	2713	11	0	0
T2	2232	9	0	0
T3	46294	147	0	0
T7	10531	9	0	0
T8	26919	63	0	0
T9	8831	125	0	0
T10	2221	19	0	0
T11	16085	155	0	0
T12	8440	75	0	0
T13	277109	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	210213	0	0
GntImpliesValid_A	415890009	210213	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	210213	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2779974	0	0
ReadyAndValidImplyGrant_A	415890009	210213	0	0
ReqAndReadyImplyGrant_A	415890009	210213	0	0
ReqImpliesValid_A	415890009	559123	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	210213	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210213	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	117	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210213	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	117	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210213	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	117	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2779974	0	0
T1	2713	15	0	0
T2	2232	15	0	0
T3	46294	794	0	0
T7	10531	65	0	0
T8	26919	465	0	0
T9	8831	119	0	0
T10	2221	10	0	0
T11	16085	152	0	0
T12	8440	92	0	0
T13	277109	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210213	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	117	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210213	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	117	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	559123	0	0
T1	2713	14	0	0
T2	2232	16	0	0
T3	46294	148	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	126	0	0
T10	2221	13	0	0
T11	16085	151	0	0
T12	8440	95	0	0
T13	277109	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	210213	0	0
T1	2713	14	0	0
T2	2232	15	0	0
T3	46294	117	0	0
T7	10531	8	0	0
T8	26919	64	0	0
T9	8831	122	0	0
T10	2221	11	0	0
T11	16085	151	0	0
T12	8440	93	0	0
T13	277109	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	219685	0	0
GntImpliesValid_A	415890009	219685	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	219685	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	2849930	0	0
ReadyAndValidImplyGrant_A	415890009	219685	0	0
ReqAndReadyImplyGrant_A	415890009	219685	0	0
ReqImpliesValid_A	415890009	619591	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	0	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	219685	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	219685	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	142	0	0
T7	10531	4	0	0
T8	26919	64	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	219685	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	142	0	0
T7	10531	4	0	0
T8	26919	64	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	219685	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	142	0	0
T7	10531	4	0	0
T8	26919	64	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2849930	0	0
T1	2713	17	0	0
T2	2232	17	0	0
T3	46294	1001	0	0
T7	10531	18	0	0
T8	26919	418	0	0
T9	8831	133	0	0
T10	2221	15	0	0
T11	16085	181	0	0
T12	8440	84	0	0
T13	277109	30	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	219685	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	142	0	0
T7	10531	4	0	0
T8	26919	64	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	219685	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	142	0	0
T7	10531	4	0	0
T8	26919	64	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	619591	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	234	0	0
T7	10531	4	0	0
T8	26919	88	0	0
T9	8831	148	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	89	0	0
T13	277109	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	219685	0	0
T1	2713	16	0	0
T2	2232	16	0	0
T3	46294	142	0	0
T7	10531	4	0	0
T8	26919	64	0	0
T9	8831	140	0	0
T10	2221	14	0	0
T11	16085	180	0	0
T12	8440	86	0	0
T13	277109	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	867840	0	0
GntImpliesValid_A	415890009	867840	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	867840	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	10799612	0	0
ReadyAndValidImplyGrant_A	415890009	867840	0	0
ReqAndReadyImplyGrant_A	415890009	867840	0	0
ReqImpliesValid_A	415890009	2272946	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	18606	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	867840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	867840	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	509	0	0
T7	10531	55	0	0
T8	26919	233	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	867840	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	509	0	0
T7	10531	55	0	0
T8	26919	233	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	867840	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	509	0	0
T7	10531	55	0	0
T8	26919	233	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	10799612	0	0
T1	2713	1	0	0
T2	2232	1	0	0
T3	46294	2881	0	0
T7	10531	325	0	0
T8	26919	1482	0	0
T9	8831	1	0	0
T10	2221	1	0	0
T11	16085	1	0	0
T12	8440	1	0	0
T13	277109	208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	867840	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	509	0	0
T7	10531	55	0	0
T8	26919	233	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	867840	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	509	0	0
T7	10531	55	0	0
T8	26919	233	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	2272946	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	805	0	0
T7	10531	86	0	0
T8	26919	363	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	18606	0	900
T7	10531	0	0	1
T8	26919	0	0	1
T9	8831	9	0	1
T10	2221	0	0	1
T11	16085	12	0	1
T12	8440	3	0	1
T13	277109	0	0	1
T14	3945	3	0	1
T15	3512	5	0	1
T16	0	11	0	0
T17	0	4	0	0
T19	0	2	0	0
T20	0	21	0	0
T21	0	52	0	0
T22	406736	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	867840	0	0
T1	2713	55	0	0
T2	2232	38	0	0
T3	46294	509	0	0
T7	10531	55	0	0
T8	26919	233	0	0
T9	8831	560	0	0
T10	2221	61	0	0
T11	16085	588	0	0
T12	8440	371	0	0
T13	277109	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415890009	415772306	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415890009	843377	0	0
GntImpliesValid_A	415890009	843377	0	0
GrantKnown_A	415890009	415772306	0	0
IdxKnown_A	415890009	415772306	0	0
IndexIsCorrect_A	415890009	843377	0	0
LockArbDecision_A	415890009	0	0	0
NoReadyValidNoGrant_A	415890009	348820633	0	0
ReadyAndValidImplyGrant_A	415890009	843377	0	0
ReqAndReadyImplyGrant_A	415890009	843377	0	0
ReqImpliesValid_A	415890009	12272039	0	0
ReqStaysHighUntilGranted0_M	415890009	0	0	0
RoundRobin_A	415890009	21967	0	900
ValidKnown_A	415890009	415772306	0	0
gen_data_port_assertion.DataFlow_A	415890009	843377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	843377	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	493	0	0
T7	10531	56	0	0
T8	26919	221	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	843377	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	493	0	0
T7	10531	56	0	0
T8	26919	221	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	843377	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	493	0	0
T7	10531	56	0	0
T8	26919	221	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	348820633	0	0
T1	2713	1	0	0
T2	2232	1	0	0
T3	46294	38571	0	0
T7	10531	9124	0	0
T8	26919	22390	0	0
T9	8831	1	0	0
T10	2221	1	0	0
T11	16085	1	0	0
T12	8440	1	0	0
T13	277109	230539	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	843377	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	493	0	0
T7	10531	56	0	0
T8	26919	221	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	843377	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	493	0	0
T7	10531	56	0	0
T8	26919	221	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	12272039	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	3908	0	0
T7	10531	450	0	0
T8	26919	1682	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	300	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	21967	0	900
T3	46294	1	0	1
T7	10531	0	0	1
T8	26919	0	0	1
T9	8831	17	0	1
T10	2221	0	0	1
T11	16085	10	0	1
T12	8440	4	0	1
T13	277109	0	0	1
T14	3945	3	0	1
T15	0	1	0	0
T16	0	14	0	0
T17	0	7	0	0
T18	0	1	0	0
T19	0	12	0	0
T22	406736	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	415772306	0	0
T1	2713	2627	0	0
T2	2232	2202	0	0
T3	46294	46210	0	0
T7	10531	10457	0	0
T8	26919	26887	0	0
T9	8831	8800	0	0
T10	2221	2150	0	0
T11	16085	16060	0	0
T12	8440	8387	0	0
T13	277109	277026	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415890009	843377	0	0
T1	2713	57	0	0
T2	2232	45	0	0
T3	46294	493	0	0
T7	10531	56	0	0
T8	26919	221	0	0
T9	8831	538	0	0
T10	2221	46	0	0
T11	16085	638	0	0
T12	8440	368	0	0
T13	277109	65	0	0