Unified Coverage Report :: Module :: tlul_socket_m1

Module : tlul_socket_m1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28	95.96	100.00	87.88				100.00
tb.dut.u_sm1_29	95.96	100.00	87.88				100.00
tb.dut.u_sm1_31	95.96	100.00	87.88				100.00
tb.dut.u_sm1_33	96.97	100.00	90.91				100.00
tb.dut.u_sm1_34	96.97	100.00	90.91				100.00
tb.dut.u_sm1_36	96.97	100.00	90.91				100.00
tb.dut.u_sm1_38	96.97	100.00	90.91				100.00
tb.dut.u_sm1_40	96.97	100.00	90.91				100.00
tb.dut.u_sm1_42	96.97	100.00	90.91				100.00
tb.dut.u_sm1_43	96.97	100.00	90.91				100.00
tb.dut.u_sm1_44	96.97	100.00	90.91				100.00
tb.dut.u_sm1_45	96.97	100.00	90.91				100.00
tb.dut.u_sm1_46	96.97	100.00	90.91				100.00
tb.dut.u_sm1_47	96.97	100.00	90.91				100.00
tb.dut.u_sm1_48	96.97	100.00	90.91				100.00
tb.dut.u_sm1_49	96.97	100.00	90.91				100.00
tb.dut.u_sm1_50	96.97	100.00	90.91				100.00
tb.dut.u_sm1_51	96.97	100.00	90.91				100.00
tb.dut.u_sm1_52	96.97	100.00	90.91				100.00
tb.dut.u_sm1_53	96.97	100.00	90.91				100.00
tb.dut.u_sm1_54	96.97	100.00	90.91				100.00
tb.dut.u_sm1_55	96.97	100.00	90.91				100.00
tb.dut.u_sm1_56	96.97	100.00	90.91				100.00
tb.dut.u_sm1_30	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sm1_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.61	98.68	85.92			92.73	97.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	92.21	97.50	82.14			89.19	100.00

---

Module Instance : tb.dut.u_sm1_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	98.68	85.07			92.59	95.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.96	100.00	87.88				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	98.68	85.07			92.59	95.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	93.62			100.00	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_sm1_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59	98.54	84.87			92.31	94.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	91.66	97.50	80.26			88.89	100.00

---

Module Instance : tb.dut.u_sm1_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.87	100.00	98.39			100.00	97.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	100.00	98.80		100.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
gen_host_fifo[0].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[1].u_hostfifo	100.00	100.00	100.00			100.00	100.00
gen_host_fifo[2].u_hostfifo	100.00	100.00	100.00			100.00	100.00
u_devicefifo	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_28

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_29

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30

SCORE	LINE
95.96	100.00

tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_33

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_34

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_36

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_38

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_40

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_42

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_43

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_44

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_45

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_46

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_47

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_48

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_49

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_50

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_51

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_52

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_53

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_54

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_55

SCORE	LINE
96.97	100.00

tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
95.96	87.88

tb.dut.u_sm1_28

SCORE	COND
95.96	87.88

tb.dut.u_sm1_29

SCORE	COND
95.96	87.88

tb.dut.u_sm1_31

SCORE	COND
100.00	100.00

tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T23
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T23
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.97	90.91

tb.dut.u_sm1_33

SCORE	COND
96.97	90.91

tb.dut.u_sm1_34

SCORE	COND
96.97	90.91

tb.dut.u_sm1_43

SCORE	COND
96.97	90.91

tb.dut.u_sm1_44

SCORE	COND
96.97	90.91

tb.dut.u_sm1_45

SCORE	COND
96.97	90.91

tb.dut.u_sm1_46

SCORE	COND
96.97	90.91

tb.dut.u_sm1_47

SCORE	COND
96.97	90.91

tb.dut.u_sm1_48

SCORE	COND
96.97	90.91

tb.dut.u_sm1_49

SCORE	COND
96.97	90.91

tb.dut.u_sm1_50

SCORE	COND
96.97	90.91

tb.dut.u_sm1_51

SCORE	COND
96.97	90.91

tb.dut.u_sm1_52

SCORE	COND
96.97	90.91

tb.dut.u_sm1_53

SCORE	COND
96.97	90.91

tb.dut.u_sm1_54

SCORE	COND
96.97	90.91

tb.dut.u_sm1_55

SCORE	COND
96.97	90.91

tb.dut.u_sm1_56

SCORE	COND
96.97	90.91

tb.dut.u_sm1_36

SCORE	COND
96.97	90.91

tb.dut.u_sm1_38

SCORE	COND
96.97	90.91

tb.dut.u_sm1_40

SCORE	COND
96.97	90.91

tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T9
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_m1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	2147483647	24417077	0	0
gen_host_fifo[1].idInRange	2147483647	13430757	0	0
gen_host_fifo[2].idInRange	1682908836	4089871	0	0
maxM	21600	21600	0	0
rspIdInRange	2147483647	172893711	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24417077	0	0
T1	56880	377	0	0
T2	246624	5141	0	0
T3	37968	281	0	0
T7	283392	733	0	0
T8	319680	871	0	0
T10	54600	252	0	0
T11	38976	255	0	0
T12	43656	404	0	0
T13	61848	621	0	0
T14	61776	715	0	0
T22	0	74	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13430757	0	0
T1	56880	125	0	0
T2	246624	2482	0	0
T3	37968	167	0	0
T7	283392	261	0	0
T8	319680	296	0	0
T9	0	6067	0	0
T10	54600	161	0	0
T11	38976	113	0	0
T12	43656	158	0	0
T13	61848	401	0	0
T14	61776	420	0	0
T22	0	40	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682908836	4089871	0	0
T1	7110	12	0	0
T2	41104	403	0	0
T3	6328	29	0	0
T7	47232	33	0	0
T8	53280	81	0	0
T9	16481	0	0	0
T10	9100	30	0	0
T11	6496	15	0	0
T12	7276	25	0	0
T13	10308	51	0	0
T14	10296	79	0	0
T22	0	151	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0
T14	24	24	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	172893711	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	1892	0	0
T8	319680	2791	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

Line Coverage for Instance : tb.dut.u_sm1_28

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	1816032	0	0
gen_host_fifo[1].idInRange	420727209	469575	0	0
gen_host_fifo[2].idInRange	420727209	601859	0	0
maxM	900	900	0	0
rspIdInRange	420727209	22446248	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1816032	0	0
T1	2370	46	0	0
T2	10276	631	0	0
T3	1582	19	0	0
T7	11808	81	0	0
T8	13320	48	0	0
T10	2275	28	0	0
T11	1624	25	0	0
T12	1819	45	0	0
T13	2577	57	0	0
T14	2574	117	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	469575	0	0
T1	2370	5	0	0
T2	10276	120	0	0
T3	1582	1	0	0
T7	11808	6	0	0
T8	13320	4	0	0
T9	0	6067	0	0
T10	2275	0	0	0
T11	1624	3	0	0
T12	1819	5	0	0
T13	2577	11	0	0
T14	2574	16	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	601859	0	0
T1	2370	6	0	0
T2	10276	113	0	0
T3	1582	5	0	0
T7	11808	3	0	0
T8	13320	11	0	0
T10	2275	6	0	0
T11	1624	5	0	0
T12	1819	7	0	0
T13	2577	13	0	0
T14	2574	20	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	22446248	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	357	0	0
T8	13320	440	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

Line Coverage for Instance : tb.dut.u_sm1_29

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_29

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	1988894	0	0
gen_host_fifo[1].idInRange	420727209	510945	0	0
gen_host_fifo[2].idInRange	420727209	653655	0	0
maxM	900	900	0	0
rspIdInRange	420727209	22030419	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1988894	0	0
T1	2370	41	0	0
T2	10276	821	0	0
T3	1582	48	0	0
T7	11808	46	0	0
T8	13320	87	0	0
T10	2275	46	0	0
T11	1624	40	0	0
T12	1819	78	0	0
T13	2577	72	0	0
T14	2574	109	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	510945	0	0
T1	2370	6	0	0
T2	10276	134	0	0
T3	1582	8	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	6	0	0
T11	1624	6	0	0
T12	1819	6	0	0
T13	2577	13	0	0
T14	2574	13	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	653655	0	0
T1	2370	3	0	0
T2	10276	107	0	0
T3	1582	6	0	0
T7	11808	6	0	0
T8	13320	4	0	0
T10	2275	9	0	0
T11	1624	3	0	0
T12	1819	6	0	0
T13	2577	13	0	0
T14	2574	22	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	22030419	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	298	0	0
T8	13320	511	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_31

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_31

	Total	Covered	Percent
Conditions	33	29	87.88
Logical	33	29	87.88
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	1906344	0	0
gen_host_fifo[1].idInRange	420727209	498087	0	0
gen_host_fifo[2].idInRange	420727209	657510	0	0
maxM	900	900	0	0
rspIdInRange	420727209	20737897	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1906344	0	0
T1	2370	48	0	0
T2	10276	789	0	0
T3	1582	36	0	0
T7	11808	67	0	0
T8	13320	72	0	0
T10	2275	31	0	0
T11	1624	34	0	0
T12	1819	39	0	0
T13	2577	66	0	0
T14	2574	116	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	498087	0	0
T1	2370	4	0	0
T2	10276	150	0	0
T3	1582	5	0	0
T7	11808	10	0	0
T8	13320	3	0	0
T10	2275	5	0	0
T11	1624	4	0	0
T12	1819	3	0	0
T13	2577	7	0	0
T14	2574	14	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	657510	0	0
T1	2370	3	0	0
T2	10276	82	0	0
T3	1582	6	0	0
T7	11808	5	0	0
T8	13320	9	0	0
T10	2275	9	0	0
T11	1624	4	0	0
T12	1819	7	0	0
T13	2577	11	0	0
T14	2574	20	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	20737897	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	447	0	0
T8	13320	407	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

Line Coverage for Instance : tb.dut.u_sm1_33

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_33

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	269911	0	0
gen_host_fifo[1].idInRange	420727209	378704	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4255402	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	269911	0	0
T1	2370	12	0	0
T2	10276	122	0	0
T3	1582	3	0	0
T7	11808	12	0	0
T8	13320	1	0	0
T10	2275	4	0	0
T11	1624	4	0	0
T12	1819	7	0	0
T13	2577	12	0	0
T14	2574	9	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	378704	0	0
T1	2370	8	0	0
T2	10276	119	0	0
T3	1582	6	0	0
T7	11808	4	0	0
T8	13320	32	0	0
T10	2275	4	0	0
T11	1624	2	0	0
T12	1819	3	0	0
T13	2577	12	0	0
T14	2574	22	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4255402	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	34	0	0
T8	13320	10	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_34

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_34

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	324201	0	0
gen_host_fifo[1].idInRange	420727209	431868	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4527973	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	324201	0	0
T1	2370	7	0	0
T2	10276	111	0	0
T3	1582	4	0	0
T7	11808	3	0	0
T8	13320	7	0	0
T10	2275	3	0	0
T11	1624	4	0	0
T12	1819	10	0	0
T13	2577	16	0	0
T14	2574	14	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	431868	0	0
T1	2370	1	0	0
T2	10276	93	0	0
T3	1582	12	0	0
T7	11808	13	0	0
T8	13320	1	0	0
T10	2275	8	0	0
T11	1624	6	0	0
T12	1819	8	0	0
T13	2577	21	0	0
T14	2574	14	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4527973	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	20	0	0
T8	13320	67	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_36

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_36

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T26,T27
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	609612	0	0
gen_host_fifo[1].idInRange	420727209	747616	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4106552	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	609612	0	0
T1	2370	4	0	0
T2	10276	152	0	0
T3	1582	13	0	0
T7	11808	3	0	0
T8	13320	0	0	0
T10	2275	13	0	0
T11	1624	5	0	0
T12	1819	9	0	0
T13	2577	6	0	0
T14	2574	10	0	0
T22	0	74	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	747616	0	0
T1	2370	12	0	0
T2	10276	125	0	0
T3	1582	18	0	0
T7	11808	10	0	0
T8	13320	34	0	0
T10	2275	11	0	0
T11	1624	13	0	0
T12	1819	5	0	0
T13	2577	8	0	0
T14	2574	20	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4106552	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	31	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_38

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_38

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T20,T28
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	786324	0	0
gen_host_fifo[1].idInRange	420727209	952666	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4809179	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	786324	0	0
T1	2370	22	0	0
T2	10276	157	0	0
T3	1582	19	0	0
T7	11808	5	0	0
T8	13320	9	0	0
T10	2275	16	0	0
T11	1624	5	0	0
T12	1819	4	0	0
T13	2577	29	0	0
T14	2574	16	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	952666	0	0
T1	2370	2	0	0
T2	10276	143	0	0
T3	1582	6	0	0
T7	11808	18	0	0
T8	13320	44	0	0
T10	2275	15	0	0
T11	1624	7	0	0
T12	1819	39	0	0
T13	2577	49	0	0
T14	2574	14	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4809179	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	18	0	0
T8	13320	73	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_40

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_40

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	601384	0	0
gen_host_fifo[1].idInRange	420727209	758169	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4683999	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	601384	0	0
T1	2370	17	0	0
T2	10276	100	0	0
T3	1582	3	0	0
T7	11808	80	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	3	0	0
T12	1819	8	0	0
T13	2577	10	0	0
T14	2574	19	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	758169	0	0
T1	2370	3	0	0
T2	10276	101	0	0
T3	1582	2	0	0
T7	11808	7	0	0
T8	13320	5	0	0
T10	2275	4	0	0
T11	1624	2	0	0
T12	1819	4	0	0
T13	2577	11	0	0
T14	2574	17	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4683999	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	90	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_42

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_42

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	773196	0	0
gen_host_fifo[1].idInRange	420727209	927149	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4558392	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	773196	0	0
T1	2370	8	0	0
T2	10276	123	0	0
T3	1582	7	0	0
T7	11808	2	0	0
T8	13320	109	0	0
T10	2275	11	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	122	0	0
T14	2574	12	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	927149	0	0
T1	2370	4	0	0
T2	10276	106	0	0
T3	1582	11	0	0
T7	11808	6	0	0
T8	13320	2	0	0
T10	2275	8	0	0
T11	1624	3	0	0
T12	1819	4	0	0
T13	2577	77	0	0
T14	2574	28	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4558392	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	85	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_43

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_43

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	288152	0	0
gen_host_fifo[1].idInRange	420727209	379263	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4395085	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	288152	0	0
T1	2370	6	0	0
T2	10276	94	0	0
T3	1582	4	0	0
T7	11808	9	0	0
T8	13320	7	0	0
T10	2275	7	0	0
T11	1624	7	0	0
T12	1819	7	0	0
T13	2577	9	0	0
T14	2574	13	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	379263	0	0
T1	2370	9	0	0
T2	10276	95	0	0
T3	1582	7	0	0
T7	11808	4	0	0
T8	13320	11	0	0
T10	2275	2	0	0
T11	1624	2	0	0
T12	1819	4	0	0
T13	2577	9	0	0
T14	2574	22	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4395085	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	49	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_44

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_44

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	324369	0	0
gen_host_fifo[1].idInRange	420727209	439270	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4151450	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	324369	0	0
T1	2370	13	0	0
T2	10276	101	0	0
T3	1582	4	0	0
T7	11808	10	0	0
T8	13320	28	0	0
T10	2275	5	0	0
T11	1624	9	0	0
T12	1819	12	0	0
T13	2577	11	0	0
T14	2574	8	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	439270	0	0
T1	2370	6	0	0
T2	10276	85	0	0
T3	1582	7	0	0
T7	11808	5	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	3	0	0
T12	1819	4	0	0
T13	2577	12	0	0
T14	2574	7	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4151450	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	143	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_45

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_45

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	330568	0	0
gen_host_fifo[1].idInRange	420727209	442464	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3870383	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	330568	0	0
T1	2370	10	0	0
T2	10276	116	0	0
T3	1582	16	0	0
T7	11808	32	0	0
T8	13320	5	0	0
T10	2275	3	0	0
T11	1624	7	0	0
T12	1819	10	0	0
T13	2577	16	0	0
T14	2574	21	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	442464	0	0
T1	2370	4	0	0
T2	10276	91	0	0
T3	1582	8	0	0
T7	11808	8	0	0
T8	13320	8	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	7	0	0
T13	2577	8	0	0
T14	2574	18	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3870383	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	44	0	0
T8	13320	37	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_46

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_46

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	318818	0	0
gen_host_fifo[1].idInRange	420727209	426933	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3797589	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	318818	0	0
T1	2370	16	0	0
T2	10276	77	0	0
T3	1582	7	0	0
T7	11808	9	0	0
T8	13320	9	0	0
T10	2275	10	0	0
T11	1624	5	0	0
T12	1819	6	0	0
T13	2577	9	0	0
T14	2574	16	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	426933	0	0
T1	2370	4	0	0
T2	10276	81	0	0
T3	1582	8	0	0
T7	11808	11	0	0
T8	13320	7	0	0
T10	2275	10	0	0
T11	1624	4	0	0
T12	1819	4	0	0
T13	2577	16	0	0
T14	2574	20	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3797589	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	24	0	0
T8	13320	85	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_47

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_47

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	284496	0	0
gen_host_fifo[1].idInRange	420727209	393278	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3837145	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	284496	0	0
T1	2370	11	0	0
T2	10276	115	0	0
T3	1582	7	0	0
T7	11808	11	0	0
T8	13320	3	0	0
T10	2275	5	0	0
T11	1624	5	0	0
T12	1819	9	0	0
T13	2577	16	0	0
T14	2574	10	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	393278	0	0
T1	2370	6	0	0
T2	10276	94	0	0
T3	1582	5	0	0
T7	11808	7	0	0
T8	13320	4	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	4	0	0
T13	2577	14	0	0
T14	2574	13	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3837145	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	27	0	0
T8	13320	21	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_48

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_48

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T22,T24
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	308059	0	0
gen_host_fifo[1].idInRange	420727209	418920	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4271955	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	308059	0	0
T1	2370	13	0	0
T2	10276	123	0	0
T3	1582	3	0	0
T7	11808	3	0	0
T8	13320	4	0	0
T10	2275	2	0	0
T11	1624	3	0	0
T12	1819	5	0	0
T13	2577	13	0	0
T14	2574	18	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	418920	0	0
T1	2370	2	0	0
T2	10276	83	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	4	0	0
T10	2275	7	0	0
T11	1624	2	0	0
T12	1819	6	0	0
T13	2577	9	0	0
T14	2574	16	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4271955	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	28	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_49

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_49

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	296579	0	0
gen_host_fifo[1].idInRange	420727209	389804	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4430035	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	296579	0	0
T1	2370	7	0	0
T2	10276	121	0	0
T3	1582	5	0	0
T7	11808	7	0	0
T8	13320	20	0	0
T10	2275	6	0	0
T11	1624	8	0	0
T12	1819	3	0	0
T13	2577	9	0	0
T14	2574	13	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	389804	0	0
T1	2370	4	0	0
T2	10276	108	0	0
T3	1582	5	0	0
T7	11808	11	0	0
T8	13320	13	0	0
T10	2275	8	0	0
T11	1624	4	0	0
T12	1819	6	0	0
T13	2577	15	0	0
T14	2574	21	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4430035	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	23	0	0
T8	13320	65	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_50

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_50

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T9,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	297671	0	0
gen_host_fifo[1].idInRange	420727209	402858	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3956140	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	297671	0	0
T1	2370	11	0	0
T2	10276	106	0	0
T3	1582	7	0	0
T7	11808	10	0	0
T8	13320	8	0	0
T10	2275	1	0	0
T11	1624	6	0	0
T12	1819	4	0	0
T13	2577	22	0	0
T14	2574	6	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	402858	0	0
T1	2370	2	0	0
T2	10276	78	0	0
T3	1582	8	0	0
T7	11808	18	0	0
T8	13320	14	0	0
T10	2275	9	0	0
T11	1624	8	0	0
T12	1819	7	0	0
T13	2577	9	0	0
T14	2574	11	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3956140	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	30	0	0
T8	13320	59	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_51

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_51

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T12,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	343456	0	0
gen_host_fifo[1].idInRange	420727209	471248	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3931698	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	343456	0	0
T1	2370	12	0	0
T2	10276	100	0	0
T3	1582	7	0	0
T7	11808	6	0	0
T8	13320	4	0	0
T10	2275	3	0	0
T11	1624	6	0	0
T12	1819	17	0	0
T13	2577	8	0	0
T14	2574	20	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	471248	0	0
T1	2370	3	0	0
T2	10276	96	0	0
T3	1582	5	0	0
T7	11808	15	0	0
T8	13320	0	0	0
T10	2275	7	0	0
T11	1624	4	0	0
T12	1819	12	0	0
T13	2577	9	0	0
T14	2574	26	0	0
T22	0	40	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3931698	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	30	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_52

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_52

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	307111	0	0
gen_host_fifo[1].idInRange	420727209	434432	0	0
maxM	900	900	0	0
rspIdInRange	420727209	5183302	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	307111	0	0
T1	2370	8	0	0
T2	10276	99	0	0
T3	1582	8	0	0
T7	11808	9	0	0
T8	13320	5	0	0
T10	2275	7	0	0
T11	1624	9	0	0
T12	1819	7	0	0
T13	2577	11	0	0
T14	2574	17	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	434432	0	0
T1	2370	8	0	0
T2	10276	110	0	0
T3	1582	9	0	0
T7	11808	10	0	0
T8	13320	4	0	0
T10	2275	6	0	0
T11	1624	5	0	0
T12	1819	6	0	0
T13	2577	20	0	0
T14	2574	25	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	5183302	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	22	0	0
T8	13320	45	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_53

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_53

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	306483	0	0
gen_host_fifo[1].idInRange	420727209	410437	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4313144	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	306483	0	0
T1	2370	3	0	0
T2	10276	91	0	0
T3	1582	5	0	0
T7	11808	12	0	0
T8	13320	1	0	0
T10	2275	3	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	9	0	0
T14	2574	16	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	410437	0	0
T1	2370	7	0	0
T2	10276	85	0	0
T3	1582	5	0	0
T7	11808	2	0	0
T8	13320	5	0	0
T10	2275	2	0	0
T11	1624	3	0	0
T12	1819	4	0	0
T13	2577	16	0	0
T14	2574	8	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4313144	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	30	0	0
T8	13320	13	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_54

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_54

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	287165	0	0
gen_host_fifo[1].idInRange	420727209	374828	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3899052	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	287165	0	0
T1	2370	8	0	0
T2	10276	105	0	0
T3	1582	5	0	0
T7	11808	6	0	0
T8	13320	2	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	9	0	0
T13	2577	15	0	0
T14	2574	10	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	374828	0	0
T1	2370	5	0	0
T2	10276	96	0	0
T3	1582	6	0	0
T7	11808	12	0	0
T8	13320	12	0	0
T10	2275	9	0	0
T11	1624	2	0	0
T12	1819	3	0	0
T13	2577	17	0	0
T14	2574	21	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3899052	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	14	0	0
T8	13320	25	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_55

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_55

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T12,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	265000	0	0
gen_host_fifo[1].idInRange	420727209	354293	0	0
maxM	900	900	0	0
rspIdInRange	420727209	3719756	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	265000	0	0
T1	2370	5	0	0
T2	10276	121	0	0
T3	1582	9	0	0
T7	11808	6	0	0
T8	13320	4	0	0
T10	2275	5	0	0
T11	1624	4	0	0
T12	1819	18	0	0
T13	2577	7	0	0
T14	2574	13	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	354293	0	0
T1	2370	5	0	0
T2	10276	90	0	0
T3	1582	8	0	0
T7	11808	11	0	0
T8	13320	12	0	0
T10	2275	6	0	0
T11	1624	7	0	0
T12	1819	5	0	0
T13	2577	8	0	0
T14	2574	17	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3719756	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	25	0	0
T8	13320	23	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_56

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         2/2              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        2/2              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        2/2              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        2/2              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        2/2              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        2/2              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        2/2              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_56

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T22
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	275399	0	0
gen_host_fifo[1].idInRange	420727209	373776	0	0
maxM	900	900	0	0
rspIdInRange	420727209	4155965	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	275399	0	0
T1	2370	9	0	0
T2	10276	132	0	0
T3	1582	4	0	0
T7	11808	11	0	0
T8	13320	8	0	0
T10	2275	7	0	0
T11	1624	5	0	0
T12	1819	8	0	0
T13	2577	12	0	0
T14	2574	12	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	373776	0	0
T1	2370	2	0	0
T2	10276	106	0	0
T3	1582	5	0	0
T7	11808	9	0	0
T8	13320	3	0	0
T10	2275	4	0	0
T11	1624	3	0	0
T12	1819	4	0	0
T13	2577	14	0	0
T14	2574	21	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4155965	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	37	0	0
T8	13320	86	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_30

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00

95                          assign reqid_sub = i;   // can cause conversion error?
96         3/3              assign shifted_id = {
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
97                            tl_h_i[i].a_source[0+:(IDW-STIDW)],
98                            reqid_sub
99                          };
100                     
101                       `ASSERT(idInRange, tl_h_i[i].a_valid |-> tl_h_i[i].a_source[IDW-1 -:STIDW] == '0)
102                     
103                         // assign not connected bits to nc_* signal to make lint happy
104                         logic [IDW-1 : IDW-STIDW] unused_tl_h_source;
105        3/3              assign unused_tl_h_source = tl_h_i[i].a_source[IDW-1 -: STIDW];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                     
107                         // Put shifted ID
108        3/3              assign hreq_fifo_i = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
109                           a_valid:    tl_h_i[i].a_valid,
110                           a_opcode:   tl_h_i[i].a_opcode,
111                           a_param:    tl_h_i[i].a_param,
112                           a_size:     tl_h_i[i].a_size,
113                           a_source:   shifted_id,
114                           a_address:  tl_h_i[i].a_address,
115                           a_mask:     tl_h_i[i].a_mask,
116                           a_data:     tl_h_i[i].a_data,
117                           a_user:     tl_h_i[i].a_user,
118                           d_ready:    tl_h_i[i].d_ready
119                         };
120                     
121                         tlul_fifo_sync #(
122                           .ReqPass    (HReqPass[i]),
123                           .RspPass    (HRspPass[i]),
124                           .ReqDepth   (HReqDepth[i*4+:4]),
125                           .RspDepth   (HRspDepth[i*4+:4]),
126                           .SpareReqW  (1)
127                         ) u_hostfifo (
128                           .clk_i,
129                           .rst_ni,
130                           .tl_h_i      (hreq_fifo_i),
131                           .tl_h_o      (tl_h_o[i]),
132                           .tl_d_o      (hreq_fifo_o[i]),
133                           .tl_d_i      (hrsp_fifo_i[i]),
134                           .spare_req_i (1'b0),
135                           .spare_req_o (),
136                           .spare_rsp_i (1'b0),
137                           .spare_rsp_o ()
138                         );
139                       end
140                     
141                       // Device Req/Rsp FIFO
142                       tlul_fifo_sync #(
143                         .ReqPass    (DReqPass),
144                         .RspPass    (DRspPass),
145                         .ReqDepth   (DReqDepth),
146                         .RspDepth   (DRspDepth),
147                         .SpareReqW  (1)
148                       ) u_devicefifo (
149                         .clk_i,
150                         .rst_ni,
151                         .tl_h_i      (dreq_fifo_i),
152                         .tl_h_o      (drsp_fifo_o),
153                         .tl_d_o      (tl_d_o),
154                         .tl_d_i      (tl_d_i),
155                         .spare_req_i (1'b0),
156                         .spare_req_o (),
157                         .spare_rsp_i (1'b0),
158                         .spare_rsp_o ()
159                       );
160                     
161                       // Request Arbiter
162                       for (genvar i = 0 ; i < M ; i++) begin : gen_arbreqgnt
163        3/3              assign hrequest[i] = hreq_fifo_o[i].a_valid;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164                       end
165                     
166        1/1            assign arb_ready = drsp_fifo_o.a_ready;
           Tests:       T1 T2 T3 
167                     
168                       if (tlul_pkg::ArbiterImpl == "PPC") begin : gen_arb_ppc
169                         prim_arbiter_ppc #(
170                           .N          (M),
171                           .DW         ($bits(tlul_pkg::tl_h2d_t))
172                         ) u_reqarb (
173                           .clk_i,
174                           .rst_ni,
175                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
176                           .req_i     ( hrequest    ),
177                           .data_i    ( hreq_fifo_o ),
178                           .gnt_o     ( hgrant      ),
179                           .idx_o     (             ),
180                           .valid_o   ( arb_valid   ),
181                           .data_o    ( arb_data    ),
182                           .ready_i   ( arb_ready   )
183                         );
184                       end else if (tlul_pkg::ArbiterImpl == "BINTREE") begin : gen_tree_arb
185                         prim_arbiter_tree #(
186                           .N          (M),
187                           .DW         ($bits(tlul_pkg::tl_h2d_t))
188                         ) u_reqarb (
189                           .clk_i,
190                           .rst_ni,
191                           .req_chk_i ( 1'b0        ), // TL-UL allows dropping valid without ready. See #3354.
192                           .req_i     ( hrequest    ),
193                           .data_i    ( hreq_fifo_o ),
194                           .gnt_o     ( hgrant      ),
195                           .idx_o     (             ),
196                           .valid_o   ( arb_valid   ),
197                           .data_o    ( arb_data    ),
198                           .ready_i   ( arb_ready   )
199                         );
200                       end else begin : gen_unknown
201                         `ASSERT_INIT(UnknownArbImpl_A, 0)
202                       end
203                     
204                       logic [  M-1:0] hfifo_rspvalid;
205                       logic [  M-1:0] dfifo_rspready;
206                       logic [IDW-1:0] hfifo_rspid;
207                       logic dfifo_rspready_merged;
208                     
209                       // arb_data --> dreq_fifo_i
210                       //   dreq_fifo_i.hd_rspready <= dfifo_rspready
211                     
212        1/1            assign dfifo_rspready_merged = |dfifo_rspready;
           Tests:       T1 T2 T3 
213        1/1            assign dreq_fifo_i = '{
           Tests:       T1 T2 T3 
214                         a_valid:   arb_valid,
215                         a_opcode:  arb_data.a_opcode,
216                         a_param:   arb_data.a_param,
217                         a_size:    arb_data.a_size,
218                         a_source:  arb_data.a_source,
219                         a_address: arb_data.a_address,
220                         a_mask:    arb_data.a_mask,
221                         a_data:    arb_data.a_data,
222                         a_user:    arb_data.a_user,
223                     
224                         d_ready:   dfifo_rspready_merged
225                       };
226                     
227                       // Response ID steering
228                       // drsp_fifo_o --> hrsp_fifo_i[i]
229                     
230                       // Response ID shifting before put into host fifo
231        1/1            assign hfifo_rspid = {
           Tests:       T1 T2 T3 
232                         {STIDW{1'b0}},
233                         drsp_fifo_o.d_source[IDW-1:STIDW]
234                       };
235                       for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
236        3/3              assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
237                                                    (drsp_fifo_o.d_source[0+:STIDW] == i);
238        3/3              assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready                &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
239                                                    (drsp_fifo_o.d_source[0+:STIDW] == i) &
240                                                   drsp_fifo_o.d_valid;
241                     
242        3/3              assign hrsp_fifo_i[i] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_30

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T23
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T12
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T23
1	1	1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T23
1	1	1	Covered	T2,T3,T10

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_host_fifo[0].idInRange	420727209	11107853	0	0
gen_host_fifo[1].idInRange	420727209	2044174	0	0
gen_host_fifo[2].idInRange	420727209	2176847	0	0
maxM	900	900	0	0
rspIdInRange	420727209	22824951	0	0

gen_host_fifo[0].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	11107853	0	0
T1	2370	40	0	0
T2	10276	634	0	0
T3	1582	38	0	0
T7	11808	293	0	0
T8	13320	413	0	0
T10	2275	18	0	0
T11	1624	31	0	0
T12	1819	60	0	0
T13	2577	64	0	0
T14	2574	100	0	0

gen_host_fifo[1].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	2044174	0	0
T1	2370	13	0	0
T2	10276	93	0	0
T3	1582	1	0	0
T7	11808	43	0	0
T8	13320	64	0	0
T10	2275	7	0	0
T11	1624	4	0	0
T12	1819	5	0	0
T13	2577	16	0	0
T14	2574	16	0	0

gen_host_fifo[2].idInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	2176847	0	0
T2	10276	101	0	0
T3	1582	12	0	0
T7	11808	19	0	0
T8	13320	57	0	0
T9	16481	0	0	0
T10	2275	6	0	0
T11	1624	3	0	0
T12	1819	5	0	0
T13	2577	14	0	0
T14	2574	17	0	0
T22	0	151	0	0

maxM

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

rspIdInRange

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	22824951	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	335	0	0
T8	13320	390	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0