Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7722850	0	0
GntImpliesValid_A	2147483647	7722850	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7722850	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	468137130	0	0
ReadyAndValidImplyGrant_A	2147483647	7722850	0	0
ReqAndReadyImplyGrant_A	2147483647	7722850	0	0
ReqImpliesValid_A	2147483647	36550331	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42847	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7722850	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	56880	55200	0	0
T2	246624	246240	0	0
T3	37968	37752	0	0
T7	283392	282528	0	0
T8	319680	318456	0	0
T10	54600	52968	0	0
T11	38976	38184	0	0
T12	43656	42216	0	0
T13	61848	59880	0	0
T14	61776	61392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0
T14	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722850	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	511	0	0
T8	319680	461	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722850	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	511	0	0
T8	319680	461	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	56880	55200	0	0
T2	246624	246240	0	0
T3	37968	37752	0	0
T7	283392	282528	0	0
T8	319680	318456	0	0
T10	54600	52968	0	0
T11	38976	38184	0	0
T12	43656	42216	0	0
T13	61848	59880	0	0
T14	61776	61392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	56880	55200	0	0
T2	246624	246240	0	0
T3	37968	37752	0	0
T7	283392	282528	0	0
T8	319680	318456	0	0
T10	54600	52968	0	0
T11	38976	38184	0	0
T12	43656	42216	0	0
T13	61848	59880	0	0
T14	61776	61392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722850	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	511	0	0
T8	319680	461	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	468137130	0	0
T1	56880	615	0	0
T2	246624	6674	0	0
T3	37968	427	0	0
T7	283392	14081	0	0
T8	319680	15258	0	0
T10	54600	704	0	0
T11	38976	437	0	0
T12	43656	785	0	0
T13	61848	1567	0	0
T14	61776	1128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722850	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	511	0	0
T8	319680	461	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722850	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	511	0	0
T8	319680	461	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36550331	0	0
T1	56880	514	0	0
T2	246624	7911	0	0
T3	37968	477	0	0
T7	283392	1027	0	0
T8	319680	1248	0	0
T10	54600	443	0	0
T11	38976	383	0	0
T12	43656	587	0	0
T13	61848	1050	0	0
T14	61776	1209	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42847	0	21600
T2	20552	38	0	2
T3	3164	0	0	2
T4	0	12	0	0
T7	23616	0	0	2
T8	26640	0	0	2
T9	32962	22	0	2
T10	4550	0	0	2
T11	3248	0	0	2
T12	3638	0	0	2
T13	5154	5	0	2
T14	5148	6	0	2
T15	0	21	0	0
T16	0	481	0	0
T17	0	9	0	0
T18	0	25	0	0
T19	0	22	0	0
T20	0	2	0	0
T21	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	56880	55200	0	0
T2	246624	246240	0	0
T3	37968	37752	0	0
T7	283392	282528	0	0
T8	319680	318456	0	0
T10	54600	52968	0	0
T11	38976	38184	0	0
T12	43656	42216	0	0
T13	61848	59880	0	0
T14	61776	61392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722850	0	0
T1	56880	459	0	0
T2	246624	7026	0	0
T3	37968	414	0	0
T7	283392	511	0	0
T8	319680	461	0	0
T10	54600	388	0	0
T11	38976	346	0	0
T12	43656	519	0	0
T13	61848	788	0	0
T14	61776	1137	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	858154	0	0
GntImpliesValid_A	420727209	858154	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	858154	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	13307472	0	0
ReadyAndValidImplyGrant_A	420727209	858154	0	0
ReqAndReadyImplyGrant_A	420727209	858154	0	0
ReqImpliesValid_A	420727209	2623550	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	858154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	858154	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	56	0	0
T8	13320	59	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	858154	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	56	0	0
T8	13320	59	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	858154	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	56	0	0
T8	13320	59	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	13307472	0	0
T1	2370	33	0	0
T2	10276	571	0	0
T3	1582	35	0	0
T7	11808	410	0	0
T8	13320	483	0	0
T10	2275	38	0	0
T11	1624	28	0	0
T12	1819	59	0	0
T13	2577	56	0	0
T14	2574	109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	858154	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	56	0	0
T8	13320	59	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	858154	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	56	0	0
T8	13320	59	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	2623550	0	0
T1	2370	50	0	0
T2	10276	1026	0	0
T3	1582	62	0	0
T7	11808	65	0	0
T8	13320	95	0	0
T10	2275	61	0	0
T11	1624	49	0	0
T12	1819	90	0	0
T13	2577	97	0	0
T14	2574	144	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	858154	0	0
T1	2370	41	0	0
T2	10276	798	0	0
T3	1582	48	0	0
T7	11808	56	0	0
T8	13320	59	0	0
T10	2275	49	0	0
T11	1624	38	0	0
T12	1819	74	0	0
T13	2577	76	0	0
T14	2574	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	863764	0	0
GntImpliesValid_A	420727209	863764	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	863764	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	13342110	0	0
ReadyAndValidImplyGrant_A	420727209	863764	0	0
ReqAndReadyImplyGrant_A	420727209	863764	0	0
ReqImpliesValid_A	420727209	2600423	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	863764	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	863764	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	60	0	0
T8	13320	67	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	863764	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	60	0	0
T8	13320	67	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	863764	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	60	0	0
T8	13320	67	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	13342110	0	0
T1	2370	36	0	0
T2	10276	552	0	0
T3	1582	38	0	0
T7	11808	480	0	0
T8	13320	516	0	0
T10	2275	34	0	0
T11	1624	27	0	0
T12	1819	38	0	0
T13	2577	55	0	0
T14	2574	108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	863764	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	60	0	0
T8	13320	67	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	863764	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	60	0	0
T8	13320	67	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	2600423	0	0
T1	2370	55	0	0
T2	10276	999	0	0
T3	1582	47	0	0
T7	11808	82	0	0
T8	13320	84	0	0
T10	2275	45	0	0
T11	1624	42	0	0
T12	1819	49	0	0
T13	2577	84	0	0
T14	2574	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	863764	0	0
T1	2370	45	0	0
T2	10276	775	0	0
T3	1582	42	0	0
T7	11808	60	0	0
T8	13320	67	0	0
T10	2275	39	0	0
T11	1624	34	0	0
T12	1819	43	0	0
T13	2577	69	0	0
T14	2574	128	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	210087	0	0
GntImpliesValid_A	420727209	210087	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	210087	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3267188	0	0
ReadyAndValidImplyGrant_A	420727209	210087	0	0
ReqAndReadyImplyGrant_A	420727209	210087	0	0
ReqImpliesValid_A	420727209	553429	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	210087	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210087	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	15	0	0
T8	13320	8	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210087	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	15	0	0
T8	13320	8	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210087	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	15	0	0
T8	13320	8	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3267188	0	0
T1	2370	17	0	0
T2	10276	220	0	0
T3	1582	8	0	0
T7	11808	118	0	0
T8	13320	42	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	30	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210087	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	15	0	0
T8	13320	8	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210087	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	15	0	0
T8	13320	8	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	553429	0	0
T1	2370	20	0	0
T2	10276	241	0	0
T3	1582	9	0	0
T7	11808	16	0	0
T8	13320	33	0	0
T10	2275	8	0	0
T11	1624	6	0	0
T12	1819	10	0	0
T13	2577	24	0	0
T14	2574	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210087	0	0
T1	2370	18	0	0
T2	10276	230	0	0
T3	1582	8	0	0
T7	11808	15	0	0
T8	13320	8	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	10	0	0
T13	2577	22	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T13 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T13
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	211820	0	0
GntImpliesValid_A	420727209	211820	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	211820	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3365328	0	0
ReadyAndValidImplyGrant_A	420727209	211820	0	0
ReqAndReadyImplyGrant_A	420727209	211820	0	0
ReqImpliesValid_A	420727209	629007	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	211820	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	211820	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	14	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	211820	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	14	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	211820	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	14	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3365328	0	0
T1	2370	9	0	0
T2	10276	177	0	0
T3	1582	17	0	0
T7	11808	65	0	0
T8	13320	80	0	0
T10	2275	12	0	0
T11	1624	11	0	0
T12	1819	19	0	0
T13	2577	32	0	0
T14	2574	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	211820	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	14	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	211820	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	14	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	629007	0	0
T1	2370	8	0	0
T2	10276	202	0	0
T3	1582	16	0	0
T7	11808	16	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	37	0	0
T14	2574	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	211820	0	0
T1	2370	8	0	0
T2	10276	189	0	0
T3	1582	16	0	0
T7	11808	14	0	0
T8	13320	8	0	0
T10	2275	11	0	0
T11	1624	10	0	0
T12	1819	18	0	0
T13	2577	34	0	0
T14	2574	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	209667	0	0
GntImpliesValid_A	420727209	209667	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	209667	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	5320227	0	0
ReadyAndValidImplyGrant_A	420727209	209667	0	0
ReqAndReadyImplyGrant_A	420727209	209667	0	0
ReqImpliesValid_A	420727209	1078977	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	209667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209667	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	10	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209667	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	10	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209667	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	10	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	5320227	0	0
T1	2370	64	0	0
T2	10276	659	0	0
T3	1582	39	0	0
T7	11808	73	0	0
T8	13320	113	0	0
T10	2275	81	0	0
T11	1624	48	0	0
T12	1819	83	0	0
T13	2577	235	0	0
T14	2574	123	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209667	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	10	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209667	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	10	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1078977	0	0
T1	2370	16	0	0
T2	10276	275	0	0
T3	1582	31	0	0
T7	11808	13	0	0
T8	13320	34	0	0
T10	2275	24	0	0
T11	1624	18	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209667	0	0
T1	2370	11	0	0
T2	10276	191	0	0
T3	1582	15	0	0
T7	11808	10	0	0
T8	13320	9	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	14	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	216280	0	0
GntImpliesValid_A	420727209	216280	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	216280	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	5574784	0	0
ReadyAndValidImplyGrant_A	420727209	216280	0	0
ReqAndReadyImplyGrant_A	420727209	216280	0	0
ReqImpliesValid_A	420727209	1317060	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	216280	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216280	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	13	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216280	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	13	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216280	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	13	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	5574784	0	0
T1	2370	69	0	0
T2	10276	742	0	0
T3	1582	51	0	0
T7	11808	158	0	0
T8	13320	302	0	0
T10	2275	109	0	0
T11	1624	72	0	0
T12	1819	146	0	0
T13	2577	182	0	0
T14	2574	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216280	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	13	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216280	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	13	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1317060	0	0
T1	2370	24	0	0
T2	10276	297	0	0
T3	1582	25	0	0
T7	11808	23	0	0
T8	13320	53	0	0
T10	2275	31	0	0
T11	1624	12	0	0
T12	1819	43	0	0
T13	2577	60	0	0
T14	2574	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216280	0	0
T1	2370	14	0	0
T2	10276	224	0	0
T3	1582	17	0	0
T7	11808	13	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	210675	0	0
GntImpliesValid_A	420727209	210675	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	210675	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	4751892	0	0
ReadyAndValidImplyGrant_A	420727209	210675	0	0
ReqAndReadyImplyGrant_A	420727209	210675	0	0
ReqImpliesValid_A	420727209	1067143	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	210675	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210675	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	16	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210675	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	16	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210675	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	16	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	4751892	0	0
T1	2370	67	0	0
T2	10276	628	0	0
T3	1582	30	0	0
T7	11808	415	0	0
T8	13320	212	0	0
T10	2275	36	0	0
T11	1624	37	0	0
T12	1819	157	0	0
T13	2577	202	0	0
T14	2574	102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210675	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	16	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210675	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	16	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1067143	0	0
T1	2370	20	0	0
T2	10276	201	0	0
T3	1582	5	0	0
T7	11808	87	0	0
T8	13320	22	0	0
T10	2275	14	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210675	0	0
T1	2370	13	0	0
T2	10276	162	0	0
T3	1582	5	0	0
T7	11808	18	0	0
T8	13320	16	0	0
T10	2275	8	0	0
T11	1624	5	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	209865	0	0
GntImpliesValid_A	420727209	209865	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	209865	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	5792914	0	0
ReadyAndValidImplyGrant_A	420727209	209865	0	0
ReqAndReadyImplyGrant_A	420727209	209865	0	0
ReqImpliesValid_A	420727209	1306979	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	209865	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209865	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	13	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209865	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	13	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209865	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	13	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	5792914	0	0
T1	2370	129	0	0
T2	10276	633	0	0
T3	1582	29	0	0
T7	11808	82	0	0
T8	13320	440	0	0
T10	2275	216	0	0
T11	1624	53	0	0
T12	1819	66	0	0
T13	2577	456	0	0
T14	2574	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209865	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	13	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209865	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	13	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	1306979	0	0
T1	2370	12	0	0
T2	10276	228	0	0
T3	1582	18	0	0
T7	11808	8	0	0
T8	13320	111	0	0
T10	2275	19	0	0
T11	1624	16	0	0
T12	1819	20	0	0
T13	2577	199	0	0
T14	2574	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209865	0	0
T1	2370	12	0	0
T2	10276	167	0	0
T3	1582	11	0	0
T7	11808	8	0	0
T8	13320	13	0	0
T10	2275	15	0	0
T11	1624	12	0	0
T12	1819	12	0	0
T13	2577	27	0	0
T14	2574	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	208362	0	0
GntImpliesValid_A	420727209	208362	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	208362	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3295671	0	0
ReadyAndValidImplyGrant_A	420727209	208362	0	0
ReqAndReadyImplyGrant_A	420727209	208362	0	0
ReqImpliesValid_A	420727209	568684	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	208362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208362	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	11	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208362	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	11	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208362	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	11	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3295671	0	0
T1	2370	16	0	0
T2	10276	167	0	0
T3	1582	12	0	0
T7	11808	82	0	0
T8	13320	96	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	19	0	0
T14	2574	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208362	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	11	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208362	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	11	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	568684	0	0
T1	2370	15	0	0
T2	10276	188	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	9	0	0
T11	1624	9	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208362	0	0
T1	2370	15	0	0
T2	10276	177	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	11	0	0
T10	2275	8	0	0
T11	1624	8	0	0
T12	1819	11	0	0
T13	2577	18	0	0
T14	2574	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T11 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T11,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T11,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	226380	0	0
GntImpliesValid_A	420727209	226380	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	226380	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3339817	0	0
ReadyAndValidImplyGrant_A	420727209	226380	0	0
ReqAndReadyImplyGrant_A	420727209	226380	0	0
ReqImpliesValid_A	420727209	638064	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	226380	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	226380	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	20	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	226380	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	20	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	226380	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	20	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3339817	0	0
T1	2370	20	0	0
T2	10276	167	0	0
T3	1582	12	0	0
T7	11808	63	0	0
T8	13320	181	0	0
T10	2275	11	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	226380	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	20	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	226380	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	20	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	638064	0	0
T1	2370	19	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	15	0	0
T8	13320	34	0	0
T10	2275	10	0	0
T11	1624	12	0	0
T12	1819	16	0	0
T13	2577	23	0	0
T14	2574	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	226380	0	0
T1	2370	19	0	0
T2	10276	175	0	0
T3	1582	11	0	0
T7	11808	12	0	0
T8	13320	20	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	15	0	0
T13	2577	22	0	0
T14	2574	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	217944	0	0
GntImpliesValid_A	420727209	217944	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	217944	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3340905	0	0
ReadyAndValidImplyGrant_A	420727209	217944	0	0
ReqAndReadyImplyGrant_A	420727209	217944	0	0
ReqImpliesValid_A	420727209	633612	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	217944	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	217944	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	24	0	0
T8	13320	10	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	217944	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	24	0	0
T8	13320	10	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	217944	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	24	0	0
T8	13320	10	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3340905	0	0
T1	2370	15	0	0
T2	10276	189	0	0
T3	1582	17	0	0
T7	11808	158	0	0
T8	13320	67	0	0
T10	2275	14	0	0
T11	1624	16	0	0
T12	1819	18	0	0
T13	2577	19	0	0
T14	2574	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	217944	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	24	0	0
T8	13320	10	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	217944	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	24	0	0
T8	13320	10	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	633612	0	0
T1	2370	14	0	0
T2	10276	206	0	0
T3	1582	24	0	0
T7	11808	40	0	0
T8	13320	13	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	24	0	0
T14	2574	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	217944	0	0
T1	2370	14	0	0
T2	10276	197	0	0
T3	1582	20	0	0
T7	11808	24	0	0
T8	13320	10	0	0
T10	2275	13	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	21	0	0
T14	2574	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	210039	0	0
GntImpliesValid_A	420727209	210039	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	210039	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3329675	0	0
ReadyAndValidImplyGrant_A	420727209	210039	0	0
ReqAndReadyImplyGrant_A	420727209	210039	0	0
ReqImpliesValid_A	420727209	624505	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	210039	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210039	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	16	0	0
T8	13320	16	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210039	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	16	0	0
T8	13320	16	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210039	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	16	0	0
T8	13320	16	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3329675	0	0
T1	2370	15	0	0
T2	10276	151	0	0
T3	1582	14	0	0
T7	11808	126	0	0
T8	13320	100	0	0
T10	2275	19	0	0
T11	1624	10	0	0
T12	1819	11	0	0
T13	2577	26	0	0
T14	2574	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210039	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	16	0	0
T8	13320	16	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210039	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	16	0	0
T8	13320	16	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	624505	0	0
T1	2370	20	0	0
T2	10276	158	0	0
T3	1582	15	0	0
T7	11808	20	0	0
T8	13320	16	0	0
T10	2275	20	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	210039	0	0
T1	2370	17	0	0
T2	10276	154	0	0
T3	1582	14	0	0
T7	11808	16	0	0
T8	13320	16	0	0
T10	2275	19	0	0
T11	1624	9	0	0
T12	1819	10	0	0
T13	2577	25	0	0
T14	2574	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	208781	0	0
GntImpliesValid_A	420727209	208781	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	208781	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3273141	0	0
ReadyAndValidImplyGrant_A	420727209	208781	0	0
ReqAndReadyImplyGrant_A	420727209	208781	0	0
ReqImpliesValid_A	420727209	574610	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	208781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208781	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208781	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208781	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3273141	0	0
T1	2370	14	0	0
T2	10276	186	0	0
T3	1582	11	0	0
T7	11808	122	0	0
T8	13320	54	0	0
T10	2275	14	0	0
T11	1624	12	0	0
T12	1819	14	0	0
T13	2577	31	0	0
T14	2574	22	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208781	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208781	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	574610	0	0
T1	2370	17	0	0
T2	10276	207	0	0
T3	1582	12	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	13	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	208781	0	0
T1	2370	15	0	0
T2	10276	196	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	7	0	0
T10	2275	13	0	0
T11	1624	12	0	0
T12	1819	13	0	0
T13	2577	30	0	0
T14	2574	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	215707	0	0
GntImpliesValid_A	420727209	215707	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	215707	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3335006	0	0
ReadyAndValidImplyGrant_A	420727209	215707	0	0
ReqAndReadyImplyGrant_A	420727209	215707	0	0
ReqImpliesValid_A	420727209	601574	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	215707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215707	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215707	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215707	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3335006	0	0
T1	2370	10	0	0
T2	10276	175	0	0
T3	1582	15	0	0
T7	11808	93	0	0
T8	13320	41	0	0
T10	2275	10	0	0
T11	1624	6	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215707	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215707	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	601574	0	0
T1	2370	15	0	0
T2	10276	204	0	0
T3	1582	14	0	0
T7	11808	11	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	22	0	0
T14	2574	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215707	0	0
T1	2370	12	0	0
T2	10276	189	0	0
T3	1582	14	0	0
T7	11808	7	0	0
T8	13320	8	0	0
T10	2275	9	0	0
T11	1624	5	0	0
T12	1819	11	0	0
T13	2577	21	0	0
T14	2574	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T11 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T11,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T11,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	212301	0	0
GntImpliesValid_A	420727209	212301	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	212301	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3304005	0	0
ReadyAndValidImplyGrant_A	420727209	212301	0	0
ReqAndReadyImplyGrant_A	420727209	212301	0	0
ReqImpliesValid_A	420727209	577777	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	212301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	212301	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	212301	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	212301	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3304005	0	0
T1	2370	12	0	0
T2	10276	200	0	0
T3	1582	11	0	0
T7	11808	96	0	0
T8	13320	96	0	0
T10	2275	15	0	0
T11	1624	11	0	0
T12	1819	10	0	0
T13	2577	23	0	0
T14	2574	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	212301	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	212301	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	577777	0	0
T1	2370	11	0	0
T2	10276	229	0	0
T3	1582	10	0	0
T7	11808	18	0	0
T8	13320	33	0	0
T10	2275	14	0	0
T11	1624	12	0	0
T12	1819	9	0	0
T13	2577	24	0	0
T14	2574	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	212301	0	0
T1	2370	11	0	0
T2	10276	214	0	0
T3	1582	10	0	0
T7	11808	13	0	0
T8	13320	18	0	0
T10	2275	14	0	0
T11	1624	11	0	0
T12	1819	9	0	0
T13	2577	23	0	0
T14	2574	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	215875	0	0
GntImpliesValid_A	420727209	215875	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	215875	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3284105	0	0
ReadyAndValidImplyGrant_A	420727209	215875	0	0
ReqAndReadyImplyGrant_A	420727209	215875	0	0
ReqImpliesValid_A	420727209	594455	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	215875	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215875	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	18	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215875	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	18	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215875	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	18	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3284105	0	0
T1	2370	12	0	0
T2	10276	156	0	0
T3	1582	14	0	0
T7	11808	151	0	0
T8	13320	120	0	0
T10	2275	11	0	0
T11	1624	13	0	0
T12	1819	12	0	0
T13	2577	21	0	0
T14	2574	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215875	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	18	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215875	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	18	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	594455	0	0
T1	2370	13	0	0
T2	10276	183	0	0
T3	1582	15	0	0
T7	11808	28	0	0
T8	13320	22	0	0
T10	2275	10	0	0
T11	1624	14	0	0
T12	1819	11	0	0
T13	2577	30	0	0
T14	2574	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	215875	0	0
T1	2370	12	0	0
T2	10276	169	0	0
T3	1582	14	0	0
T7	11808	18	0	0
T8	13320	17	0	0
T10	2275	10	0	0
T11	1624	13	0	0
T12	1819	11	0	0
T13	2577	25	0	0
T14	2574	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	234741	0	0
GntImpliesValid_A	420727209	234741	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	234741	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3425774	0	0
ReadyAndValidImplyGrant_A	420727209	234741	0	0
ReqAndReadyImplyGrant_A	420727209	234741	0	0
ReqImpliesValid_A	420727209	681260	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	234741	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	234741	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	234741	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	234741	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3425774	0	0
T1	2370	14	0	0
T2	10276	174	0	0
T3	1582	11	0	0
T7	11808	89	0	0
T8	13320	39	0	0
T10	2275	11	0	0
T11	1624	11	0	0
T12	1819	24	0	0
T13	2577	16	0	0
T14	2574	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	234741	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	234741	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	681260	0	0
T1	2370	15	0	0
T2	10276	195	0	0
T3	1582	12	0	0
T7	11808	21	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	29	0	0
T13	2577	17	0	0
T14	2574	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	234741	0	0
T1	2370	14	0	0
T2	10276	184	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	4	0	0
T10	2275	10	0	0
T11	1624	10	0	0
T12	1819	26	0	0
T13	2577	16	0	0
T14	2574	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	216860	0	0
GntImpliesValid_A	420727209	216860	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	216860	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3320844	0	0
ReadyAndValidImplyGrant_A	420727209	216860	0	0
ReqAndReadyImplyGrant_A	420727209	216860	0	0
ReqImpliesValid_A	420727209	617266	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	216860	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216860	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	17	0	0
T8	13320	9	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216860	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	17	0	0
T8	13320	9	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216860	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	17	0	0
T8	13320	9	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3320844	0	0
T1	2370	15	0	0
T2	10276	194	0	0
T3	1582	16	0	0
T7	11808	126	0	0
T8	13320	82	0	0
T10	2275	10	0	0
T11	1624	15	0	0
T12	1819	14	0	0
T13	2577	32	0	0
T14	2574	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216860	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	17	0	0
T8	13320	9	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216860	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	17	0	0
T8	13320	9	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	617266	0	0
T1	2370	16	0	0
T2	10276	207	0	0
T3	1582	17	0	0
T7	11808	19	0	0
T8	13320	9	0	0
T10	2275	13	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	216860	0	0
T1	2370	15	0	0
T2	10276	200	0	0
T3	1582	16	0	0
T7	11808	17	0	0
T8	13320	9	0	0
T10	2275	11	0	0
T11	1624	14	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	209314	0	0
GntImpliesValid_A	420727209	209314	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	209314	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3221124	0	0
ReadyAndValidImplyGrant_A	420727209	209314	0	0
ReqAndReadyImplyGrant_A	420727209	209314	0	0
ReqImpliesValid_A	420727209	594075	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	209314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209314	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209314	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209314	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3221124	0	0
T1	2370	11	0	0
T2	10276	164	0	0
T3	1582	11	0	0
T7	11808	119	0	0
T8	13320	75	0	0
T10	2275	6	0	0
T11	1624	12	0	0
T12	1819	16	0	0
T13	2577	26	0	0
T14	2574	23	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209314	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209314	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	594075	0	0
T1	2370	10	0	0
T2	10276	175	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	15	0	0
T12	1819	17	0	0
T13	2577	25	0	0
T14	2574	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209314	0	0
T1	2370	10	0	0
T2	10276	169	0	0
T3	1582	10	0	0
T7	11808	14	0	0
T8	13320	6	0	0
T10	2275	5	0	0
T11	1624	13	0	0
T12	1819	16	0	0
T13	2577	25	0	0
T14	2574	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	207318	0	0
GntImpliesValid_A	420727209	207318	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	207318	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3240256	0	0
ReadyAndValidImplyGrant_A	420727209	207318	0	0
ReqAndReadyImplyGrant_A	420727209	207318	0	0
ReqImpliesValid_A	420727209	546359	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	207318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	207318	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	6	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	207318	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	6	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	207318	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	6	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3240256	0	0
T1	2370	14	0	0
T2	10276	186	0	0
T3	1582	12	0	0
T7	11808	74	0	0
T8	13320	21	0	0
T10	2275	18	0	0
T11	1624	8	0	0
T12	1819	13	0	0
T13	2577	31	0	0
T14	2574	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	207318	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	6	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	207318	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	6	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	546359	0	0
T1	2370	13	0	0
T2	10276	201	0	0
T3	1582	11	0	0
T7	11808	18	0	0
T8	13320	14	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	32	0	0
T14	2574	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	207318	0	0
T1	2370	13	0	0
T2	10276	193	0	0
T3	1582	11	0	0
T7	11808	13	0	0
T8	13320	6	0	0
T10	2275	17	0	0
T11	1624	7	0	0
T12	1819	12	0	0
T13	2577	31	0	0
T14	2574	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	203064	0	0
GntImpliesValid_A	420727209	203064	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	203064	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3307065	0	0
ReadyAndValidImplyGrant_A	420727209	203064	0	0
ReqAndReadyImplyGrant_A	420727209	203064	0	0
ReqImpliesValid_A	420727209	533636	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	203064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	203064	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	15	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	203064	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	15	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	203064	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	15	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3307065	0	0
T1	2370	11	0	0
T2	10276	175	0	0
T3	1582	14	0	0
T7	11808	107	0	0
T8	13320	62	0	0
T10	2275	10	0	0
T11	1624	12	0	0
T12	1819	20	0	0
T13	2577	14	0	0
T14	2574	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	203064	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	15	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	203064	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	15	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	533636	0	0
T1	2370	10	0	0
T2	10276	206	0	0
T3	1582	17	0	0
T7	11808	17	0	0
T8	13320	16	0	0
T10	2275	11	0	0
T11	1624	11	0	0
T12	1819	23	0	0
T13	2577	15	0	0
T14	2574	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	203064	0	0
T1	2370	10	0	0
T2	10276	190	0	0
T3	1582	15	0	0
T7	11808	15	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	11	0	0
T12	1819	21	0	0
T13	2577	14	0	0
T14	2574	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	209873	0	0
GntImpliesValid_A	420727209	209873	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	209873	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	3265407	0	0
ReadyAndValidImplyGrant_A	420727209	209873	0	0
ReqAndReadyImplyGrant_A	420727209	209873	0	0
ReqImpliesValid_A	420727209	551207	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	0	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	209873	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209873	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209873	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209873	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	3265407	0	0
T1	2370	10	0	0
T2	10276	206	0	0
T3	1582	8	0	0
T7	11808	116	0	0
T8	13320	94	0	0
T10	2275	10	0	0
T11	1624	9	0	0
T12	1819	13	0	0
T13	2577	25	0	0
T14	2574	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209873	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209873	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	551207	0	0
T1	2370	11	0	0
T2	10276	237	0	0
T3	1582	9	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	11	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	26	0	0
T14	2574	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	209873	0	0
T1	2370	10	0	0
T2	10276	221	0	0
T3	1582	8	0	0
T7	11808	20	0	0
T8	13320	11	0	0
T10	2275	10	0	0
T11	1624	8	0	0
T12	1819	12	0	0
T13	2577	25	0	0
T14	2574	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	869987	0	0
GntImpliesValid_A	420727209	869987	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	869987	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	12687773	0	0
ReadyAndValidImplyGrant_A	420727209	869987	0	0
ReqAndReadyImplyGrant_A	420727209	869987	0	0
ReqImpliesValid_A	420727209	2481328	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	15782	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	869987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	869987	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	52	0	0
T8	13320	53	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	869987	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	52	0	0
T8	13320	53	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	869987	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	52	0	0
T8	13320	53	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	12687773	0	0
T1	2370	1	0	0
T2	10276	1	0	0
T3	1582	1	0	0
T7	11808	359	0	0
T8	13320	338	0	0
T10	2275	1	0	0
T11	1624	1	0	0
T12	1819	1	0	0
T13	2577	1	0	0
T14	2574	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	869987	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	52	0	0
T8	13320	53	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	869987	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	52	0	0
T8	13320	53	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	2481328	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	90	0	0
T8	13320	63	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	15782	0	900
T2	10276	23	0	1
T3	1582	0	0	1
T4	0	7	0	0
T7	11808	0	0	1
T8	13320	0	0	1
T9	16481	22	0	1
T10	2275	0	0	1
T11	1624	0	0	1
T12	1819	0	0	1
T13	2577	2	0	1
T14	2574	3	0	1
T15	0	11	0	0
T17	0	3	0	0
T18	0	12	0	0
T19	0	17	0	0
T21	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	869987	0	0
T1	2370	57	0	0
T2	10276	842	0	0
T3	1582	25	0	0
T7	11808	52	0	0
T8	13320	53	0	0
T10	2275	34	0	0
T11	1624	33	0	0
T12	1819	57	0	0
T13	2577	80	0	0
T14	2574	151	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420727209	420593071	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420727209	865992	0	0
GntImpliesValid_A	420727209	865992	0	0
GrantKnown_A	420727209	420593071	0	0
IdxKnown_A	420727209	420593071	0	0
IndexIsCorrect_A	420727209	865992	0	0
LockArbDecision_A	420727209	0	0	0
NoReadyValidNoGrant_A	420727209	354444647	0	0
ReadyAndValidImplyGrant_A	420727209	865992	0	0
ReqAndReadyImplyGrant_A	420727209	865992	0	0
ReqImpliesValid_A	420727209	14555351	0	0
ReqStaysHighUntilGranted0_M	420727209	0	0	0
RoundRobin_A	420727209	27065	0	900
ValidKnown_A	420727209	420593071	0	0
gen_data_port_assertion.DataFlow_A	420727209	865992	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	865992	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	52	0	0
T8	13320	60	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	865992	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	52	0	0
T8	13320	60	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	865992	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	52	0	0
T8	13320	60	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	354444647	0	0
T1	2370	1	0	0
T2	10276	1	0	0
T3	1582	1	0	0
T7	11808	10399	0	0
T8	13320	11604	0	0
T10	2275	1	0	0
T11	1624	1	0	0
T12	1819	1	0	0
T13	2577	1	0	0
T14	2574	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	865992	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	52	0	0
T8	13320	60	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	865992	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	52	0	0
T8	13320	60	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	14555351	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	355	0	0
T8	13320	534	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	27065	0	900
T2	10276	15	0	1
T3	1582	0	0	1
T4	0	5	0	0
T7	11808	0	0	1
T8	13320	0	0	1
T9	16481	0	0	1
T10	2275	0	0	1
T11	1624	0	0	1
T12	1819	0	0	1
T13	2577	3	0	1
T14	2574	3	0	1
T15	0	10	0	0
T16	0	481	0	0
T17	0	6	0	0
T18	0	13	0	0
T19	0	5	0	0
T20	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	420593071	0	0
T1	2370	2300	0	0
T2	10276	10260	0	0
T3	1582	1573	0	0
T7	11808	11772	0	0
T8	13320	13269	0	0
T10	2275	2207	0	0
T11	1624	1591	0	0
T12	1819	1759	0	0
T13	2577	2495	0	0
T14	2574	2558	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420727209	865992	0	0
T1	2370	53	0	0
T2	10276	820	0	0
T3	1582	51	0	0
T7	11808	52	0	0
T8	13320	60	0	0
T10	2275	31	0	0
T11	1624	38	0	0
T12	1819	70	0	0
T13	2577	92	0	0
T14	2574	133	0	0