Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[1] 2328398 1 T1 151 T2 171 T3 102
values[2] 167691 1 T1 12 T2 16 T3 6
values[3] 41914 1 T2 1 T11 3 T14 3
values[4] 26456 1 T21 1 T72 1 T73 152
values[5] 18622 1 T72 1 T73 112 T96 1
values[6] 14248 1 T73 125 T96 1 T75 139
values[7] 11788 1 T73 67 T96 1 T75 148
values[8] 9674 1 T73 49 T96 1 T75 97
values[9] 8312 1 T73 39 T96 1 T75 81
values[10] 7398 1 T73 32 T96 1 T75 50
values[11] 6675 1 T73 31 T96 1 T75 37
values[12] 6029 1 T73 20 T96 1 T75 33
values[13] 5708 1 T73 21 T96 1 T75 31
values[14] 5384 1 T73 20 T96 1 T75 22
values[15] 4774 1 T73 13 T96 1 T75 12
values[16] 4360 1 T73 24 T96 1 T75 20
values[17] 3905 1 T73 18 T96 1 T75 26
values[18] 3758 1 T73 26 T96 1 T75 25
values[19] 3658 1 T73 12 T96 1 T75 26
values[20] 3679 1 T73 9 T96 1 T75 23
values[21] 3395 1 T73 9 T96 1 T75 17
values[22] 3085 1 T73 5 T96 1 T75 10
values[23] 2794 1 T73 7 T96 1 T75 17
values[24] 2693 1 T73 12 T96 1 T75 13
values[25] 2626 1 T73 14 T96 1 T75 21
values[26] 2566 1 T73 14 T96 1 T75 27
values[27] 2433 1 T73 9 T96 1 T75 30
values[28] 2300 1 T73 6 T96 1 T75 37
values[29] 2177 1 T73 16 T96 1 T75 20
values[30] 2083 1 T73 13 T96 1 T75 19
values[31] 1999 1 T73 15 T96 1 T75 13
values[32] 1866 1 T73 17 T96 1 T75 5
values[33] 1745 1 T73 14 T96 1 T75 3
values[34] 1811 1 T73 12 T96 1 T75 4
values[35] 1783 1 T73 14 T96 1 T75 4
values[36] 1776 1 T73 11 T96 1 T75 2
values[37] 1698 1 T73 10 T96 1 T75 9
values[38] 1756 1 T73 14 T96 1 T75 5
values[39] 1703 1 T73 14 T96 1 T75 6
values[40] 1628 1 T73 12 T96 1 T75 8
values[41] 1624 1 T73 24 T96 1 T75 6
values[42] 1638 1 T73 24 T96 1 T75 8
values[43] 1545 1 T73 17 T96 1 T75 4
values[44] 1508 1 T73 13 T96 1 T75 5
values[45] 1464 1 T73 15 T96 1 T75 7
values[46] 1409 1 T73 8 T96 1 T75 6
values[47] 1401 1 T73 9 T96 1 T75 6
values[48] 1362 1 T73 12 T96 1 T75 3
values[49] 1414 1 T73 7 T96 1 T75 2
values[50] 1405 1 T73 16 T96 1 T75 2
values[51] 1353 1 T73 13 T96 1 T75 5
values[52] 1357 1 T73 8 T96 1 T75 5
values[53] 1394 1 T73 12 T96 1 T75 6
values[54] 1375 1 T73 14 T96 1 T75 5
values[55] 1321 1 T73 14 T96 1 T75 3
values[56] 1352 1 T73 5 T96 1 T75 5
values[57] 1377 1 T73 9 T96 1 T75 3
values[58] 1312 1 T73 13 T96 1 T75 7
values[59] 1348 1 T73 8 T96 1 T75 11
values[60] 1379 1 T73 11 T96 1 T75 5
values[61] 1615 1 T73 6 T96 1 T75 11
values[62] 2708 1 T73 8 T96 1 T75 18
values[63] 8103 1 T73 23 T96 1 T75 54
values[64] 121427 1 T73 30 T96 235 T75 148


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[1] 2413315 1 T1 86 T2 93 T3 98
values[2] 403778 1 T1 35 T2 24 T3 25
values[3] 43732 1 T2 1 T3 1 T8 4
values[4] 8930 1 T3 1 T11 1 T12 1
values[5] 4029 1 T21 1 T50 4 T73 39
values[6] 2762 1 T21 1 T73 30 T75 11
values[7] 2182 1 T73 26 T75 12 T77 9
values[8] 1984 1 T73 22 T75 23 T77 14
values[9] 1854 1 T73 29 T75 28 T77 14
values[10] 1875 1 T73 27 T75 28 T77 9
values[11] 1560 1 T73 18 T75 20 T77 2
values[12] 1412 1 T73 10 T75 15 T79 11
values[13] 1315 1 T73 7 T75 20 T79 13
values[14] 1235 1 T73 7 T75 15 T79 12
values[15] 1180 1 T73 2 T75 26 T79 13
values[16] 1121 1 T73 3 T75 9 T79 10
values[17] 1047 1 T73 4 T75 7 T79 4
values[18] 1006 1 T73 2 T75 8 T79 7
values[19] 991 1 T73 5 T75 17 T79 4
values[20] 903 1 T73 8 T75 22 T79 2
values[21] 862 1 T73 3 T75 32 T79 1
values[22] 821 1 T73 3 T75 24 T79 2
values[23] 758 1 T73 3 T75 14 T79 10
values[24] 760 1 T73 6 T75 8 T79 10
values[25] 718 1 T73 6 T75 4 T79 3
values[26] 682 1 T73 7 T75 1 T79 3
values[27] 665 1 T73 3 T75 1 T79 1
values[28] 664 1 T73 2 T75 1 T79 5
values[29] 622 1 T73 3 T75 1 T79 4
values[30] 617 1 T73 3 T75 4 T79 1
values[31] 588 1 T73 1 T75 3 T79 3
values[32] 511 1 T73 1 T75 1 T79 3
values[33] 492 1 T73 2 T75 1 T79 3
values[34] 436 1 T73 1 T75 1 T79 3
values[35] 440 1 T73 4 T75 1 T79 1
values[36] 419 1 T73 10 T75 2 T79 1
values[37] 454 1 T73 7 T75 1 T79 2
values[38] 438 1 T73 4 T75 1 T79 1
values[39] 454 1 T73 6 T75 1 T79 1
values[40] 428 1 T73 9 T75 1 T79 2
values[41] 448 1 T73 15 T75 3 T79 2
values[42] 385 1 T73 8 T75 1 T79 1
values[43] 392 1 T73 6 T75 3 T79 4
values[44] 400 1 T73 1 T75 4 T79 2
values[45] 392 1 T75 2 T79 3 T171 3
values[46] 408 1 T75 1 T79 6 T171 6
values[47] 421 1 T75 2 T79 3 T171 4
values[48] 395 1 T75 1 T79 1 T171 4
values[49] 390 1 T75 2 T171 4 T323 2
values[50] 383 1 T75 3 T171 3 T323 7
values[51] 365 1 T75 3 T171 3 T323 2
values[52] 380 1 T75 1 T171 4 T323 2
values[53] 410 1 T75 2 T171 3 T323 2
values[54] 391 1 T75 2 T171 3 T323 3
values[55] 328 1 T75 2 T171 3 T323 1
values[56] 335 1 T75 2 T171 3 T323 2
values[57] 375 1 T75 7 T171 4 T323 1
values[58] 374 1 T75 2 T171 4 T323 1
values[59] 368 1 T75 3 T171 3 T323 1
values[60] 334 1 T75 1 T171 3 T323 1
values[61] 378 1 T75 1 T171 3 T323 1
values[62] 581 1 T75 4 T171 3 T323 1
values[63] 2226 1 T75 21 T171 9 T323 8
values[64] 25921 1 T75 71 T171 143 T323 96


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[1] 299278 1 T1 1 T2 1 T3 2
values[2] 1633081 1 T1 154 T2 41 T3 119
values[3] 520986 1 T1 6 T2 59 T3 22
values[4] 53805 1 T3 1 T13 1 T14 3
values[5] 34475 1 T72 1 T73 253 T74 1
values[6] 26652 1 T73 153 T96 1 T75 231
values[7] 21290 1 T73 98 T96 1 T75 181
values[8] 17778 1 T73 76 T96 1 T75 213
values[9] 15113 1 T73 87 T96 1 T75 144
values[10] 12854 1 T73 88 T96 1 T75 144
values[11] 11229 1 T73 42 T96 1 T75 97
values[12] 9995 1 T73 26 T96 1 T75 60
values[13] 8795 1 T73 34 T96 1 T75 41
values[14] 7757 1 T73 32 T96 1 T75 22
values[15] 7082 1 T73 32 T96 1 T75 20
values[16] 6445 1 T73 29 T96 1 T75 54
values[17] 5689 1 T73 9 T96 1 T75 49
values[18] 4950 1 T73 10 T96 1 T75 36
values[19] 4484 1 T73 8 T96 1 T75 45
values[20] 4018 1 T73 15 T96 1 T75 48
values[21] 3617 1 T73 18 T96 1 T75 39
values[22] 3383 1 T73 8 T96 1 T75 15
values[23] 3201 1 T73 11 T96 1 T75 16
values[24] 2992 1 T73 14 T96 1 T75 2
values[25] 2973 1 T73 14 T96 1 T75 4
values[26] 2896 1 T73 16 T96 1 T75 4
values[27] 2555 1 T73 20 T96 1 T75 6
values[28] 2383 1 T73 22 T96 1 T75 5
values[29] 2242 1 T73 15 T96 1 T75 7
values[30] 2143 1 T73 18 T96 1 T75 5
values[31] 2008 1 T73 17 T96 1 T75 2
values[32] 2039 1 T73 15 T96 1 T75 7
values[33] 2036 1 T73 18 T96 1 T75 5
values[34] 1948 1 T73 13 T96 1 T75 8
values[35] 1899 1 T73 12 T96 1 T75 8
values[36] 1861 1 T73 27 T96 1 T75 2
values[37] 1863 1 T73 27 T96 1 T75 6
values[38] 1827 1 T73 17 T96 1 T75 8
values[39] 1733 1 T73 23 T96 1 T75 12
values[40] 1769 1 T73 29 T96 1 T75 11
values[41] 1631 1 T73 21 T96 1 T75 7
values[42] 1631 1 T73 12 T96 1 T75 2
values[43] 1616 1 T73 7 T96 1 T75 4
values[44] 1527 1 T73 10 T96 1 T75 5
values[45] 1519 1 T73 6 T96 1 T75 6
values[46] 1479 1 T73 9 T96 1 T75 4
values[47] 1526 1 T73 14 T96 1 T75 3
values[48] 1448 1 T73 7 T96 1 T75 4
values[49] 1454 1 T73 8 T96 1 T75 4
values[50] 1428 1 T73 11 T96 1 T75 3
values[51] 1464 1 T73 11 T96 1 T75 4
values[52] 1484 1 T73 7 T96 1 T75 10
values[53] 1456 1 T73 4 T96 1 T75 4
values[54] 1443 1 T73 9 T96 1 T75 6
values[55] 1391 1 T73 13 T96 1 T75 11
values[56] 1327 1 T73 13 T96 1 T75 7
values[57] 1303 1 T73 12 T96 1 T75 4
values[58] 1311 1 T73 8 T96 1 T75 5
values[59] 1356 1 T73 7 T96 1 T75 3
values[60] 1368 1 T73 8 T96 1 T75 6
values[61] 1501 1 T73 8 T96 1 T75 10
values[62] 2335 1 T73 15 T96 1 T75 18
values[63] 7066 1 T73 50 T96 1 T75 46
values[64] 121382 1 T73 99 T96 196 T75 158