Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1456156	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231664

1

T1

19

T2

21

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	572366	1			T1	46		T2	55		T3	49
values[0x0]	542231	1			T1	40		T2	35		T3	45
values[0x1]	573223	1			T1	45		T2	52		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1125820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

562000

1

T1

48

T2

47

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25791	1			T1	4		T3	1		T9	6
valid_sources[0x01]	27288	1			T1	7		T3	5		T9	2
valid_sources[0x02]	26367	1			T1	3		T3	1		T9	5
valid_sources[0x03]	27982	1			T3	1		T9	3		T10	13
valid_sources[0x04]	26075	1			T1	2		T11	7		T12	3
valid_sources[0x05]	26098	1			T2	7		T3	2		T9	2
valid_sources[0x06]	26107	1			T1	15		T2	10		T3	1
valid_sources[0x07]	26739	1			T1	6		T2	15		T9	2
valid_sources[0x08]	26596	1			T3	2		T9	3		T11	6
valid_sources[0x09]	25569	1			T3	4		T9	4		T11	6
valid_sources[0x0a]	26265	1			T3	2		T10	3		T11	12
valid_sources[0x0b]	25429	1			T1	1		T3	2		T9	5
valid_sources[0x0c]	26005	1			T3	2		T9	1		T11	7
valid_sources[0x0d]	25876	1			T9	2		T10	3		T11	4
valid_sources[0x0e]	25600	1			T1	1		T3	5		T9	3
valid_sources[0x0f]	26168	1			T1	1		T2	26		T3	1
valid_sources[0x10]	25971	1			T2	18		T3	2		T9	1
valid_sources[0x11]	26710	1			T9	10		T11	15		T13	8
valid_sources[0x12]	25251	1			T3	1		T9	4		T11	10
valid_sources[0x13]	25751	1			T3	1		T9	3		T10	21
valid_sources[0x14]	26562	1			T1	3		T3	3		T9	2
valid_sources[0x15]	26265	1			T9	3		T10	14		T11	8
valid_sources[0x16]	26044	1			T1	7		T3	5		T9	1
valid_sources[0x17]	26020	1			T1	11		T3	1		T9	2
valid_sources[0x18]	26924	1			T3	3		T9	2		T11	8
valid_sources[0x19]	26234	1			T1	2		T3	2		T9	5
valid_sources[0x1a]	27854	1			T2	5		T3	1		T9	2
valid_sources[0x1b]	25844	1			T3	4		T10	24		T11	9
valid_sources[0x1c]	25917	1			T1	11		T3	1		T9	4
valid_sources[0x1d]	26159	1			T1	1		T9	3		T11	10
valid_sources[0x1e]	27054	1			T3	1		T9	1		T10	4
valid_sources[0x1f]	26908	1			T1	4		T3	1		T9	6
valid_sources[0x20]	27037	1			T3	3		T9	1		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24432

1

T1

1

T2

2

T3

2

values[0x0]

all_enables

biggest_size

183051

1

T1

16

T2

13

T3

15

values[0x1]

all_enables

biggest_size

24181

1

T1

2

T2

6

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1474143	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241147

1

T1

18

T2

18

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586399	1			T1	36		T2	24		T3	42
values[0x0]	543095	1			T1	42		T2	34		T3	30
values[0x1]	585796	1			T1	38		T2	35		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1131917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

583373

1

T1

39

T2

32

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27128	1			T1	5		T2	2		T10	22
valid_sources[0x01]	27586	1			T2	1		T3	2		T10	26
valid_sources[0x02]	26484	1			T1	6		T2	1		T3	3
valid_sources[0x03]	26624	1			T2	2		T10	14		T13	1
valid_sources[0x04]	26943	1			T1	1		T3	3		T10	6
valid_sources[0x05]	26330	1			T1	4		T2	2		T10	4
valid_sources[0x06]	27141	1			T1	6		T2	2		T3	2
valid_sources[0x07]	26835	1			T1	2		T2	3		T10	20
valid_sources[0x08]	26647	1			T2	1		T3	3		T10	2
valid_sources[0x09]	26089	1			T1	10		T2	1		T3	2
valid_sources[0x0a]	26415	1			T3	3		T9	2		T10	15
valid_sources[0x0b]	26487	1			T2	1		T3	2		T11	6
valid_sources[0x0c]	27487	1			T2	1		T3	1		T11	5
valid_sources[0x0d]	26477	1			T1	4		T2	1		T3	3
valid_sources[0x0e]	26369	1			T2	2		T3	4		T10	8
valid_sources[0x0f]	26888	1			T1	1		T10	12		T7	1
valid_sources[0x10]	26678	1			T3	4		T9	4		T10	10
valid_sources[0x11]	26976	1			T2	2		T3	3		T11	38
valid_sources[0x12]	26582	1			T2	2		T10	2		T11	4
valid_sources[0x13]	26922	1			T2	4		T3	1		T13	2
valid_sources[0x14]	27112	1			T1	15		T3	1		T9	8
valid_sources[0x15]	27460	1			T2	6		T3	2		T9	4
valid_sources[0x16]	26951	1			T2	1		T11	13		T12	7
valid_sources[0x17]	26762	1			T1	3		T2	3		T9	2
valid_sources[0x18]	25893	1			T2	1		T9	1		T10	4
valid_sources[0x19]	27115	1			T1	11		T2	5		T3	1
valid_sources[0x1a]	27475	1			T2	1		T11	10		T12	3
valid_sources[0x1b]	26369	1			T2	1		T3	5		T10	15
valid_sources[0x1c]	27100	1			T3	1		T10	1		T11	1
valid_sources[0x1d]	26392	1			T2	3		T3	4		T10	10
valid_sources[0x1e]	26568	1			T2	1		T3	1		T10	8
valid_sources[0x1f]	26688	1			T2	1		T3	2		T9	7
valid_sources[0x20]	26302	1			T10	24		T11	28		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25135

1

T1

4

T2

2

T3

3

values[0x0]

all_enables

biggest_size

191028

1

T1

11

T2

13

T3

14

values[0x1]

all_enables

biggest_size

24984

1

T1

3

T2

3

T9

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1466938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233207

1

T1

22

T2

21

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	577222	1			T1	51		T2	35		T3	39
values[0x0]	545957	1			T1	55		T2	43		T3	37
values[0x1]	576966	1			T1	41		T2	45		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1134476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

565669

1

T1

51

T2

44

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27529	1			T1	2		T9	2		T10	14
valid_sources[0x01]	26895	1			T1	11		T2	8		T9	4
valid_sources[0x02]	26445	1			T1	6		T9	5		T11	8
valid_sources[0x03]	26969	1			T1	3		T9	3		T10	1
valid_sources[0x04]	26485	1			T1	5		T9	8		T10	5
valid_sources[0x05]	26283	1			T1	2		T2	7		T9	5
valid_sources[0x06]	27605	1			T1	3		T10	5		T11	9
valid_sources[0x07]	27042	1			T1	2		T9	1		T10	13
valid_sources[0x08]	27915	1			T1	4		T9	5		T10	12
valid_sources[0x09]	27183	1			T1	3		T9	4		T10	8
valid_sources[0x0a]	26437	1			T1	10		T10	4		T11	11
valid_sources[0x0b]	25547	1			T1	4		T2	7		T9	1
valid_sources[0x0c]	25988	1			T9	2		T10	1		T11	10
valid_sources[0x0d]	26418	1			T1	2		T2	16		T9	2
valid_sources[0x0e]	26027	1			T3	28		T9	3		T10	5
valid_sources[0x0f]	26172	1			T9	2		T10	8		T11	4
valid_sources[0x10]	27016	1			T9	5		T10	14		T11	9
valid_sources[0x11]	26108	1			T1	4		T3	4		T9	4
valid_sources[0x12]	26141	1			T1	1		T2	10		T9	3
valid_sources[0x13]	26754	1			T1	1		T9	3		T10	19
valid_sources[0x14]	26248	1			T9	3		T10	16		T11	6
valid_sources[0x15]	27022	1			T1	1		T3	5		T9	5
valid_sources[0x16]	27699	1			T1	1		T9	2		T10	7
valid_sources[0x17]	26352	1			T1	3		T2	15		T9	6
valid_sources[0x18]	26163	1			T1	5		T9	1		T10	2
valid_sources[0x19]	26995	1			T9	1		T10	7		T11	7
valid_sources[0x1a]	26546	1			T9	4		T10	13		T11	10
valid_sources[0x1b]	26913	1			T1	3		T10	8		T11	6
valid_sources[0x1c]	26048	1			T9	4		T10	20		T11	6
valid_sources[0x1d]	26098	1			T1	2		T10	11		T11	5
valid_sources[0x1e]	26795	1			T1	5		T10	7		T11	2
valid_sources[0x1f]	25771	1			T1	1		T9	3		T11	7
valid_sources[0x20]	26788	1			T1	1		T2	4		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24630

1

T1

3

T2

1

T3

2

values[0x0]

all_enables

biggest_size

184212

1

T1

19

T2

16

T3

10

values[0x1]

all_enables

biggest_size

24365

1

T2

4

T3

1

T9

3