Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1568014 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 249948 1 T1 20 T2 22 T3 1


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 616190 1 T1 47 T2 58 T3 2
values[0x0] 585832 1 T1 58 T2 59 T8 241
values[0x1] 615940 1 T1 58 T2 71 T3 2


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1212748 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 605214 1 T1 41 T2 55 T3 2


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 28464 1 T1 4 T2 2 T3 1
valid_sources[0x01] 28296 1 T7 2 T10 2 T11 16
valid_sources[0x02] 28309 1 T1 4 T2 3 T7 2
valid_sources[0x03] 28784 1 T1 1 T2 4 T8 52
valid_sources[0x04] 28555 1 T2 6 T11 16 T12 6
valid_sources[0x05] 28491 1 T2 1 T7 3 T10 3
valid_sources[0x06] 28548 1 T1 3 T2 4 T9 1
valid_sources[0x07] 29228 1 T1 1 T11 1 T12 8
valid_sources[0x08] 28020 1 T2 7 T8 271 T7 1
valid_sources[0x09] 28278 1 T1 1 T2 4 T7 1
valid_sources[0x0a] 28071 1 T2 1 T7 6 T9 55
valid_sources[0x0b] 28412 1 T1 4 T2 2 T10 4
valid_sources[0x0c] 29141 1 T2 2 T7 2 T11 21
valid_sources[0x0d] 28348 1 T2 5 T7 5 T10 3
valid_sources[0x0e] 28951 1 T2 1 T7 1 T11 14
valid_sources[0x0f] 28048 1 T1 10 T8 10 T7 2
valid_sources[0x10] 27925 1 T2 2 T11 8 T12 28
valid_sources[0x11] 27743 1 T1 2 T2 1 T7 8
valid_sources[0x12] 28684 1 T2 1 T7 3 T10 5
valid_sources[0x13] 28639 1 T2 3 T7 1 T10 1
valid_sources[0x14] 28717 1 T2 4 T7 5 T11 19
valid_sources[0x15] 28970 1 T2 4 T11 19 T12 5
valid_sources[0x16] 27977 1 T1 1 T2 1 T7 2
valid_sources[0x17] 27562 1 T1 4 T2 1 T7 1
valid_sources[0x18] 28931 1 T1 2 T2 3 T7 4
valid_sources[0x19] 28895 1 T1 3 T2 1 T3 1
valid_sources[0x1a] 27330 1 T1 7 T7 1 T11 20
valid_sources[0x1b] 29003 1 T2 7 T8 274 T7 9
valid_sources[0x1c] 28222 1 T2 9 T7 4 T9 3
valid_sources[0x1d] 28400 1 T1 6 T2 2 T3 1
valid_sources[0x1e] 28900 1 T1 2 T2 1 T7 1
valid_sources[0x1f] 28150 1 T1 2 T2 5 T7 1
valid_sources[0x20] 28740 1 T1 1 T2 2 T7 5


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 26423 1 T1 1 T2 2 T3 1
values[0x0] all_enables biggest_size 197512 1 T1 17 T2 18 T8 78
values[0x1] all_enables biggest_size 26013 1 T1 2 T2 2 T8 12


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1591572 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 258999 1 T1 18 T2 13 T3 1


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 633280 1 T1 31 T2 37 T3 4
values[0x0] 583709 1 T1 41 T2 37 T3 1
values[0x1] 633582 1 T1 49 T2 44 T3 3


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1221667 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 628904 1 T1 35 T2 38 T3 4


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 29127 1 T8 12 T9 4 T11 24
valid_sources[0x01] 28747 1 T8 12 T7 3 T9 1
valid_sources[0x02] 28513 1 T1 1 T8 15 T7 2
valid_sources[0x03] 28402 1 T1 1 T8 9 T7 5
valid_sources[0x04] 29242 1 T2 10 T8 10 T7 3
valid_sources[0x05] 28525 1 T3 1 T8 9 T7 3
valid_sources[0x06] 29036 1 T8 6 T9 2 T10 6
valid_sources[0x07] 28301 1 T3 1 T8 8 T7 1
valid_sources[0x08] 28860 1 T1 14 T2 1 T8 9
valid_sources[0x09] 29016 1 T1 15 T8 20 T9 1
valid_sources[0x0a] 28262 1 T1 9 T8 12 T7 6
valid_sources[0x0b] 28969 1 T8 21 T7 2 T10 5
valid_sources[0x0c] 28632 1 T1 7 T8 7 T7 2
valid_sources[0x0d] 28498 1 T2 1 T3 1 T8 11
valid_sources[0x0e] 29449 1 T1 1 T8 12 T7 1
valid_sources[0x0f] 29210 1 T8 7 T7 4 T9 2
valid_sources[0x10] 29105 1 T3 1 T8 12 T7 3
valid_sources[0x11] 28746 1 T1 4 T2 1 T8 10
valid_sources[0x12] 29664 1 T2 8 T8 15 T7 3
valid_sources[0x13] 28973 1 T1 6 T8 11 T9 1
valid_sources[0x14] 29005 1 T8 11 T7 1 T9 3
valid_sources[0x15] 29202 1 T1 11 T8 16 T7 3
valid_sources[0x16] 28746 1 T8 11 T7 2 T9 1
valid_sources[0x17] 28609 1 T8 8 T9 2 T10 2
valid_sources[0x18] 28982 1 T1 2 T8 9 T9 3
valid_sources[0x19] 28652 1 T8 8 T11 3 T12 36
valid_sources[0x1a] 28718 1 T2 1 T8 20 T7 1
valid_sources[0x1b] 29415 1 T8 15 T9 2 T10 2
valid_sources[0x1c] 28596 1 T2 19 T8 21 T7 2
valid_sources[0x1d] 28577 1 T2 9 T8 20 T7 2
valid_sources[0x1e] 30431 1 T1 2 T8 6 T7 7
valid_sources[0x1f] 28856 1 T8 12 T7 1 T9 1
valid_sources[0x20] 29035 1 T8 12 T7 1 T9 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 27067 1 T1 1 T8 8 T7 4
values[0x0] all_enables biggest_size 204679 1 T1 14 T2 13 T3 1
values[0x1] all_enables biggest_size 27253 1 T1 3 T8 5 T7 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1584819 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 251819 1 T1 24 T2 12 T8 106


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 623973 1 T1 58 T2 36 T3 4
values[0x0] 590634 1 T1 55 T2 31 T8 253
values[0x1] 622031 1 T1 48 T2 34 T3 2


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1224026 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 612612 1 T1 57 T2 35 T3 1


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 28469 1 T1 7 T10 4 T11 8
valid_sources[0x01] 29374 1 T1 11 T7 6 T10 2
valid_sources[0x02] 29596 1 T1 18 T2 2 T7 5
valid_sources[0x03] 28360 1 T2 1 T3 1 T7 11
valid_sources[0x04] 28354 1 T2 2 T9 1 T10 5
valid_sources[0x05] 27745 1 T2 1 T11 22 T12 65
valid_sources[0x06] 29683 1 T2 2 T8 181 T7 2
valid_sources[0x07] 29038 1 T2 4 T7 3 T11 11
valid_sources[0x08] 29846 1 T10 2 T11 16 T12 42
valid_sources[0x09] 28377 1 T2 4 T8 83 T7 6
valid_sources[0x0a] 29378 1 T1 6 T7 1 T9 51
valid_sources[0x0b] 29383 1 T2 7 T7 2 T10 3
valid_sources[0x0c] 28865 1 T1 7 T10 3 T11 16
valid_sources[0x0d] 27937 1 T2 1 T9 24 T10 1
valid_sources[0x0e] 28753 1 T3 3 T10 5 T11 26
valid_sources[0x0f] 28744 1 T2 4 T9 13 T10 1
valid_sources[0x10] 28816 1 T2 1 T7 2 T10 3
valid_sources[0x11] 28362 1 T8 20 T10 1 T11 10
valid_sources[0x12] 29279 1 T1 16 T8 2 T7 2
valid_sources[0x13] 28250 1 T2 3 T7 9 T9 3
valid_sources[0x14] 28635 1 T2 2 T10 2 T11 25
valid_sources[0x15] 28686 1 T2 5 T8 112 T7 15
valid_sources[0x16] 28452 1 T10 2 T11 10 T12 65
valid_sources[0x17] 28465 1 T2 7 T7 7 T11 11
valid_sources[0x18] 28534 1 T2 2 T10 1 T11 23
valid_sources[0x19] 29634 1 T1 5 T2 2 T7 2
valid_sources[0x1a] 28131 1 T10 2 T11 14 T12 34
valid_sources[0x1b] 28451 1 T8 83 T11 9 T12 49
valid_sources[0x1c] 28566 1 T1 11 T2 2 T9 16
valid_sources[0x1d] 28166 1 T8 3 T10 2 T11 7
valid_sources[0x1e] 29014 1 T1 13 T2 2 T7 2
valid_sources[0x1f] 28638 1 T2 5 T10 2 T11 35
valid_sources[0x20] 28940 1 T1 5 T8 12 T10 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 26496 1 T1 3 T8 13 T7 2
values[0x0] all_enables biggest_size 198898 1 T1 17 T2 10 T8 75
values[0x1] all_enables biggest_size 26425 1 T1 4 T2 2 T8 18