Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	411341	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	411341	0	0
T1	2071	4	0	0
T2	13197	15	0	0
T3	3524	10	0	0
T7	13369	4	0	0
T8	3945	0	0	0
T9	2006	5	0	0
T10	1411	3	0	0
T11	27495	88	0	0
T12	18102	120	0	0
T13	4146	4	0	0
T14	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	753224	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	753224	0	0
T1	2071	4	0	0
T2	13197	8	0	0
T3	3524	13	0	0
T7	13369	4	0	0
T8	3945	0	0	0
T9	2006	5	0	0
T10	1411	3	0	0
T11	27495	43	0	0
T12	18102	118	0	0
T13	4146	15	0	0
T14	0	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	395378	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	395378	0	0
T1	2071	6	0	0
T2	13197	4	0	0
T3	3524	24	0	0
T7	13369	31	0	0
T8	3945	0	0	0
T9	2006	9	0	0
T10	1411	4	0	0
T11	27495	125	0	0
T12	18102	109	0	0
T13	4146	3	0	0
T14	0	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	732447	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	732447	0	0
T1	2071	6	0	0
T2	13197	4	0	0
T3	3524	11	0	0
T7	13369	11	0	0
T8	3945	0	0	0
T9	2006	9	0	0
T10	1411	4	0	0
T11	27495	64	0	0
T12	18102	105	0	0
T13	4146	3	0	0
T14	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	453310	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	453310	0	0
T1	2071	11	0	0
T2	13197	6	0	0
T3	3524	4	0	0
T7	13369	13	0	0
T8	3945	0	0	0
T9	2006	6	0	0
T10	1411	4	0	0
T11	27495	78	0	0
T12	18102	122	0	0
T13	4146	4	0	0
T14	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	675955	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	675955	0	0
T1	2071	11	0	0
T2	13197	6	0	0
T3	3524	4	0	0
T7	13369	5	0	0
T8	3945	0	0	0
T9	2006	6	0	0
T10	1411	4	0	0
T11	27495	51	0	0
T12	18102	122	0	0
T13	4146	4	0	0
T14	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	359877	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	359877	0	0
T1	2071	6	0	0
T2	13197	5	0	0
T3	3524	6	0	0
T7	13369	4	0	0
T8	3945	0	0	0
T9	2006	13	0	0
T10	1411	2	0	0
T11	27495	97	0	0
T12	18102	121	0	0
T13	4146	1	0	0
T14	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	798323	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	798323	0	0
T1	2071	6	0	0
T2	13197	5	0	0
T3	3524	5	0	0
T7	13369	9	0	0
T8	3945	0	0	0
T9	2006	13	0	0
T10	1411	2	0	0
T11	27495	61	0	0
T12	18102	120	0	0
T13	4146	1	0	0
T14	0	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	412511	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	412511	0	0
T1	2071	5	0	0
T2	13197	8	0	0
T3	3524	4	0	0
T7	13369	8	0	0
T8	3945	0	0	0
T9	2006	10	0	0
T10	1411	7	0	0
T11	27495	67	0	0
T12	18102	117	0	0
T13	4146	21	0	0
T14	0	133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	723586	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	723586	0	0
T1	2071	5	0	0
T2	13197	6	0	0
T3	3524	4	0	0
T7	13369	16	0	0
T8	3945	0	0	0
T9	2006	10	0	0
T10	1411	7	0	0
T11	27495	53	0	0
T12	18102	113	0	0
T13	4146	18	0	0
T14	0	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0