Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	726623	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	726623	0	0
T1	2071	14	0	0
T2	13197	29	0	0
T3	3524	1	0	0
T7	13369	9	0	0
T8	3945	0	0	0
T9	2006	14	0	0
T10	1411	5	0	0
T11	27495	50	0	0
T12	18102	220	0	0
T13	4146	6	0	0
T14	0	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	4386804	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	4386804	0	0
T1	2071	9	0	0
T2	13197	21	0	0
T3	3524	1	0	0
T7	13369	66	0	0
T8	3945	0	0	0
T9	2006	10	0	0
T10	1411	5	0	0
T11	27495	156	0	0
T12	18102	91	0	0
T13	4146	21	0	0
T14	0	481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	649966	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	649966	0	0
T1	2071	8	0	0
T2	13197	8	0	0
T3	3524	38	0	0
T7	13369	8	0	0
T8	3945	0	0	0
T9	2006	4	0	0
T10	1411	3	0	0
T11	27495	46	0	0
T12	18102	621	0	0
T13	4146	4	0	0
T14	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	4259942	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	4259942	0	0
T1	2071	8	0	0
T2	13197	13	0	0
T3	3524	7	0	0
T7	13369	56	0	0
T8	3945	0	0	0
T9	2006	4	0	0
T10	1411	3	0	0
T11	27495	219	0	0
T12	18102	111	0	0
T13	4146	17	0	0
T14	0	324	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	748947	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	748947	0	0
T1	2071	4	0	0
T2	13197	8	0	0
T3	3524	4	0	0
T7	13369	72	0	0
T8	3945	0	0	0
T9	2006	3	0	0
T10	1411	1	0	0
T11	27495	47	0	0
T12	18102	160	0	0
T13	4146	5	0	0
T14	0	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	4239700	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	4239700	0	0
T1	2071	4	0	0
T2	13197	26	0	0
T3	3524	4	0	0
T7	13369	125	0	0
T8	3945	0	0	0
T9	2006	3	0	0
T10	1411	1	0	0
T11	27495	191	0	0
T12	18102	101	0	0
T13	4146	53	0	0
T14	0	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	303990	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	303990	0	0
T1	2071	11	0	0
T2	13197	14	0	0
T3	3524	10	0	0
T7	13369	8	0	0
T8	3945	1848	0	0
T9	2006	4	0	0
T10	1411	5	0	0
T11	27495	61	0	0
T12	18102	79	0	0
T13	4146	0	0	0
T14	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3652706	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3652706	0	0
T1	2071	10	0	0
T2	13197	50	0	0
T3	3524	15	0	0
T7	13369	58	0	0
T8	3945	504	0	0
T9	2006	4	0	0
T10	1411	4	0	0
T11	27495	116	0	0
T12	18102	75	0	0
T13	4146	0	0	0
T14	0	368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	333049	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	333049	0	0
T1	2071	4	0	0
T2	13197	17	0	0
T3	3524	6	0	0
T7	13369	3	0	0
T8	3945	0	0	0
T9	2006	6	0	0
T10	1411	1	0	0
T11	27495	56	0	0
T12	18102	112	0	0
T13	4146	3	0	0
T14	0	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3636624	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3636624	0	0
T1	2071	4	0	0
T2	13197	13	0	0
T3	3524	9	0	0
T7	13369	15	0	0
T8	3945	0	0	0
T9	2006	4	0	0
T10	1411	1	0	0
T11	27495	74	0	0
T12	18102	102	0	0
T13	4146	24	0	0
T14	0	523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	451728	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	451728	0	0
T1	2071	6	0	0
T2	13197	10	0	0
T3	3524	5	0	0
T7	13369	2	0	0
T8	3945	1693	0	0
T9	2006	4	0	0
T10	1411	1	0	0
T11	27495	108	0	0
T12	18102	118	0	0
T13	4146	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3028767	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3028767	0	0
T1	2071	6	0	0
T2	13197	22	0	0
T3	3524	7	0	0
T7	13369	24	0	0
T8	3945	284	0	0
T9	2006	4	0	0
T10	1411	1	0	0
T11	27495	86	0	0
T12	18102	105	0	0
T13	4146	130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	325652	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	325652	0	0
T1	2071	10	0	0
T2	13197	7	0	0
T3	3524	3	0	0
T7	13369	12	0	0
T8	3945	0	0	0
T9	2006	12	0	0
T10	1411	6	0	0
T11	27495	43	0	0
T12	18102	118	0	0
T13	4146	6	0	0
T14	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3677636	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3677636	0	0
T1	2071	9	0	0
T2	13197	27	0	0
T3	3524	3	0	0
T7	13369	24	0	0
T8	3945	0	0	0
T9	2006	9	0	0
T10	1411	5	0	0
T11	27495	64	0	0
T12	18102	104	0	0
T13	4146	54	0	0
T14	0	376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0