Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	292614	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	292614	0	0
T1	2071	5	0	0
T2	13197	6	0	0
T3	3524	5	0	0
T7	13369	6	0	0
T8	3945	0	0	0
T9	2006	9	0	0
T10	1411	9	0	0
T11	27495	45	0	0
T12	18102	92	0	0
T13	4146	4	0	0
T14	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3717307	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3717307	0	0
T1	2071	5	0	0
T2	13197	44	0	0
T3	3524	5	0	0
T7	13369	59	0	0
T8	3945	0	0	0
T9	2006	7	0	0
T10	1411	8	0	0
T11	27495	80	0	0
T12	18102	84	0	0
T13	4146	18	0	0
T14	0	298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	300332	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	300332	0	0
T1	2071	6	0	0
T2	13197	7	0	0
T3	3524	10	0	0
T7	13369	10	0	0
T8	3945	0	0	0
T9	2006	9	0	0
T10	1411	3	0	0
T11	27495	49	0	0
T12	18102	126	0	0
T13	4146	6	0	0
T14	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3391754	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3391754	0	0
T1	2071	6	0	0
T2	13197	34	0	0
T3	3524	6	0	0
T7	13369	78	0	0
T8	3945	0	0	0
T9	2006	9	0	0
T10	1411	2	0	0
T11	27495	90	0	0
T12	18102	113	0	0
T13	4146	24	0	0
T14	0	502	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	312999	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	312999	0	0
T1	2071	8	0	0
T2	13197	5	0	0
T3	3524	4	0	0
T7	13369	10	0	0
T8	3945	0	0	0
T9	2006	10	0	0
T10	1411	3	0	0
T11	27495	106	0	0
T12	18102	91	0	0
T13	4146	12	0	0
T14	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3639477	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3639477	0	0
T1	2071	7	0	0
T2	13197	16	0	0
T3	3524	4	0	0
T7	13369	53	0	0
T8	3945	0	0	0
T9	2006	10	0	0
T10	1411	3	0	0
T11	27495	152	0	0
T12	18102	86	0	0
T13	4146	28	0	0
T14	0	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	291093	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	291093	0	0
T1	2071	13	0	0
T2	13197	6	0	0
T3	3524	6	0	0
T7	13369	11	0	0
T8	3945	0	0	0
T9	2006	3	0	0
T10	1411	4	0	0
T11	27495	59	0	0
T12	18102	132	0	0
T13	4146	5	0	0
T14	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	2952964	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	2952964	0	0
T1	2071	11	0	0
T2	13197	8	0	0
T3	3524	9	0	0
T7	13369	89	0	0
T8	3945	0	0	0
T9	2006	3	0	0
T10	1411	4	0	0
T11	27495	117	0	0
T12	18102	116	0	0
T13	4146	49	0	0
T14	0	320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	273484	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	273484	0	0
T1	2071	5	0	0
T2	13197	6	0	0
T3	3524	4	0	0
T7	13369	11	0	0
T8	3945	0	0	0
T9	2006	10	0	0
T10	1411	1	0	0
T11	27495	46	0	0
T12	18102	113	0	0
T13	4146	4	0	0
T14	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3585411	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3585411	0	0
T1	2071	5	0	0
T2	13197	7	0	0
T3	3524	4	0	0
T7	13369	51	0	0
T8	3945	0	0	0
T9	2006	8	0	0
T10	1411	1	0	0
T11	27495	115	0	0
T12	18102	104	0	0
T13	4146	41	0	0
T14	0	446	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	280439	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	280439	0	0
T1	2071	15	0	0
T2	13197	15	0	0
T3	3524	4	0	0
T7	13369	11	0	0
T8	3945	0	0	0
T9	2006	4	0	0
T10	1411	4	0	0
T11	27495	51	0	0
T12	18102	95	0	0
T13	4146	9	0	0
T14	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3796737	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3796737	0	0
T1	2071	12	0	0
T2	13197	32	0	0
T3	3524	4	0	0
T7	13369	72	0	0
T8	3945	0	0	0
T9	2006	4	0	0
T10	1411	4	0	0
T11	27495	117	0	0
T12	18102	87	0	0
T13	4146	59	0	0
T14	0	589	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	305540	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	305540	0	0
T1	2071	3	0	0
T2	13197	8	0	0
T3	3524	3	0	0
T7	13369	6	0	0
T8	3945	0	0	0
T9	2006	7	0	0
T10	1411	2	0	0
T11	27495	46	0	0
T12	18102	95	0	0
T13	4146	3	0	0
T14	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430217806	3555451	0	0
DepthKnown_A	430217806	430092490	0	0
RvalidKnown_A	430217806	430092490	0	0
WreadyKnown_A	430217806	430092490	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	3555451	0	0
T1	2071	3	0	0
T2	13197	8	0	0
T3	3524	12	0	0
T7	13369	18	0	0
T8	3945	0	0	0
T9	2006	6	0	0
T10	1411	2	0	0
T11	27495	100	0	0
T12	18102	84	0	0
T13	4146	42	0	0
T14	0	453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	430092490	0	0
T1	2071	2020	0	0
T2	13197	13140	0	0
T3	3524	3502	0	0
T7	13369	13253	0	0
T8	3945	3905	0	0
T9	2006	1961	0	0
T10	1411	1405	0	0
T11	27495	27482	0	0
T12	18102	18052	0	0
T13	4146	4090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0