Unified Coverage Report :: Module

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7823991	0	0
GntImpliesValid_A	2147483647	7823991	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7823991	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	465886571	0	0
ReadyAndValidImplyGrant_A	2147483647	7823991	0	0
ReqAndReadyImplyGrant_A	2147483647	7823991	0	0
ReqImpliesValid_A	2147483647	34240674	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44534	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7823991	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	49704	48480
T2	316728	315360
T3	84576	84048
T7	320856	318072
T8	94680	93720
T9	48144	47064
T10	33864	33720
T11	659880	659568
T12	434448	433248
T13	99504	98160

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	21600	21600
T1	24	24
T2	24	24
T3	24	24
T7	24	24
T8	24	24
T9	24	24
T10	24	24
T11	24	24
T12	24	24
T13	24	24

GntImpliesReady_A

Name	Attempts	Real Successes
Total	2147483647	7823991
T1	49704	445
T2	316728	407
T3	84576	377
T7	320856	462
T8	94680	2318
T9	48144	440
T10	33864	395
T11	659880	3369
T12	434448	7488
T13	99504	302
T14	0	2353

GntImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	7823991
T1	49704	445
T2	316728	407
T3	84576	377
T7	320856	462
T8	94680	2318
T9	48144	440
T10	33864	395
T11	659880	3369
T12	434448	7488
T13	99504	302
T14	0	2353

GrantKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	49704	48480
T2	316728	315360
T3	84576	84048
T7	320856	318072
T8	94680	93720
T9	48144	47064
T10	33864	33720
T11	659880	659568
T12	434448	433248
T13	99504	98160

IdxKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	49704	48480
T2	316728	315360
T3	84576	84048
T7	320856	318072
T8	94680	93720
T9	48144	47064
T10	33864	33720
T11	659880	659568
T12	434448	433248
T13	99504	98160

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	2147483647	7823991
T1	49704	445
T2	316728	407
T3	84576	377
T7	320856	462
T8	94680	2318
T9	48144	440
T10	33864	395
T11	659880	3369
T12	434448	7488
T13	99504	302
T14	0	2353

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	2147483647	465886571
T1	49704	558
T2	316728	15850
T3	84576	5526
T7	320856	15152
T8	94680	240
T9	48144	545
T10	33864	356
T11	659880	43636
T12	434448	14267
T13	99504	5715
T14	0	6433

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	7823991
T1	49704	445
T2	316728	407
T3	84576	377
T7	320856	462
T8	94680	2318
T9	48144	440
T10	33864	395
T11	659880	3369
T12	434448	7488
T13	99504	302
T14	0	2353

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	7823991
T1	49704	445
T2	316728	407
T3	84576	377
T7	320856	462
T8	94680	2318
T9	48144	440
T10	33864	395
T11	659880	3369
T12	434448	7488
T13	99504	302
T14	0	2353

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	34240674
T1	49704	501
T2	316728	876
T3	84576	903
T7	320856	1139
T8	94680	4154
T9	48144	495
T10	33864	439
T11	659880	7743
T12	434448	9438
T13	99504	705
T14	0	3312

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	2147483647	44534	21600
T12	36204	29	2
T13	8292	0	2
T14	129390	1	2
T15	27408	29	2
T16	127636	2	2
T17	261342	1	2
T18	0	20	0
T19	0	1	0
T20	0	8	0
T21	0	3	0
T22	0	3	0
T23	0	7	0
T24	0	32	0
T25	359630	0	2
T26	5370	0	2
T27	5858	0	2
T28	24334	0	2

ValidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	49704	48480
T2	316728	315360
T3	84576	84048
T7	320856	318072
T8	94680	93720
T9	48144	47064
T10	33864	33720
T11	659880	659568
T12	434448	433248
T13	99504	98160

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	2147483647	7823991
T1	49704	445
T2	316728	407
T3	84576	377
T7	320856	462
T8	94680	2318
T9	48144	440
T10	33864	395
T11	659880	3369
T12	434448	7488
T13	99504	302
T14	0	2353

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	883679	0	0
GntImpliesValid_A	430217806	883679	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	883679	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	12145216	0	0
ReadyAndValidImplyGrant_A	430217806	883679	0	0
ReqAndReadyImplyGrant_A	430217806	883679	0	0
ReqImpliesValid_A	430217806	2606750	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	883679	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	883679
T1	2071	55
T2	13197	43
T3	3524	47
T7	13369	43
T8	3945	100
T9	2006	41
T10	1411	61
T11	27495	351
T12	18102	817
T13	4146	36

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	883679
T1	2071	55
T2	13197	43
T3	3524	47
T7	13369	43
T8	3945	100
T9	2006	41
T10	1411	61
T11	27495	351
T12	18102	817
T13	4146	36

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	883679
T1	2071	55
T2	13197	43
T3	3524	47
T7	13369	43
T8	3945	100
T9	2006	41
T10	1411	61
T11	27495	351
T12	18102	817
T13	4146	36

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	12145216
T1	2071	40
T2	13197	308
T3	3524	346
T7	13369	266
T8	3945	82
T9	2006	33
T10	1411	46
T11	27495	2483
T12	18102	607
T13	4146	249

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	883679
T1	2071	55
T2	13197	43
T3	3524	47
T7	13369	43
T8	3945	100
T9	2006	41
T10	1411	61
T11	27495	351
T12	18102	817
T13	4146	36

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	883679
T1	2071	55
T2	13197	43
T3	3524	47
T7	13369	43
T8	3945	100
T9	2006	41
T10	1411	61
T11	27495	351
T12	18102	817
T13	4146	36

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	2606750
T1	2071	71
T2	13197	63
T3	3524	93
T7	13369	54
T8	3945	119
T9	2006	50
T10	1411	77
T11	27495	599
T12	18102	1028
T13	4146	140

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	883679
T1	2071	55
T2	13197	43
T3	3524	47
T7	13369	43
T8	3945	100
T9	2006	41
T10	1411	61
T11	27495	351
T12	18102	817
T13	4146	36

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	853031	0	0
GntImpliesValid_A	430217806	853031	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	853031	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	11968093	0	0
ReadyAndValidImplyGrant_A	430217806	853031	0	0
ReqAndReadyImplyGrant_A	430217806	853031	0	0
ReqImpliesValid_A	430217806	2400805	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	853031	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	853031
T1	2071	44
T2	13197	37
T3	3524	41
T7	13369	54
T8	3945	987
T9	2006	48
T10	1411	53
T11	27495	372
T12	18102	811
T13	4146	40

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	853031
T1	2071	44
T2	13197	37
T3	3524	41
T7	13369	54
T8	3945	987
T9	2006	48
T10	1411	53
T11	27495	372
T12	18102	811
T13	4146	40

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	853031
T1	2071	44
T2	13197	37
T3	3524	41
T7	13369	54
T8	3945	987
T9	2006	48
T10	1411	53
T11	27495	372
T12	18102	811
T13	4146	40

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	11968093
T1	2071	33
T2	13197	307
T3	3524	290
T7	13369	360
T8	3945	99
T9	2006	35
T10	1411	43
T11	27495	2741
T12	18102	612
T13	4146	303

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	853031
T1	2071	44
T2	13197	37
T3	3524	41
T7	13369	54
T8	3945	987
T9	2006	48
T10	1411	53
T11	27495	372
T12	18102	811
T13	4146	40

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	853031
T1	2071	44
T2	13197	37
T3	3524	41
T7	13369	54
T8	3945	987
T9	2006	48
T10	1411	53
T11	27495	372
T12	18102	811
T13	4146	40

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	2400805
T1	2071	56
T2	13197	50
T3	3524	67
T7	13369	65
T8	3945	1876
T9	2006	62
T10	1411	64
T11	27495	701
T12	18102	1011
T13	4146	98

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	853031
T1	2071	44
T2	13197	37
T3	3524	41
T7	13369	54
T8	3945	987
T9	2006	48
T10	1411	53
T11	27495	372
T12	18102	811
T13	4146	40

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T10
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	215780	0	0
GntImpliesValid_A	430217806	215780	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	215780	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2953879	0	0
ReadyAndValidImplyGrant_A	430217806	215780	0	0
ReqAndReadyImplyGrant_A	430217806	215780	0	0
ReqImpliesValid_A	430217806	565259	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	215780	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	215780
T1	2071	18
T2	13197	11
T3	3524	17
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	16
T11	27495	84
T12	18102	196
T13	4146	9
T14	0	131

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	215780
T1	2071	18
T2	13197	11
T3	3524	17
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	16
T11	27495	84
T12	18102	196
T13	4146	9
T14	0	131

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	215780
T1	2071	18
T2	13197	11
T3	3524	17
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	16
T11	27495	84
T12	18102	196
T13	4146	9
T14	0	131

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2953879
T1	2071	19
T2	13197	74
T3	3524	80
T7	13369	81
T8	3945	1
T9	2006	15
T10	1411	16
T11	27495	564
T12	18102	186
T13	4146	90

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	215780
T1	2071	18
T2	13197	11
T3	3524	17
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	16
T11	27495	84
T12	18102	196
T13	4146	9
T14	0	131

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	215780
T1	2071	18
T2	13197	11
T3	3524	17
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	16
T11	27495	84
T12	18102	196
T13	4146	9
T14	0	131

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	565259
T1	2071	18
T2	13197	11
T3	3524	22
T7	13369	10
T8	3945	0
T9	2006	16
T10	1411	17
T11	27495	118
T12	18102	207
T13	4146	10
T14	0	180

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	215780
T1	2071	18
T2	13197	11
T3	3524	17
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	16
T11	27495	84
T12	18102	196
T13	4146	9
T14	0	131

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T11

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	204542	0	0
GntImpliesValid_A	430217806	204542	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	204542	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3014577	0	0
ReadyAndValidImplyGrant_A	430217806	204542	0	0
ReqAndReadyImplyGrant_A	430217806	204542	0	0
ReqImpliesValid_A	430217806	541765	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	204542	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	204542
T1	2071	17
T2	13197	11
T3	3524	9
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	89
T12	18102	218
T13	4146	17
T14	0	121

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	204542
T1	2071	17
T2	13197	11
T3	3524	9
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	89
T12	18102	218
T13	4146	17
T14	0	121

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	204542
T1	2071	17
T2	13197	11
T3	3524	9
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	89
T12	18102	218
T13	4146	17
T14	0	121

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3014577
T1	2071	16
T2	13197	79
T3	3524	88
T7	13369	65
T8	3945	1
T9	2006	8
T10	1411	10
T11	27495	690
T12	18102	202
T13	4146	141

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	204542
T1	2071	17
T2	13197	11
T3	3524	9
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	89
T12	18102	218
T13	4146	17
T14	0	121

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	204542
T1	2071	17
T2	13197	11
T3	3524	9
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	89
T12	18102	218
T13	4146	17
T14	0	121

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	541765
T1	2071	19
T2	13197	11
T3	3524	14
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	150
T12	18102	235
T13	4146	17
T14	0	145

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	204542
T1	2071	17
T2	13197	11
T3	3524	9
T7	13369	11
T8	3945	0
T9	2006	7
T10	1411	9
T11	27495	89
T12	18102	218
T13	4146	17
T14	0	121

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	203399	0	0
GntImpliesValid_A	430217806	203399	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	203399	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	4891121	0	0
ReadyAndValidImplyGrant_A	430217806	203399	0	0
ReqAndReadyImplyGrant_A	430217806	203399	0	0
ReqImpliesValid_A	430217806	881614	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	203399	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	203399
T1	2071	13
T2	13197	11
T3	3524	9
T7	13369	14
T8	3945	0
T9	2006	14
T10	1411	9
T11	27495	101
T12	18102	190
T13	4146	8
T14	0	135

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	203399
T1	2071	13
T2	13197	11
T3	3524	9
T7	13369	14
T8	3945	0
T9	2006	14
T10	1411	9
T11	27495	101
T12	18102	190
T13	4146	8
T14	0	135

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	203399
T1	2071	13
T2	13197	11
T3	3524	9
T7	13369	14
T8	3945	0
T9	2006	14
T10	1411	9
T11	27495	101
T12	18102	190
T13	4146	8
T14	0	135

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	4891121
T1	2071	65
T2	13197	135
T3	3524	57
T7	13369	181
T8	3945	0
T9	2006	64
T10	1411	24
T11	27495	918
T12	18102	2700
T13	4146	91
T14	0	1629

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	203399
T1	2071	13
T2	13197	11
T3	3524	9
T7	13369	14
T8	3945	0
T9	2006	14
T10	1411	9
T11	27495	101
T12	18102	190
T13	4146	8
T14	0	135

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	203399
T1	2071	13
T2	13197	11
T3	3524	9
T7	13369	14
T8	3945	0
T9	2006	14
T10	1411	9
T11	27495	101
T12	18102	190
T13	4146	8
T14	0	135

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	881614
T1	2071	18
T2	13197	11
T3	3524	13
T7	13369	31
T8	3945	0
T9	2006	17
T10	1411	16
T11	27495	183
T12	18102	417
T13	4146	8
T14	0	197

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	203399
T1	2071	13
T2	13197	11
T3	3524	9
T7	13369	14
T8	3945	0
T9	2006	14
T10	1411	9
T11	27495	101
T12	18102	190
T13	4146	8
T14	0	135

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	219054	0	0
GntImpliesValid_A	430217806	219054	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	219054	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	5483610	0	0
ReadyAndValidImplyGrant_A	430217806	219054	0	0
ReqAndReadyImplyGrant_A	430217806	219054	0	0
ReqImpliesValid_A	430217806	1247672	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	219054	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	219054
T1	2071	15
T2	13197	14
T3	3524	5
T7	13369	12
T8	3945	0
T9	2006	18
T10	1411	9
T11	27495	83
T12	18102	214
T13	4146	6
T14	0	119

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	219054
T1	2071	15
T2	13197	14
T3	3524	5
T7	13369	12
T8	3945	0
T9	2006	18
T10	1411	9
T11	27495	83
T12	18102	214
T13	4146	6
T14	0	119

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	219054
T1	2071	15
T2	13197	14
T3	3524	5
T7	13369	12
T8	3945	0
T9	2006	18
T10	1411	9
T11	27495	83
T12	18102	214
T13	4146	6
T14	0	119

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	5483610
T1	2071	74
T2	13197	248
T3	3524	86
T7	13369	84
T8	3945	0
T9	2006	80
T10	1411	40
T11	27495	535
T12	18102	1699
T13	4146	89
T14	0	1133

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219054
T1	2071	15
T2	13197	14
T3	3524	5
T7	13369	12
T8	3945	0
T9	2006	18
T10	1411	9
T11	27495	83
T12	18102	214
T13	4146	6
T14	0	119

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219054
T1	2071	15
T2	13197	14
T3	3524	5
T7	13369	12
T8	3945	0
T9	2006	18
T10	1411	9
T11	27495	83
T12	18102	214
T13	4146	6
T14	0	119

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	1247672
T1	2071	23
T2	13197	34
T3	3524	5
T7	13369	20
T8	3945	0
T9	2006	22
T10	1411	9
T11	27495	112
T12	18102	405
T13	4146	8
T14	0	139

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	219054
T1	2071	15
T2	13197	14
T3	3524	5
T7	13369	12
T8	3945	0
T9	2006	18
T10	1411	9
T11	27495	83
T12	18102	214
T13	4146	6
T14	0	119

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T10
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	219349	0	0
GntImpliesValid_A	430217806	219349	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	219349	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	4889712	0	0
ReadyAndValidImplyGrant_A	430217806	219349	0	0
ReqAndReadyImplyGrant_A	430217806	219349	0	0
ReqImpliesValid_A	430217806	1090414	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	219349	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	219349
T1	2071	13
T2	13197	16
T3	3524	11
T7	13369	12
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	86
T12	18102	236
T13	4146	5
T14	0	102

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	219349
T1	2071	13
T2	13197	16
T3	3524	11
T7	13369	12
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	86
T12	18102	236
T13	4146	5
T14	0	102

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	219349
T1	2071	13
T2	13197	16
T3	3524	11
T7	13369	12
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	86
T12	18102	236
T13	4146	5
T14	0	102

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	4889712
T1	2071	78
T2	13197	820
T3	3524	95
T7	13369	168
T8	3945	0
T9	2006	67
T10	1411	37
T11	27495	386
T12	18102	4204
T13	4146	72
T14	0	962

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219349
T1	2071	13
T2	13197	16
T3	3524	11
T7	13369	12
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	86
T12	18102	236
T13	4146	5
T14	0	102

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219349
T1	2071	13
T2	13197	16
T3	3524	11
T7	13369	12
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	86
T12	18102	236
T13	4146	5
T14	0	102

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	1090414
T1	2071	13
T2	13197	16
T3	3524	79
T7	13369	12
T8	3945	0
T9	2006	24
T10	1411	16
T11	27495	91
T12	18102	1051
T13	4146	5
T14	0	150

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	219349
T1	2071	13
T2	13197	16
T3	3524	11
T7	13369	12
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	86
T12	18102	236
T13	4146	5
T14	0	102

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	223788	0	0
GntImpliesValid_A	430217806	223788	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	223788	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	5742192	0	0
ReadyAndValidImplyGrant_A	430217806	223788	0	0
ReqAndReadyImplyGrant_A	430217806	223788	0	0
ReqImpliesValid_A	430217806	1237020	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	223788	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	223788
T1	2071	8
T2	13197	11
T3	3524	10
T7	13369	21
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	101
T12	18102	230
T13	4146	8
T14	0	129

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	223788
T1	2071	8
T2	13197	11
T3	3524	10
T7	13369	21
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	101
T12	18102	230
T13	4146	8
T14	0	129

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	223788
T1	2071	8
T2	13197	11
T3	3524	10
T7	13369	21
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	101
T12	18102	230
T13	4146	8
T14	0	129

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	5742192
T1	2071	45
T2	13197	750
T3	3524	137
T7	13369	614
T8	3945	0
T9	2006	45
T10	1411	10
T11	27495	427
T12	18102	1234
T13	4146	149
T14	0	2709

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	223788
T1	2071	8
T2	13197	11
T3	3524	10
T7	13369	21
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	101
T12	18102	230
T13	4146	8
T14	0	129

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	223788
T1	2071	8
T2	13197	11
T3	3524	10
T7	13369	21
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	101
T12	18102	230
T13	4146	8
T14	0	129

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	1237020
T1	2071	12
T2	13197	11
T3	3524	10
T7	13369	97
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	122
T12	18102	358
T13	4146	37
T14	0	410

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	223788
T1	2071	8
T2	13197	11
T3	3524	10
T7	13369	21
T8	3945	0
T9	2006	7
T10	1411	3
T11	27495	101
T12	18102	230
T13	4146	8
T14	0	129

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	219253	0	0
GntImpliesValid_A	430217806	219253	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	219253	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3025571	0	0
ReadyAndValidImplyGrant_A	430217806	219253	0	0
ReqAndReadyImplyGrant_A	430217806	219253	0	0
ReqImpliesValid_A	430217806	582820	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	219253	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	219253
T1	2071	12
T2	13197	18
T3	3524	16
T7	13369	13
T8	3945	969
T9	2006	7
T10	1411	12
T11	27495	113
T12	18102	196
T13	4146	6

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	219253
T1	2071	12
T2	13197	18
T3	3524	16
T7	13369	13
T8	3945	969
T9	2006	7
T10	1411	12
T11	27495	113
T12	18102	196
T13	4146	6

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	219253
T1	2071	12
T2	13197	18
T3	3524	16
T7	13369	13
T8	3945	969
T9	2006	7
T10	1411	12
T11	27495	113
T12	18102	196
T13	4146	6

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3025571
T1	2071	12
T2	13197	137
T3	3524	110
T7	13369	93
T8	3945	42
T9	2006	8
T10	1411	12
T11	27495	880
T12	18102	192
T13	4146	44

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219253
T1	2071	12
T2	13197	18
T3	3524	16
T7	13369	13
T8	3945	969
T9	2006	7
T10	1411	12
T11	27495	113
T12	18102	196
T13	4146	6

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219253
T1	2071	12
T2	13197	18
T3	3524	16
T7	13369	13
T8	3945	969
T9	2006	7
T10	1411	12
T11	27495	113
T12	18102	196
T13	4146	6

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	582820
T1	2071	13
T2	13197	18
T3	3524	19
T7	13369	13
T8	3945	1897
T9	2006	7
T10	1411	13
T11	27495	171
T12	18102	201
T13	4146	8

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	219253
T1	2071	12
T2	13197	18
T3	3524	16
T7	13369	13
T8	3945	969
T9	2006	7
T10	1411	12
T11	27495	113
T12	18102	196
T13	4146	6

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	222072	0	0
GntImpliesValid_A	430217806	222072	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	222072	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3010818	0	0
ReadyAndValidImplyGrant_A	430217806	222072	0	0
ReqAndReadyImplyGrant_A	430217806	222072	0	0
ReqImpliesValid_A	430217806	629431	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	222072	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	222072
T1	2071	10
T2	13197	15
T3	3524	15
T7	13369	7
T8	3945	0
T9	2006	10
T10	1411	8
T11	27495	80
T12	18102	218
T13	4146	6
T14	0	123

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	222072
T1	2071	10
T2	13197	15
T3	3524	15
T7	13369	7
T8	3945	0
T9	2006	10
T10	1411	8
T11	27495	80
T12	18102	218
T13	4146	6
T14	0	123

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	222072
T1	2071	10
T2	13197	15
T3	3524	15
T7	13369	7
T8	3945	0
T9	2006	10
T10	1411	8
T11	27495	80
T12	18102	218
T13	4146	6
T14	0	123

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3010818
T1	2071	11
T2	13197	141
T3	3524	109
T7	13369	44
T8	3945	1
T9	2006	9
T10	1411	9
T11	27495	574
T12	18102	208
T13	4146	35

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	222072
T1	2071	10
T2	13197	15
T3	3524	15
T7	13369	7
T8	3945	0
T9	2006	10
T10	1411	8
T11	27495	80
T12	18102	218
T13	4146	6
T14	0	123

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	222072
T1	2071	10
T2	13197	15
T3	3524	15
T7	13369	7
T8	3945	0
T9	2006	10
T10	1411	8
T11	27495	80
T12	18102	218
T13	4146	6
T14	0	123

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	629431
T1	2071	10
T2	13197	27
T3	3524	23
T7	13369	7
T8	3945	0
T9	2006	12
T10	1411	8
T11	27495	155
T12	18102	229
T13	4146	6
T14	0	175

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	222072
T1	2071	10
T2	13197	15
T3	3524	15
T7	13369	7
T8	3945	0
T9	2006	10
T10	1411	8
T11	27495	80
T12	18102	218
T13	4146	6
T14	0	123

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	224083	0	0
GntImpliesValid_A	430217806	224083	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	224083	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3023400	0	0
ReadyAndValidImplyGrant_A	430217806	224083	0	0
ReqAndReadyImplyGrant_A	430217806	224083	0	0
ReqImpliesValid_A	430217806	633647	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	224083	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	224083
T1	2071	13
T2	13197	10
T3	3524	11
T7	13369	6
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	73
T12	18102	214
T13	4146	6
T14	0	122

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	224083
T1	2071	13
T2	13197	10
T3	3524	11
T7	13369	6
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	73
T12	18102	214
T13	4146	6
T14	0	122

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	224083
T1	2071	13
T2	13197	10
T3	3524	11
T7	13369	6
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	73
T12	18102	214
T13	4146	6
T14	0	122

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3023400
T1	2071	13
T2	13197	83
T3	3524	93
T7	13369	52
T8	3945	1
T9	2006	11
T10	1411	12
T11	27495	580
T12	18102	200
T13	4146	33

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	224083
T1	2071	13
T2	13197	10
T3	3524	11
T7	13369	6
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	73
T12	18102	214
T13	4146	6
T14	0	122

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	224083
T1	2071	13
T2	13197	10
T3	3524	11
T7	13369	6
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	73
T12	18102	214
T13	4146	6
T14	0	122

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	633647
T1	2071	14
T2	13197	14
T3	3524	11
T7	13369	13
T8	3945	0
T9	2006	16
T10	1411	13
T11	27495	88
T12	18102	229
T13	4146	6
T14	0	180

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	224083
T1	2071	13
T2	13197	10
T3	3524	11
T7	13369	6
T8	3945	0
T9	2006	13
T10	1411	12
T11	27495	73
T12	18102	214
T13	4146	6
T14	0	122

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T9 T10 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T10,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	213498	0	0
GntImpliesValid_A	430217806	213498	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	213498	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3020839	0	0
ReadyAndValidImplyGrant_A	430217806	213498	0	0
ReqAndReadyImplyGrant_A	430217806	213498	0	0
ReqImpliesValid_A	430217806	563836	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	213498	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	213498
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	13
T10	1411	13
T11	27495	96
T12	18102	223
T13	4146	7
T14	0	115

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	213498
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	13
T10	1411	13
T11	27495	96
T12	18102	223
T13	4146	7
T14	0	115

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	213498
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	13
T10	1411	13
T11	27495	96
T12	18102	223
T13	4146	7
T14	0	115

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3020839
T1	2071	12
T2	13197	69
T3	3524	63
T7	13369	87
T8	3945	1
T9	2006	12
T10	1411	13
T11	27495	731
T12	18102	215
T13	4146	41

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	213498
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	13
T10	1411	13
T11	27495	96
T12	18102	223
T13	4146	7
T14	0	115

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	213498
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	13
T10	1411	13
T11	27495	96
T12	18102	223
T13	4146	7
T14	0	115

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	563836
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	15
T10	1411	14
T11	27495	137
T12	18102	232
T13	4146	7
T14	0	146

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	213498
T1	2071	11
T2	13197	9
T3	3524	7
T7	13369	10
T8	3945	0
T9	2006	13
T10	1411	13
T11	27495	96
T12	18102	223
T13	4146	7
T14	0	115

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	210392	0	0
GntImpliesValid_A	430217806	210392	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	210392	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2984580	0	0
ReadyAndValidImplyGrant_A	430217806	210392	0	0
ReqAndReadyImplyGrant_A	430217806	210392	0	0
ReqImpliesValid_A	430217806	574458	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	210392	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	210392
T1	2071	11
T2	13197	10
T3	3524	11
T7	13369	16
T8	3945	0
T9	2006	17
T10	1411	6
T11	27495	92
T12	18102	245
T13	4146	9
T14	0	133

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	210392
T1	2071	11
T2	13197	10
T3	3524	11
T7	13369	16
T8	3945	0
T9	2006	17
T10	1411	6
T11	27495	92
T12	18102	245
T13	4146	9
T14	0	133

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	210392
T1	2071	11
T2	13197	10
T3	3524	11
T7	13369	16
T8	3945	0
T9	2006	17
T10	1411	6
T11	27495	92
T12	18102	245
T13	4146	9
T14	0	133

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2984580
T1	2071	12
T2	13197	72
T3	3524	97
T7	13369	106
T8	3945	1
T9	2006	18
T10	1411	6
T11	27495	760
T12	18102	233
T13	4146	89

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	210392
T1	2071	11
T2	13197	10
T3	3524	11
T7	13369	16
T8	3945	0
T9	2006	17
T10	1411	6
T11	27495	92
T12	18102	245
T13	4146	9
T14	0	133

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	210392
T1	2071	11
T2	13197	10
T3	3524	11
T7	13369	16
T8	3945	0
T9	2006	17
T10	1411	6
T11	27495	92
T12	18102	245
T13	4146	9
T14	0	133

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	574458
T1	2071	11
T2	13197	10
T3	3524	15
T7	13369	22
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	140
T12	18102	258
T13	4146	9
T14	0	167

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	210392
T1	2071	11
T2	13197	10
T3	3524	11
T7	13369	16
T8	3945	0
T9	2006	17
T10	1411	6
T11	27495	92
T12	18102	245
T13	4146	9
T14	0	133

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	219024	0	0
GntImpliesValid_A	430217806	219024	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	219024	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2985689	0	0
ReadyAndValidImplyGrant_A	430217806	219024	0	0
ReqAndReadyImplyGrant_A	430217806	219024	0	0
ReqImpliesValid_A	430217806	597290	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	219024	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	219024
T1	2071	15
T2	13197	11
T3	3524	7
T7	13369	15
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	105
T12	18102	195
T13	4146	6
T14	0	113

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	219024
T1	2071	15
T2	13197	11
T3	3524	7
T7	13369	15
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	105
T12	18102	195
T13	4146	6
T14	0	113

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	219024
T1	2071	15
T2	13197	11
T3	3524	7
T7	13369	15
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	105
T12	18102	195
T13	4146	6
T14	0	113

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2985689
T1	2071	15
T2	13197	85
T3	3524	46
T7	13369	140
T8	3945	1
T9	2006	18
T10	1411	8
T11	27495	822
T12	18102	189
T13	4146	41

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219024
T1	2071	15
T2	13197	11
T3	3524	7
T7	13369	15
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	105
T12	18102	195
T13	4146	6
T14	0	113

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	219024
T1	2071	15
T2	13197	11
T3	3524	7
T7	13369	15
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	105
T12	18102	195
T13	4146	6
T14	0	113

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	597290
T1	2071	16
T2	13197	11
T3	3524	7
T7	13369	20
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	173
T12	18102	202
T13	4146	14
T14	0	142

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	219024
T1	2071	15
T2	13197	11
T3	3524	7
T7	13369	15
T8	3945	0
T9	2006	17
T10	1411	7
T11	27495	105
T12	18102	195
T13	4146	6
T14	0	113

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	204598	0	0
GntImpliesValid_A	430217806	204598	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	204598	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2962868	0	0
ReadyAndValidImplyGrant_A	430217806	204598	0	0
ReqAndReadyImplyGrant_A	430217806	204598	0	0
ReqImpliesValid_A	430217806	556534	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	204598	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	204598
T1	2071	17
T2	13197	7
T3	3524	11
T7	13369	22
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	91
T12	18102	224
T13	4146	8
T14	0	117

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	204598
T1	2071	17
T2	13197	7
T3	3524	11
T7	13369	22
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	91
T12	18102	224
T13	4146	8
T14	0	117

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	204598
T1	2071	17
T2	13197	7
T3	3524	11
T7	13369	22
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	91
T12	18102	224
T13	4146	8
T14	0	117

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2962868
T1	2071	16
T2	13197	55
T3	3524	88
T7	13369	143
T8	3945	1
T9	2006	10
T10	1411	10
T11	27495	625
T12	18102	208
T13	4146	47

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	204598
T1	2071	17
T2	13197	7
T3	3524	11
T7	13369	22
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	91
T12	18102	224
T13	4146	8
T14	0	117

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	204598
T1	2071	17
T2	13197	7
T3	3524	11
T7	13369	22
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	91
T12	18102	224
T13	4146	8
T14	0	117

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	556534
T1	2071	19
T2	13197	7
T3	3524	11
T7	13369	46
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	137
T12	18102	241
T13	4146	8
T14	0	135

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	204598
T1	2071	17
T2	13197	7
T3	3524	11
T7	13369	22
T8	3945	0
T9	2006	9
T10	1411	9
T11	27495	91
T12	18102	224
T13	4146	8
T14	0	117

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T11

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	211569	0	0
GntImpliesValid_A	430217806	211569	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	211569	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2932144	0	0
ReadyAndValidImplyGrant_A	430217806	211569	0	0
ReqAndReadyImplyGrant_A	430217806	211569	0	0
ReqImpliesValid_A	430217806	541365	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	211569	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	211569
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	11
T8	3945	0
T9	2006	15
T10	1411	10
T11	27495	86
T12	18102	243
T13	4146	10
T14	0	131

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	211569
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	11
T8	3945	0
T9	2006	15
T10	1411	10
T11	27495	86
T12	18102	243
T13	4146	10
T14	0	131

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	211569
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	11
T8	3945	0
T9	2006	15
T10	1411	10
T11	27495	86
T12	18102	243
T13	4146	10
T14	0	131

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2932144
T1	2071	14
T2	13197	106
T3	3524	65
T7	13369	61
T8	3945	1
T9	2006	14
T10	1411	11
T11	27495	636
T12	18102	232
T13	4146	94

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	211569
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	11
T8	3945	0
T9	2006	15
T10	1411	10
T11	27495	86
T12	18102	243
T13	4146	10
T14	0	131

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	211569
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	11
T8	3945	0
T9	2006	15
T10	1411	10
T11	27495	86
T12	18102	243
T13	4146	10
T14	0	131

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	541365
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	31
T8	3945	0
T9	2006	17
T10	1411	10
T11	27495	106
T12	18102	255
T13	4146	10
T14	0	158

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	211569
T1	2071	13
T2	13197	8
T3	3524	5
T7	13369	11
T8	3945	0
T9	2006	15
T10	1411	10
T11	27495	86
T12	18102	243
T13	4146	10
T14	0	131

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	230893	0	0
GntImpliesValid_A	430217806	230893	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	230893	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3082136	0	0
ReadyAndValidImplyGrant_A	430217806	230893	0	0
ReqAndReadyImplyGrant_A	430217806	230893	0	0
ReqImpliesValid_A	430217806	549373	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	230893	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	230893
T1	2071	24
T2	13197	13
T3	3524	15
T7	13369	11
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	92
T12	18102	192
T13	4146	15
T14	0	189

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	230893
T1	2071	24
T2	13197	13
T3	3524	15
T7	13369	11
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	92
T12	18102	192
T13	4146	15
T14	0	189

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	230893
T1	2071	24
T2	13197	13
T3	3524	15
T7	13369	11
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	92
T12	18102	192
T13	4146	15
T14	0	189

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3082136
T1	2071	22
T2	13197	96
T3	3524	119
T7	13369	97
T8	3945	1
T9	2006	9
T10	1411	9
T11	27495	642
T12	18102	185
T13	4146	102

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	230893
T1	2071	24
T2	13197	13
T3	3524	15
T7	13369	11
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	92
T12	18102	192
T13	4146	15
T14	0	189

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	230893
T1	2071	24
T2	13197	13
T3	3524	15
T7	13369	11
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	92
T12	18102	192
T13	4146	15
T14	0	189

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	549373
T1	2071	27
T2	13197	25
T3	3524	24
T7	13369	15
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	114
T12	18102	200
T13	4146	23
T14	0	240

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	230893
T1	2071	24
T2	13197	13
T3	3524	15
T7	13369	11
T8	3945	0
T9	2006	8
T10	1411	8
T11	27495	92
T12	18102	192
T13	4146	15
T14	0	189

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	211723	0	0
GntImpliesValid_A	430217806	211723	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	211723	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2959589	0	0
ReadyAndValidImplyGrant_A	430217806	211723	0	0
ReqAndReadyImplyGrant_A	430217806	211723	0	0
ReqImpliesValid_A	430217806	596992	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	211723	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	211723
T1	2071	7
T2	13197	16
T3	3524	9
T7	13369	10
T8	3945	0
T9	2006	11
T10	1411	5
T11	27495	86
T12	18102	202
T13	4146	7
T14	0	116

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	211723
T1	2071	7
T2	13197	16
T3	3524	9
T7	13369	10
T8	3945	0
T9	2006	11
T10	1411	5
T11	27495	86
T12	18102	202
T13	4146	7
T14	0	116

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	211723
T1	2071	7
T2	13197	16
T3	3524	9
T7	13369	10
T8	3945	0
T9	2006	11
T10	1411	5
T11	27495	86
T12	18102	202
T13	4146	7
T14	0	116

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2959589
T1	2071	8
T2	13197	165
T3	3524	81
T7	13369	58
T8	3945	1
T9	2006	11
T10	1411	6
T11	27495	620
T12	18102	194
T13	4146	29

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	211723
T1	2071	7
T2	13197	16
T3	3524	9
T7	13369	10
T8	3945	0
T9	2006	11
T10	1411	5
T11	27495	86
T12	18102	202
T13	4146	7
T14	0	116

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	211723
T1	2071	7
T2	13197	16
T3	3524	9
T7	13369	10
T8	3945	0
T9	2006	11
T10	1411	5
T11	27495	86
T12	18102	202
T13	4146	7
T14	0	116

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	596992
T1	2071	7
T2	13197	23
T3	3524	13
T7	13369	10
T8	3945	0
T9	2006	12
T10	1411	5
T11	27495	134
T12	18102	211
T13	4146	7
T14	0	136

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	211723
T1	2071	7
T2	13197	16
T3	3524	9
T7	13369	10
T8	3945	0
T9	2006	11
T10	1411	5
T11	27495	86
T12	18102	202
T13	4146	7
T14	0	116

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	216601	0	0
GntImpliesValid_A	430217806	216601	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	216601	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2983361	0	0
ReadyAndValidImplyGrant_A	430217806	216601	0	0
ReqAndReadyImplyGrant_A	430217806	216601	0	0
ReqImpliesValid_A	430217806	584129	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	216601	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	216601
T1	2071	7
T2	13197	19
T3	3524	16
T7	13369	19
T8	3945	0
T9	2006	16
T10	1411	8
T11	27495	96
T12	18102	190
T13	4146	5
T14	0	130

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	216601
T1	2071	7
T2	13197	19
T3	3524	16
T7	13369	19
T8	3945	0
T9	2006	16
T10	1411	8
T11	27495	96
T12	18102	190
T13	4146	5
T14	0	130

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	216601
T1	2071	7
T2	13197	19
T3	3524	16
T7	13369	19
T8	3945	0
T9	2006	16
T10	1411	8
T11	27495	96
T12	18102	190
T13	4146	5
T14	0	130

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2983361
T1	2071	8
T2	13197	159
T3	3524	110
T7	13369	169
T8	3945	1
T9	2006	17
T10	1411	8
T11	27495	705
T12	18102	175
T13	4146	44

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	216601
T1	2071	7
T2	13197	19
T3	3524	16
T7	13369	19
T8	3945	0
T9	2006	16
T10	1411	8
T11	27495	96
T12	18102	190
T13	4146	5
T14	0	130

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	216601
T1	2071	7
T2	13197	19
T3	3524	16
T7	13369	19
T8	3945	0
T9	2006	16
T10	1411	8
T11	27495	96
T12	18102	190
T13	4146	5
T14	0	130

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	584129
T1	2071	7
T2	13197	19
T3	3524	36
T7	13369	45
T8	3945	0
T9	2006	16
T10	1411	9
T11	27495	167
T12	18102	206
T13	4146	5
T14	0	156

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	216601
T1	2071	7
T2	13197	19
T3	3524	16
T7	13369	19
T8	3945	0
T9	2006	16
T10	1411	8
T11	27495	96
T12	18102	190
T13	4146	5
T14	0	130

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T11

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	225157	0	0
GntImpliesValid_A	430217806	225157	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	225157	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	3023890	0	0
ReadyAndValidImplyGrant_A	430217806	225157	0	0
ReqAndReadyImplyGrant_A	430217806	225157	0	0
ReqImpliesValid_A	430217806	643725	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	225157	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	225157
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	12
T8	3945	0
T9	2006	19
T10	1411	7
T11	27495	103
T12	18102	208
T13	4146	9
T14	0	79

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	225157
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	12
T8	3945	0
T9	2006	19
T10	1411	7
T11	27495	103
T12	18102	208
T13	4146	9
T14	0	79

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	225157
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	12
T8	3945	0
T9	2006	19
T10	1411	7
T11	27495	103
T12	18102	208
T13	4146	9
T14	0	79

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	3023890
T1	2071	21
T2	13197	77
T3	3524	85
T7	13369	93
T8	3945	1
T9	2006	18
T10	1411	8
T11	27495	795
T12	18102	198
T13	4146	71

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	225157
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	12
T8	3945	0
T9	2006	19
T10	1411	7
T11	27495	103
T12	18102	208
T13	4146	9
T14	0	79

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	225157
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	12
T8	3945	0
T9	2006	19
T10	1411	7
T11	27495	103
T12	18102	208
T13	4146	9
T14	0	79

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	643725
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	30
T8	3945	0
T9	2006	21
T10	1411	7
T11	27495	146
T12	18102	219
T13	4146	19
T14	0	82

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	225157
T1	2071	20
T2	13197	10
T3	3524	8
T7	13369	12
T8	3945	0
T9	2006	19
T10	1411	7
T11	27495	103
T12	18102	208
T13	4146	9
T14	0	79

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T12

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	217152	0	0
GntImpliesValid_A	430217806	217152	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	217152	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2943519	0	0
ReadyAndValidImplyGrant_A	430217806	217152	0	0
ReqAndReadyImplyGrant_A	430217806	217152	0	0
ReqImpliesValid_A	430217806	540941	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	217152	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	217152
T1	2071	12
T2	13197	12
T3	3524	8
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	116
T12	18102	207
T13	4146	9
T14	0	119

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	217152
T1	2071	12
T2	13197	12
T3	3524	8
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	116
T12	18102	207
T13	4146	9
T14	0	119

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	217152
T1	2071	12
T2	13197	12
T3	3524	8
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	116
T12	18102	207
T13	4146	9
T14	0	119

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2943519
T1	2071	13
T2	13197	81
T3	3524	45
T7	13369	108
T8	3945	1
T9	2006	20
T10	1411	5
T11	27495	833
T12	18102	200
T13	4146	62

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	217152
T1	2071	12
T2	13197	12
T3	3524	8
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	116
T12	18102	207
T13	4146	9
T14	0	119

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	217152
T1	2071	12
T2	13197	12
T3	3524	8
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	116
T12	18102	207
T13	4146	9
T14	0	119

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	540941
T1	2071	12
T2	13197	12
T3	3524	9
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	182
T12	18102	215
T13	4146	9
T14	0	173

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	217152
T1	2071	12
T2	13197	12
T3	3524	8
T7	13369	13
T8	3945	0
T9	2006	19
T10	1411	4
T11	27495	116
T12	18102	207
T13	4146	9
T14	0	119

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	217948	0	0
GntImpliesValid_A	430217806	217948	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	217948	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	2940267	0	0
ReadyAndValidImplyGrant_A	430217806	217948	0	0
ReqAndReadyImplyGrant_A	430217806	217948	0	0
ReqImpliesValid_A	430217806	596278	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	0	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	217948	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	217948
T1	2071	9
T2	13197	12
T3	3524	8
T7	13369	17
T8	3945	0
T9	2006	21
T10	1411	10
T11	27495	89
T12	18102	200
T13	4146	16
T14	0	129

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	217948
T1	2071	9
T2	13197	12
T3	3524	8
T7	13369	17
T8	3945	0
T9	2006	21
T10	1411	10
T11	27495	89
T12	18102	200
T13	4146	16
T14	0	129

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	217948
T1	2071	9
T2	13197	12
T3	3524	8
T7	13369	17
T8	3945	0
T9	2006	21
T10	1411	10
T11	27495	89
T12	18102	200
T13	4146	16
T14	0	129

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	2940267
T1	2071	9
T2	13197	85
T3	3524	51
T7	13369	134
T8	3945	1
T9	2006	21
T10	1411	11
T11	27495	720
T12	18102	192
T13	4146	89

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	217948
T1	2071	9
T2	13197	12
T3	3524	8
T7	13369	17
T8	3945	0
T9	2006	21
T10	1411	10
T11	27495	89
T12	18102	200
T13	4146	16
T14	0	129

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	217948
T1	2071	9
T2	13197	12
T3	3524	8
T7	13369	17
T8	3945	0
T9	2006	21
T10	1411	10
T11	27495	89
T12	18102	200
T13	4146	16
T14	0	129

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	596278
T1	2071	10
T2	13197	14
T3	3524	8
T7	13369	24
T8	3945	0
T9	2006	22
T10	1411	10
T11	27495	111
T12	18102	209
T13	4146	31
T14	0	201

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	217948
T1	2071	9
T2	13197	12
T3	3524	8
T7	13369	17
T8	3945	0
T9	2006	21
T10	1411	10
T11	27495	89
T12	18102	200
T13	4146	16
T14	0	129

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	877825	0	0
GntImpliesValid_A	430217806	877825	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	877825	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	11319148	0	0
ReadyAndValidImplyGrant_A	430217806	877825	0	0
ReqAndReadyImplyGrant_A	430217806	877825	0	0
ReqImpliesValid_A	430217806	2284159	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	18140	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	877825	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	877825
T1	2071	46
T2	13197	39
T3	3524	45
T7	13369	52
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	406
T12	18102	829
T13	4146	30

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	877825
T1	2071	46
T2	13197	39
T3	3524	45
T7	13369	52
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	406
T12	18102	829
T13	4146	30

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	877825
T1	2071	46
T2	13197	39
T3	3524	45
T7	13369	52
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	406
T12	18102	829
T13	4146	30

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	11319148
T1	2071	1
T2	13197	254
T3	3524	281
T7	13369	317
T8	3945	1
T9	2006	1
T10	1411	1
T11	27495	2564
T12	18102	1
T13	4146	139

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	877825
T1	2071	46
T2	13197	39
T3	3524	45
T7	13369	52
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	406
T12	18102	829
T13	4146	30

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	877825
T1	2071	46
T2	13197	39
T3	3524	45
T7	13369	52
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	406
T12	18102	829
T13	4146	30

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	2284159
T1	2071	46
T2	13197	56
T3	3524	82
T7	13369	76
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	769
T12	18102	829
T13	4146	52

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	430217806	18140	900
T12	18102	14	1
T13	4146	0	1
T14	64695	1	1
T15	13704	19	1
T16	63818	2	1
T17	130671	0	1
T18	0	13	0
T20	0	6	0
T21	0	1	0
T22	0	1	0
T23	0	5	0
T24	0	17	0
T25	179815	0	1
T26	2685	0	1
T27	2929	0	1
T28	12167	0	1

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	877825
T1	2071	46
T2	13197	39
T3	3524	45
T7	13369	52
T8	3945	125
T9	2006	31
T10	1411	55
T11	27495	406
T12	18102	829
T13	4146	30

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430217806	430092490	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430217806	879581	0	0
GntImpliesValid_A	430217806	879581	0	0
GrantKnown_A	430217806	430092490	0	0
IdxKnown_A	430217806	430092490	0	0
IndexIsCorrect_A	430217806	879581	0	0
LockArbDecision_A	430217806	0	0	0
NoReadyValidNoGrant_A	430217806	361600352	0	0
ReadyAndValidImplyGrant_A	430217806	879581	0	0
ReqAndReadyImplyGrant_A	430217806	879581	0	0
ReqImpliesValid_A	430217806	13194397	0	0
ReqStaysHighUntilGranted0_M	430217806	0	0	0
RoundRobin_A	430217806	26394	0	900
ValidKnown_A	430217806	430092490	0	0
gen_data_port_assertion.DataFlow_A	430217806	879581	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	430217806	879581
T1	2071	35
T2	13197	44
T3	3524	36
T7	13369	51
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	378
T12	18102	790
T13	4146	24

GntImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	879581
T1	2071	35
T2	13197	44
T3	3524	36
T7	13369	51
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	378
T12	18102	790
T13	4146	24

GrantKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IdxKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	430217806	879581
T1	2071	35
T2	13197	44
T3	3524	36
T7	13369	51
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	378
T12	18102	790
T13	4146	24

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	430217806	361600352
T1	2071	1
T2	13197	11464
T3	3524	2904
T7	13369	11631
T8	3945	1
T9	2006	1
T10	1411	1
T11	27495	22405
T12	18102	1
T13	4146	3571

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	879581
T1	2071	35
T2	13197	44
T3	3524	36
T7	13369	51
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	378
T12	18102	790
T13	4146	24

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	430217806	879581
T1	2071	35
T2	13197	44
T3	3524	36
T7	13369	51
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	378
T12	18102	790
T13	4146	24

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	430217806	13194397
T1	2071	35
T2	13197	406
T3	3524	322
T7	13369	464
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	2937
T12	18102	790
T13	4146	168

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430217806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	430217806	26394	900
T12	18102	15	1
T13	4146	0	1
T14	64695	0	1
T15	13704	10	1
T16	63818	0	1
T17	130671	1	1
T18	0	7	0
T19	0	1	0
T20	0	2	0
T21	0	2	0
T22	0	2	0
T23	0	2	0
T24	0	15	0
T25	179815	0	1
T26	2685	0	1
T27	2929	0	1
T28	12167	0	1

ValidKnown_A

Name	Attempts	Real Successes
Total	430217806	430092490
T1	2071	2020
T2	13197	13140
T3	3524	3502
T7	13369	13253
T8	3945	3905
T9	2006	1961
T10	1411	1405
T11	27495	27482
T12	18102	18052
T13	4146	4090

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	430217806	879581
T1	2071	35
T2	13197	44
T3	3524	36
T7	13369	51
T8	3945	137
T9	2006	51
T10	1411	49
T11	27495	378
T12	18102	790
T13	4146	24

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children