Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1814297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

285637

1

T1

238

T2

9

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	709526	1			T1	534		T2	32		T3	58
values[0x0]	681145	1			T1	573		T2	6		T3	11
values[0x1]	709263	1			T1	589		T2	32		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1406796	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

693138

1

T1

537

T2

36

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8928	1			T1	10		T17	5		T11	2
valid_sources[0x01]	7930	1			T1	19		T17	11		T13	6
valid_sources[0x02]	9790	1			T2	1		T17	10		T13	7
valid_sources[0x03]	8564	1			T1	4		T3	1		T17	5
valid_sources[0x04]	8103	1			T1	62		T17	11		T13	7
valid_sources[0x05]	8028	1			T1	1		T17	10		T13	7
valid_sources[0x06]	7583	1			T3	1		T17	4		T11	3
valid_sources[0x07]	7755	1			T1	1		T17	20		T13	5
valid_sources[0x08]	8151	1			T1	6		T17	12		T11	1
valid_sources[0x09]	8626	1			T17	3		T13	7		T19	1
valid_sources[0x0a]	9452	1			T17	9		T13	7		T19	1
valid_sources[0x0b]	9295	1			T1	30		T17	6		T11	1
valid_sources[0x0c]	9069	1			T3	2		T17	9		T13	6
valid_sources[0x0d]	8997	1			T3	1		T17	8		T13	7
valid_sources[0x0e]	7641	1			T1	31		T2	1		T17	10
valid_sources[0x0f]	7810	1			T3	2		T17	7		T13	6
valid_sources[0x10]	8042	1			T1	5		T3	1		T17	6
valid_sources[0x11]	10099	1			T2	1		T17	4		T13	7
valid_sources[0x12]	7255	1			T1	4		T2	1		T17	6
valid_sources[0x13]	6881	1			T1	5		T17	12		T12	9
valid_sources[0x14]	7626	1			T1	13		T17	2		T13	7
valid_sources[0x15]	8438	1			T17	12		T13	7		T20	1
valid_sources[0x16]	8042	1			T1	1		T3	1		T17	6
valid_sources[0x17]	8606	1			T17	5		T11	3		T12	19
valid_sources[0x18]	8252	1			T17	2		T11	2		T13	7
valid_sources[0x19]	8374	1			T1	2		T3	1		T17	6
valid_sources[0x1a]	8124	1			T17	8		T11	1		T13	8
valid_sources[0x1b]	8685	1			T2	1		T3	2		T17	4
valid_sources[0x1c]	7921	1			T3	3		T17	11		T13	7
valid_sources[0x1d]	7728	1			T3	1		T17	8		T11	1
valid_sources[0x1e]	8413	1			T1	14		T17	11		T11	1
valid_sources[0x1f]	8549	1			T1	28		T17	6		T13	5
valid_sources[0x20]	8258	1			T2	1		T17	13		T11	1
valid_sources[0x21]	8794	1			T1	4		T2	1		T17	22
valid_sources[0x22]	7711	1			T1	1		T17	6		T13	5
valid_sources[0x23]	8156	1			T1	45		T2	1		T17	12
valid_sources[0x24]	9023	1			T17	10		T13	6		T21	7
valid_sources[0x25]	8561	1			T17	10		T13	5		T21	11
valid_sources[0x26]	10992	1			T2	1		T17	17		T12	18
valid_sources[0x27]	6988	1			T2	1		T17	2		T13	6
valid_sources[0x28]	7623	1			T17	13		T13	8		T18	1
valid_sources[0x29]	8861	1			T1	16		T17	8		T11	1
valid_sources[0x2a]	8602	1			T17	4		T11	2		T13	7
valid_sources[0x2b]	7518	1			T1	5		T2	1		T17	3
valid_sources[0x2c]	7583	1			T17	14		T11	2		T13	6
valid_sources[0x2d]	7607	1			T17	11		T13	6		T19	3
valid_sources[0x2e]	8659	1			T17	11		T11	1		T13	7
valid_sources[0x2f]	8228	1			T1	32		T17	30		T13	7
valid_sources[0x30]	7746	1			T17	4		T13	6		T20	1
valid_sources[0x31]	8406	1			T1	1		T3	1		T17	5
valid_sources[0x32]	7829	1			T1	15		T17	8		T13	8
valid_sources[0x33]	7559	1			T17	7		T11	2		T13	7
valid_sources[0x34]	9124	1			T17	11		T11	1		T13	6
valid_sources[0x35]	7756	1			T17	10		T13	7		T18	1
valid_sources[0x36]	7705	1			T3	2		T17	10		T11	1
valid_sources[0x37]	8252	1			T1	31		T3	1		T17	12
valid_sources[0x38]	7891	1			T3	2		T17	2		T13	8
valid_sources[0x39]	8457	1			T1	6		T17	13		T13	7
valid_sources[0x3a]	8227	1			T17	8		T11	2		T13	7
valid_sources[0x3b]	9271	1			T3	1		T17	5		T11	1
valid_sources[0x3c]	8159	1			T3	1		T17	9		T13	7
valid_sources[0x3d]	8127	1			T17	5		T11	1		T13	8
valid_sources[0x3e]	7961	1			T1	7		T17	8		T13	7
valid_sources[0x3f]	9535	1			T17	6		T13	7		T21	11
valid_sources[0x40]	7841	1			T17	19		T13	7		T19	1
valid_sources[0x41]	7328	1			T2	1		T3	1		T17	1
valid_sources[0x42]	8066	1			T1	14		T2	1		T3	1
valid_sources[0x43]	10260	1			T17	6		T13	7		T21	8
valid_sources[0x44]	7939	1			T1	4		T3	1		T17	5
valid_sources[0x45]	7797	1			T1	11		T3	1		T17	6
valid_sources[0x46]	7884	1			T2	1		T17	13		T11	1
valid_sources[0x47]	8048	1			T17	7		T13	6		T19	2
valid_sources[0x48]	7955	1			T2	1		T3	1		T17	10
valid_sources[0x49]	7280	1			T1	7		T17	7		T13	6
valid_sources[0x4a]	7299	1			T1	1		T17	12		T13	7
valid_sources[0x4b]	7995	1			T1	18		T2	1		T17	10
valid_sources[0x4c]	7183	1			T1	5		T3	1		T17	16
valid_sources[0x4d]	7416	1			T1	7		T17	9		T13	5
valid_sources[0x4e]	7767	1			T17	3		T13	6		T21	6
valid_sources[0x4f]	8947	1			T1	7		T17	3		T11	1
valid_sources[0x50]	7041	1			T17	7		T11	1		T13	6
valid_sources[0x51]	7270	1			T17	3		T11	1		T13	7
valid_sources[0x52]	7689	1			T2	2		T17	17		T12	12
valid_sources[0x53]	7632	1			T1	36		T2	1		T3	1
valid_sources[0x54]	7790	1			T17	7		T13	7		T20	1
valid_sources[0x55]	8417	1			T17	8		T13	7		T21	6
valid_sources[0x56]	8335	1			T17	3		T11	1		T13	7
valid_sources[0x57]	8590	1			T1	13		T3	2		T17	5
valid_sources[0x58]	9042	1			T1	1		T17	17		T13	8
valid_sources[0x59]	8020	1			T1	10		T3	1		T17	7
valid_sources[0x5a]	7972	1			T3	1		T17	24		T13	7
valid_sources[0x5b]	8381	1			T3	1		T17	11		T13	6
valid_sources[0x5c]	9253	1			T3	2		T17	13		T11	1
valid_sources[0x5d]	7972	1			T17	17		T11	4		T13	6
valid_sources[0x5e]	7872	1			T17	17		T13	6		T19	1
valid_sources[0x5f]	7912	1			T1	25		T17	11		T13	7
valid_sources[0x60]	7945	1			T17	9		T13	7		T21	10
valid_sources[0x61]	7322	1			T1	20		T3	3		T17	7
valid_sources[0x62]	7898	1			T1	30		T17	12		T13	6
valid_sources[0x63]	8495	1			T2	1		T3	2		T17	9
valid_sources[0x64]	8343	1			T1	18		T3	1		T17	14
valid_sources[0x65]	8043	1			T1	8		T17	6		T13	6
valid_sources[0x66]	8358	1			T17	12		T13	7		T19	1
valid_sources[0x67]	7954	1			T1	1		T3	1		T17	12
valid_sources[0x68]	8337	1			T3	1		T17	16		T13	6
valid_sources[0x69]	8875	1			T1	12		T3	1		T17	14
valid_sources[0x6a]	8262	1			T17	3		T13	6		T21	5
valid_sources[0x6b]	7867	1			T1	6		T2	1		T3	2
valid_sources[0x6c]	8952	1			T17	9		T11	5		T13	7
valid_sources[0x6d]	8257	1			T17	4		T13	7		T20	2
valid_sources[0x6e]	8248	1			T17	2		T13	7		T21	9
valid_sources[0x6f]	9218	1			T1	17		T3	1		T17	12
valid_sources[0x70]	8284	1			T1	19		T17	12		T13	8
valid_sources[0x71]	8151	1			T17	14		T11	1		T13	5
valid_sources[0x72]	8587	1			T17	1		T13	7		T19	1
valid_sources[0x73]	7471	1			T3	2		T17	7		T13	7
valid_sources[0x74]	8417	1			T1	20		T17	12		T12	6
valid_sources[0x75]	8805	1			T1	22		T2	1		T3	2
valid_sources[0x76]	8423	1			T17	6		T11	1		T13	6
valid_sources[0x77]	8007	1			T1	4		T2	1		T17	8
valid_sources[0x78]	8044	1			T1	18		T3	1		T17	3
valid_sources[0x79]	7657	1			T17	14		T11	1		T13	5
valid_sources[0x7a]	7460	1			T1	32		T2	1		T17	13
valid_sources[0x7b]	8832	1			T17	7		T13	7		T20	1
valid_sources[0x7c]	8335	1			T1	3		T17	12		T11	1
valid_sources[0x7d]	8564	1			T1	15		T2	1		T3	3
valid_sources[0x7e]	7858	1			T17	4		T13	5		T20	1
valid_sources[0x7f]	8444	1			T1	10		T17	12		T12	12
valid_sources[0x80]	7551	1			T1	19		T17	7		T13	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30043

1

T1

22

T2

3

T3

4

values[0x0]

all_enables

biggest_size

225744

1

T1

194

T2

3

T3

7

values[0x1]

all_enables

biggest_size

29850

1

T1

22

T2

3

T3

5