SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
98.94 | 100.00 | 94.71 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
---|---|---|---|---|---|---|---|
tlul_socket_1n | 98.42 | 100.00 | 93.68 | 100.00 | 100.00 | ||
tlul_rsp_intg_gen | 100.00 | 100.00 | 100.00 | ||||
tlul_fifo_sync | 100.00 | 100.00 | 100.00 | ||||
tlul_assert | 100.00 | 100.00 | 100.00 | 100.00 | |||
prim_fifo_sync | 100.00 | 100.00 | 100.00 | ||||
tlul_err_resp | 100.00 | 100.00 | 100.00 | 100.00 | |||
prim_secded_inv_39_32_enc | 100.00 | 100.00 | |||||
prim_secded_inv_64_57_enc | 100.00 | 100.00 | |||||
xbar_peri | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
tlul_data_integ_enc | |||||||
tb |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |