Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	333824359	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333824359	0	0
T1	49076776	871386	0	0
T2	2255680	43020	0	0
T3	3640504	69875	0	0
T11	265272	4977	0	0
T12	510608	7226	0	0
T13	9067464	1237130	0	0
T14	0	101911	0	0
T17	266616	11163	0	0
T18	734944	19224	0	0
T19	7037408	169798	0	0
T20	12107704	299092	0	0
T21	0	23116	0	0
T22	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49076776	49075712	0	0
T2	2255680	2252656	0	0
T3	3640504	3636640	0	0
T11	265272	262080	0	0
T12	510608	510104	0	0
T13	9067464	9067072	0	0
T17	266616	263312	0	0
T18	734944	733320	0	0
T19	7037408	7032816	0	0
T20	12107704	12105128	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49076776	49075712	0	0
T2	2255680	2252656	0	0
T3	3640504	3636640	0	0
T11	265272	262080	0	0
T12	510608	510104	0	0
T13	9067464	9067072	0	0
T17	266616	263312	0	0
T18	734944	733320	0	0
T19	7037408	7032816	0	0
T20	12107704	12105128	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49076776	49075712	0	0
T2	2255680	2252656	0	0
T3	3640504	3636640	0	0
T11	265272	262080	0	0
T12	510608	510104	0	0
T13	9067464	9067072	0	0
T17	266616	263312	0	0
T18	734944	733320	0	0
T19	7037408	7032816	0	0
T20	12107704	12105128	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	119241921	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	119241921	0	0
T1	876371	853818	0	0
T2	40280	19468	0	0
T3	65009	31240	0	0
T11	4737	2202	0	0
T12	9118	1893	0	0
T13	161919	7701	0	0
T17	4761	4328	0	0
T18	13124	8041	0	0
T19	125668	78553	0	0
T20	216209	128309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	88297725	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	88297725	0	0
T1	876371	5026	0	0
T2	40280	5514	0	0
T3	65009	9190	0	0
T11	4737	817	0	0
T12	9118	1720	0	0
T13	161919	610864	0	0
T17	4761	2279	0	0
T18	13124	3706	0	0
T19	125668	29635	0	0
T20	216209	58013	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1429122	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1429122	0	0
T1	876371	241	0	0
T2	40280	416	0	0
T3	65009	942	0	0
T11	4737	24	0	0
T12	9118	55	0	0
T13	161919	0	0	0
T14	0	5139	0	0
T17	4761	83	0	0
T18	13124	194	0	0
T19	125668	2208	0	0
T20	216209	4110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3963330	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3963330	0	0
T1	876371	279	0	0
T2	40280	170	0	0
T3	65009	391	0	0
T11	4737	24	0	0
T12	9118	36	0	0
T13	161919	0	0	0
T14	0	2208	0	0
T17	4761	83	0	0
T18	13124	197	0	0
T19	125668	2677	0	0
T20	216209	4718	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1437930	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1437930	0	0
T1	876371	290	0	0
T2	40280	369	0	0
T3	65009	743	0	0
T11	4737	55	0	0
T12	9118	30	0	0
T13	161919	970	0	0
T17	4761	81	0	0
T18	13124	110	0	0
T19	125668	1936	0	0
T20	216209	3085	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3539836	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3539836	0	0
T1	876371	71	0	0
T2	40280	188	0	0
T3	65009	354	0	0
T11	4737	35	0	0
T12	9118	35	0	0
T13	161919	78832	0	0
T17	4761	81	0	0
T18	13124	130	0	0
T19	125668	1134	0	0
T20	216209	2552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1452331	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1452331	0	0
T1	876371	274	0	0
T2	40280	461	0	0
T3	65009	686	0	0
T11	4737	40	0	0
T12	9118	114	0	0
T13	161919	2464	0	0
T17	4761	94	0	0
T18	13124	169	0	0
T19	125668	120	0	0
T20	216209	3180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3467650	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3467650	0	0
T1	876371	335	0	0
T2	40280	230	0	0
T3	65009	324	0	0
T11	4737	21	0	0
T12	9118	59	0	0
T13	161919	189100	0	0
T17	4761	94	0	0
T18	13124	157	0	0
T19	125668	1	0	0
T20	216209	3174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1440286	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1440286	0	0
T1	876371	280	0	0
T2	40280	456	0	0
T3	65009	680	0	0
T11	4737	28	0	0
T12	9118	95	0	0
T13	161919	0	0	0
T14	0	4241	0	0
T17	4761	92	0	0
T18	13124	164	0	0
T19	125668	273	0	0
T20	216209	1110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2946262	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2946262	0	0
T1	876371	488	0	0
T2	40280	176	0	0
T3	65009	308	0	0
T11	4737	32	0	0
T12	9118	68	0	0
T13	161919	0	0	0
T14	0	2476	0	0
T17	4761	92	0	0
T18	13124	131	0	0
T19	125668	380	0	0
T20	216209	1108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1423091	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1423091	0	0
T1	876371	261	0	0
T2	40280	429	0	0
T3	65009	858	0	0
T11	4737	68	0	0
T12	9118	47	0	0
T13	161919	0	0	0
T17	4761	76	0	0
T18	13124	160	0	0
T19	125668	1625	0	0
T20	216209	1996	0	0
T21	0	2370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3259694	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3259694	0	0
T1	876371	60	0	0
T2	40280	179	0	0
T3	65009	467	0	0
T11	4737	45	0	0
T12	9118	109	0	0
T13	161919	0	0	0
T17	4761	76	0	0
T18	13124	139	0	0
T19	125668	860	0	0
T20	216209	1665	0	0
T21	0	2476	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1412918	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1412918	0	0
T1	876371	265	0	0
T2	40280	448	0	0
T3	65009	834	0	0
T11	4737	54	0	0
T12	9118	91	0	0
T13	161919	0	0	0
T14	0	5670	0	0
T17	4761	81	0	0
T18	13124	124	0	0
T19	125668	1077	0	0
T20	216209	2816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2903173	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2903173	0	0
T1	876371	68	0	0
T2	40280	191	0	0
T3	65009	340	0	0
T11	4737	27	0	0
T12	9118	80	0	0
T13	161919	0	0	0
T14	0	2259	0	0
T17	4761	81	0	0
T18	13124	121	0	0
T19	125668	1306	0	0
T20	216209	2823	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1462412	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1462412	0	0
T1	876371	352	0	0
T2	40280	413	0	0
T3	65009	839	0	0
T11	4737	52	0	0
T12	9118	35	0	0
T13	161919	0	0	0
T14	0	5153	0	0
T17	4761	83	0	0
T18	13124	147	0	0
T19	125668	842	0	0
T20	216209	2638	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3265697	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3265697	0	0
T1	876371	73	0	0
T2	40280	236	0	0
T3	65009	388	0	0
T11	4737	29	0	0
T12	9118	51	0	0
T13	161919	0	0	0
T14	0	2219	0	0
T17	4761	83	0	0
T18	13124	128	0	0
T19	125668	1819	0	0
T20	216209	1474	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1426651	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1426651	0	0
T1	876371	308	0	0
T2	40280	516	0	0
T3	65009	979	0	0
T11	4737	39	0	0
T12	9118	126	0	0
T13	161919	0	0	0
T14	0	5214	0	0
T17	4761	74	0	0
T18	13124	143	0	0
T19	125668	662	0	0
T20	216209	1050	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2524866	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2524866	0	0
T1	876371	613	0	0
T2	40280	246	0	0
T3	65009	429	0	0
T11	4737	15	0	0
T12	9118	104	0	0
T13	161919	0	0	0
T14	0	2536	0	0
T17	4761	74	0	0
T18	13124	140	0	0
T19	125668	865	0	0
T20	216209	2406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1457129	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1457129	0	0
T1	876371	263	0	0
T2	40280	434	0	0
T3	65009	500	0	0
T11	4737	80	0	0
T12	9118	8	0	0
T13	161919	0	0	0
T17	4761	87	0	0
T18	13124	163	0	0
T19	125668	2299	0	0
T20	216209	1684	0	0
T21	0	1490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3627031	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3627031	0	0
T1	876371	248	0	0
T2	40280	177	0	0
T3	65009	239	0	0
T11	4737	62	0	0
T12	9118	11	0	0
T13	161919	0	0	0
T17	4761	87	0	0
T18	13124	142	0	0
T19	125668	3237	0	0
T20	216209	1297	0	0
T21	0	2039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1462176	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1462176	0	0
T1	876371	318	0	0
T2	40280	369	0	0
T3	65009	591	0	0
T11	4737	26	0	0
T12	9118	79	0	0
T13	161919	905	0	0
T17	4761	76	0	0
T18	13124	156	0	0
T19	125668	1761	0	0
T20	216209	1462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3722287	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3722287	0	0
T1	876371	551	0	0
T2	40280	144	0	0
T3	65009	369	0	0
T11	4737	7	0	0
T12	9118	90	0	0
T13	161919	70807	0	0
T17	4761	76	0	0
T18	13124	154	0	0
T19	125668	759	0	0
T20	216209	1676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1484713	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1484713	0	0
T1	876371	273	0	0
T2	40280	474	0	0
T3	65009	789	0	0
T11	4737	37	0	0
T12	9118	54	0	0
T13	161919	0	0	0
T14	0	5010	0	0
T17	4761	83	0	0
T18	13124	122	0	0
T19	125668	832	0	0
T20	216209	1871	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3371027	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3371027	0	0
T1	876371	60	0	0
T2	40280	206	0	0
T3	65009	387	0	0
T11	4737	39	0	0
T12	9118	40	0	0
T13	161919	0	0	0
T14	0	2404	0	0
T17	4761	83	0	0
T18	13124	146	0	0
T19	125668	1491	0	0
T20	216209	3357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1445730	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1445730	0	0
T1	876371	295	0	0
T2	40280	505	0	0
T3	65009	674	0	0
T11	4737	13	0	0
T12	9118	129	0	0
T13	161919	0	0	0
T14	0	3032	0	0
T17	4761	79	0	0
T18	13124	153	0	0
T19	125668	2056	0	0
T20	216209	1832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2936602	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2936602	0	0
T1	876371	458	0	0
T2	40280	203	0	0
T3	65009	309	0	0
T11	4737	2	0	0
T12	9118	91	0	0
T13	161919	0	0	0
T14	0	1463	0	0
T17	4761	79	0	0
T18	13124	155	0	0
T19	125668	839	0	0
T20	216209	1580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1418513	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1418513	0	0
T1	876371	198	0	0
T2	40280	434	0	0
T3	65009	605	0	0
T11	4737	59	0	0
T12	9118	69	0	0
T13	161919	0	0	0
T14	0	3382	0	0
T17	4761	91	0	0
T18	13124	141	0	0
T19	125668	0	0	0
T20	216209	895	0	0
T22	0	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3298236	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3298236	0	0
T1	876371	45	0	0
T2	40280	264	0	0
T3	65009	304	0	0
T11	4737	24	0	0
T12	9118	51	0	0
T13	161919	0	0	0
T14	0	1488	0	0
T17	4761	91	0	0
T18	13124	129	0	0
T19	125668	0	0	0
T20	216209	1006	0	0
T22	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1434870	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1434870	0	0
T1	876371	264	0	0
T2	40280	524	0	0
T3	65009	838	0	0
T11	4737	32	0	0
T12	9118	118	0	0
T13	161919	0	0	0
T14	0	7508	0	0
T17	4761	70	0	0
T18	13124	150	0	0
T19	125668	1349	0	0
T20	216209	2081	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2869954	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2869954	0	0
T1	876371	372	0	0
T2	40280	202	0	0
T3	65009	360	0	0
T11	4737	38	0	0
T12	9118	80	0	0
T13	161919	0	0	0
T14	0	3404	0	0
T17	4761	70	0	0
T18	13124	124	0	0
T19	125668	672	0	0
T20	216209	2748	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1436385	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1436385	0	0
T1	876371	329	0	0
T2	40280	406	0	0
T3	65009	751	0	0
T11	4737	60	0	0
T12	9118	64	0	0
T13	161919	0	0	0
T17	4761	101	0	0
T18	13124	167	0	0
T19	125668	650	0	0
T20	216209	2445	0	0
T21	0	1877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3237238	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3237238	0	0
T1	876371	72	0	0
T2	40280	176	0	0
T3	65009	312	0	0
T11	4737	48	0	0
T12	9118	78	0	0
T13	161919	0	0	0
T17	4761	101	0	0
T18	13124	101	0	0
T19	125668	335	0	0
T20	216209	3807	0	0
T21	0	2289	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1435144	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1435144	0	0
T1	876371	264	0	0
T2	40280	469	0	0
T3	65009	791	0	0
T11	4737	35	0	0
T12	9118	96	0	0
T13	161919	0	0	0
T14	0	3294	0	0
T17	4761	84	0	0
T18	13124	123	0	0
T19	125668	1451	0	0
T20	216209	2175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3218829	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3218829	0	0
T1	876371	63	0	0
T2	40280	229	0	0
T3	65009	332	0	0
T11	4737	34	0	0
T12	9118	59	0	0
T13	161919	0	0	0
T14	0	1363	0	0
T17	4761	84	0	0
T18	13124	151	0	0
T19	125668	1036	0	0
T20	216209	2380	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1415440	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1415440	0	0
T1	876371	295	0	0
T2	40280	660	0	0
T3	65009	605	0	0
T11	4737	23	0	0
T12	9118	137	0	0
T13	161919	1262	0	0
T17	4761	79	0	0
T18	13124	217	0	0
T19	125668	338	0	0
T20	216209	3121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3596492	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3596492	0	0
T1	876371	65	0	0
T2	40280	324	0	0
T3	65009	302	0	0
T11	4737	8	0	0
T12	9118	82	0	0
T13	161919	105221	0	0
T17	4761	79	0	0
T18	13124	218	0	0
T19	125668	798	0	0
T20	216209	3262	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1448221	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1448221	0	0
T1	876371	256	0	0
T2	40280	569	0	0
T3	65009	619	0	0
T11	4737	58	0	0
T12	9118	11	0	0
T13	161919	0	0	0
T17	4761	84	0	0
T18	13124	83	0	0
T19	125668	600	0	0
T20	216209	395	0	0
T21	0	2986	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3633082	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3633082	0	0
T1	876371	56	0	0
T2	40280	202	0	0
T3	65009	334	0	0
T11	4737	22	0	0
T12	9118	16	0	0
T13	161919	0	0	0
T17	4761	84	0	0
T18	13124	67	0	0
T19	125668	1664	0	0
T20	216209	415	0	0
T21	0	4162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1396282	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1396282	0	0
T1	876371	302	0	0
T2	40280	393	0	0
T3	65009	859	0	0
T11	4737	42	0	0
T12	9118	23	0	0
T13	161919	0	0	0
T14	0	2995	0	0
T17	4761	79	0	0
T18	13124	143	0	0
T19	125668	1530	0	0
T20	216209	3340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2905742	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2905742	0	0
T1	876371	69	0	0
T2	40280	183	0	0
T3	65009	397	0	0
T11	4737	7	0	0
T12	9118	37	0	0
T13	161919	0	0	0
T14	0	1392	0	0
T17	4761	79	0	0
T18	13124	120	0	0
T19	125668	1408	0	0
T20	216209	1809	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1440284	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1440284	0	0
T1	876371	236	0	0
T2	40280	431	0	0
T3	65009	847	0	0
T11	4737	37	0	0
T12	9118	45	0	0
T13	161919	1205	0	0
T17	4761	101	0	0
T18	13124	96	0	0
T19	125668	2088	0	0
T20	216209	1296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3510880	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3510880	0	0
T1	876371	56	0	0
T2	40280	181	0	0
T3	65009	374	0	0
T11	4737	70	0	0
T12	9118	30	0	0
T13	161919	95725	0	0
T17	4761	101	0	0
T18	13124	118	0	0
T19	125668	3138	0	0
T20	216209	1296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1442465	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1442465	0	0
T1	876371	253	0	0
T2	40280	496	0	0
T3	65009	936	0	0
T11	4737	20	0	0
T12	9118	41	0	0
T13	161919	0	0	0
T17	4761	74	0	0
T18	13124	110	0	0
T19	125668	1638	0	0
T20	216209	2756	0	0
T21	0	1388	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3307764	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3307764	0	0
T1	876371	182	0	0
T2	40280	188	0	0
T3	65009	346	0	0
T11	4737	2	0	0
T12	9118	32	0	0
T13	161919	0	0	0
T17	4761	74	0	0
T18	13124	81	0	0
T19	125668	1237	0	0
T20	216209	3552	0	0
T21	0	2039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1477611	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1477611	0	0
T1	876371	252	0	0
T2	40280	388	0	0
T3	65009	768	0	0
T11	4737	97	0	0
T12	9118	68	0	0
T13	161919	0	0	0
T14	0	6544	0	0
T17	4761	81	0	0
T18	13124	157	0	0
T19	125668	1776	0	0
T20	216209	1616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3049627	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3049627	0	0
T1	876371	67	0	0
T2	40280	151	0	0
T3	65009	244	0	0
T11	4737	45	0	0
T12	9118	126	0	0
T13	161919	0	0	0
T14	0	3308	0	0
T17	4761	81	0	0
T18	13124	156	0	0
T19	125668	972	0	0
T20	216209	2138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1483515	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1483515	0	0
T1	876371	288	0	0
T2	40280	569	0	0
T3	65009	759	0	0
T11	4737	7	0	0
T12	9118	64	0	0
T13	161919	0	0	0
T14	0	3223	0	0
T17	4761	89	0	0
T18	13124	161	0	0
T19	125668	1338	0	0
T20	216209	2125	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3300396	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3300396	0	0
T1	876371	68	0	0
T2	40280	201	0	0
T3	65009	342	0	0
T11	4737	15	0	0
T12	9118	94	0	0
T13	161919	0	0	0
T14	0	1440	0	0
T17	4761	89	0	0
T18	13124	168	0	0
T19	125668	180	0	0
T20	216209	1274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1452610	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1452610	0	0
T1	876371	278	0	0
T2	40280	481	0	0
T3	65009	754	0	0
T11	4737	41	0	0
T12	9118	103	0	0
T13	161919	0	0	0
T14	0	3307	0	0
T17	4761	83	0	0
T18	13124	62	0	0
T19	125668	1056	0	0
T20	216209	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2767887	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2767887	0	0
T1	876371	141	0	0
T2	40280	257	0	0
T3	65009	343	0	0
T11	4737	41	0	0
T12	9118	67	0	0
T13	161919	0	0	0
T14	0	1483	0	0
T17	4761	83	0	0
T18	13124	79	0	0
T19	125668	1494	0	0
T20	216209	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1444756	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1444756	0	0
T1	876371	272	0	0
T2	40280	525	0	0
T3	65009	576	0	0
T11	4737	52	0	0
T12	9118	33	0	0
T13	161919	0	0	0
T14	0	3217	0	0
T17	4761	82	0	0
T18	13124	119	0	0
T19	125668	1064	0	0
T20	216209	1778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3221108	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3221108	0	0
T1	876371	339	0	0
T2	40280	192	0	0
T3	65009	311	0	0
T11	4737	19	0	0
T12	9118	16	0	0
T13	161919	0	0	0
T14	0	1266	0	0
T17	4761	82	0	0
T18	13124	167	0	0
T19	125668	365	0	0
T20	216209	3097	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1521406	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1521406	0	0
T1	876371	326	0	0
T2	40280	409	0	0
T3	65009	788	0	0
T11	4737	22	0	0
T12	9118	101	0	0
T13	161919	895	0	0
T17	4761	94	0	0
T18	13124	147	0	0
T19	125668	196	0	0
T20	216209	3281	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	2770419	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	2770419	0	0
T1	876371	71	0	0
T2	40280	179	0	0
T3	65009	312	0	0
T11	4737	25	0	0
T12	9118	94	0	0
T13	161919	71179	0	0
T17	4761	94	0	0
T18	13124	183	0	0
T19	125668	586	0	0
T20	216209	2955	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	1417374	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	1417374	0	0
T1	876371	283	0	0
T2	40280	480	0	0
T3	65009	646	0	0
T11	4737	40	0	0
T12	9118	57	0	0
T13	161919	0	0	0
T14	0	2947	0	0
T17	4761	97	0	0
T18	13124	91	0	0
T19	125668	1210	0	0
T20	216209	542	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303991653	3070239	0	0
DepthKnown_A	303991653	303868096	0	0
RvalidKnown_A	303991653	303868096	0	0
WreadyKnown_A	303991653	303868096	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	3070239	0	0
T1	876371	56	0	0
T2	40280	239	0	0
T3	65009	270	0	0
T11	4737	81	0	0
T12	9118	84	0	0
T13	161919	0	0	0
T14	0	1326	0	0
T17	4761	97	0	0
T18	13124	103	0	0
T19	125668	382	0	0
T20	216209	312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303991653	303868096	0	0
T1	876371	876352	0	0
T2	40280	40226	0	0
T3	65009	64940	0	0
T11	4737	4680	0	0
T12	9118	9109	0	0
T13	161919	161912	0	0
T17	4761	4702	0	0
T18	13124	13095	0	0
T19	125668	125586	0	0
T20	216209	216163	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0