Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1924173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

302265

1

T1

232

T2

1

T3

399

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	751808	1			T1	610		T2	8		T3	945
values[0x0]	722595	1			T1	606		T2	3		T3	1009
values[0x1]	752035	1			T1	589		T2	12		T3	966

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1490359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

736079

1

T1

611

T2

6

T3

926

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9858	1			T3	6		T16	25		T18	8
valid_sources[0x01]	9282	1			T3	14		T16	1		T18	10
valid_sources[0x02]	9124	1			T3	16		T16	1		T18	11
valid_sources[0x03]	8913	1			T3	10		T18	1		T19	1
valid_sources[0x04]	9455	1			T3	5		T18	2		T20	2
valid_sources[0x05]	8148	1			T1	1		T3	4		T18	4
valid_sources[0x06]	10390	1			T3	12		T18	8		T19	37
valid_sources[0x07]	9996	1			T3	15		T18	7		T21	4
valid_sources[0x08]	8535	1			T3	11		T16	1		T18	10
valid_sources[0x09]	8031	1			T1	15		T3	10		T18	9
valid_sources[0x0a]	8725	1			T1	111		T2	1		T3	9
valid_sources[0x0b]	9099	1			T1	3		T3	17		T18	4
valid_sources[0x0c]	8866	1			T1	26		T3	5		T15	1
valid_sources[0x0d]	8076	1			T1	38		T3	8		T18	12
valid_sources[0x0e]	7768	1			T1	8		T2	1		T3	10
valid_sources[0x0f]	9213	1			T3	16		T15	1		T18	13
valid_sources[0x10]	9135	1			T3	19		T18	9		T20	1
valid_sources[0x11]	8311	1			T1	3		T3	9		T16	1
valid_sources[0x12]	9067	1			T3	10		T18	8		T19	19
valid_sources[0x13]	9136	1			T3	12		T15	1		T16	2
valid_sources[0x14]	8469	1			T1	13		T3	11		T16	8
valid_sources[0x15]	8818	1			T3	10		T16	3		T18	5
valid_sources[0x16]	7778	1			T3	10		T16	4		T18	5
valid_sources[0x17]	8171	1			T3	19		T18	6		T21	1
valid_sources[0x18]	9034	1			T3	21		T16	14		T18	6
valid_sources[0x19]	8282	1			T3	5		T16	4		T18	12
valid_sources[0x1a]	9569	1			T3	19		T18	13		T20	2
valid_sources[0x1b]	8663	1			T3	18		T16	5		T18	14
valid_sources[0x1c]	8251	1			T3	6		T15	2		T18	9
valid_sources[0x1d]	8526	1			T3	11		T15	1		T18	5
valid_sources[0x1e]	7750	1			T3	6		T16	5		T18	6
valid_sources[0x1f]	8218	1			T1	4		T3	9		T18	7
valid_sources[0x20]	9154	1			T1	5		T3	11		T18	12
valid_sources[0x21]	8094	1			T3	18		T18	5		T20	1
valid_sources[0x22]	8082	1			T3	7		T18	5		T19	27
valid_sources[0x23]	7688	1			T1	1		T3	13		T18	9
valid_sources[0x24]	8125	1			T3	9		T18	9		T21	6
valid_sources[0x25]	8399	1			T1	21		T3	17		T15	2
valid_sources[0x26]	8025	1			T3	4		T16	1		T18	4
valid_sources[0x27]	9574	1			T1	26		T3	10		T18	2
valid_sources[0x28]	8722	1			T2	1		T3	7		T18	5
valid_sources[0x29]	8867	1			T3	7		T15	1		T16	11
valid_sources[0x2a]	8428	1			T3	19		T16	1		T18	11
valid_sources[0x2b]	8399	1			T3	9		T16	1		T18	3
valid_sources[0x2c]	8352	1			T3	19		T16	2		T18	7
valid_sources[0x2d]	10213	1			T1	22		T3	22		T15	2
valid_sources[0x2e]	10233	1			T1	13		T3	7		T15	1
valid_sources[0x2f]	7851	1			T1	11		T3	13		T18	8
valid_sources[0x30]	8581	1			T3	15		T16	1		T18	12
valid_sources[0x31]	8857	1			T3	20		T18	5		T20	2
valid_sources[0x32]	10358	1			T3	12		T15	1		T16	7
valid_sources[0x33]	8300	1			T3	14		T15	3		T18	1
valid_sources[0x34]	9881	1			T3	12		T18	6		T21	25
valid_sources[0x35]	8444	1			T3	15		T18	6		T21	15
valid_sources[0x36]	8976	1			T2	1		T3	19		T18	4
valid_sources[0x37]	8210	1			T3	11		T15	2		T16	2
valid_sources[0x38]	9393	1			T1	111		T3	18		T16	19
valid_sources[0x39]	8394	1			T3	9		T18	12		T21	17
valid_sources[0x3a]	8154	1			T3	12		T15	5		T16	2
valid_sources[0x3b]	8829	1			T1	16		T3	6		T18	10
valid_sources[0x3c]	9490	1			T1	23		T3	15		T16	2
valid_sources[0x3d]	7761	1			T3	7		T16	1		T18	13
valid_sources[0x3e]	9435	1			T1	12		T3	9		T18	14
valid_sources[0x3f]	8513	1			T1	12		T3	8		T18	5
valid_sources[0x40]	8413	1			T3	7		T18	1		T21	3
valid_sources[0x41]	7396	1			T3	6		T15	1		T18	4
valid_sources[0x42]	9012	1			T1	13		T3	6		T18	8
valid_sources[0x43]	8637	1			T3	12		T18	3		T20	2
valid_sources[0x44]	8995	1			T3	12		T16	1		T20	2
valid_sources[0x45]	9256	1			T3	9		T18	13		T21	13
valid_sources[0x46]	9215	1			T3	21		T18	13		T19	9
valid_sources[0x47]	8323	1			T1	2		T3	13		T18	8
valid_sources[0x48]	8326	1			T3	12		T16	12		T18	5
valid_sources[0x49]	8565	1			T1	7		T3	8		T15	1
valid_sources[0x4a]	8377	1			T3	9		T18	11		T20	2
valid_sources[0x4b]	8644	1			T3	12		T15	1		T18	6
valid_sources[0x4c]	8363	1			T1	17		T3	9		T18	5
valid_sources[0x4d]	8177	1			T2	1		T3	17		T18	13
valid_sources[0x4e]	8638	1			T1	1		T3	14		T16	1
valid_sources[0x4f]	9548	1			T3	7		T15	12		T18	5
valid_sources[0x50]	8716	1			T3	12		T15	7		T16	3
valid_sources[0x51]	7481	1			T3	14		T18	4		T20	1
valid_sources[0x52]	8537	1			T3	5		T16	5		T18	4
valid_sources[0x53]	9937	1			T3	3		T18	11		T19	1
valid_sources[0x54]	8484	1			T3	11		T18	11		T21	12
valid_sources[0x55]	8453	1			T1	9		T3	14		T16	6
valid_sources[0x56]	9172	1			T1	2		T2	1		T3	14
valid_sources[0x57]	7397	1			T3	20		T18	3		T21	9
valid_sources[0x58]	9695	1			T1	4		T3	14		T18	7
valid_sources[0x59]	8665	1			T1	4		T3	12		T16	2
valid_sources[0x5a]	9006	1			T1	18		T3	10		T18	5
valid_sources[0x5b]	9337	1			T1	49		T3	7		T18	15
valid_sources[0x5c]	9298	1			T2	2		T3	4		T18	4
valid_sources[0x5d]	8533	1			T1	11		T3	4		T18	4
valid_sources[0x5e]	9447	1			T3	13		T16	1		T18	7
valid_sources[0x5f]	8374	1			T1	2		T3	9		T18	7
valid_sources[0x60]	8267	1			T1	4		T3	11		T16	1
valid_sources[0x61]	8248	1			T1	6		T3	7		T18	14
valid_sources[0x62]	8847	1			T1	14		T3	21		T15	5
valid_sources[0x63]	8439	1			T3	10		T16	2		T18	6
valid_sources[0x64]	8269	1			T2	1		T3	25		T18	5
valid_sources[0x65]	9441	1			T3	8		T16	1		T18	6
valid_sources[0x66]	8666	1			T1	5		T3	10		T15	15
valid_sources[0x67]	8347	1			T1	18		T3	7		T16	3
valid_sources[0x68]	9177	1			T3	10		T15	1		T18	3
valid_sources[0x69]	9431	1			T1	3		T3	12		T16	1
valid_sources[0x6a]	8224	1			T3	8		T18	5		T19	6
valid_sources[0x6b]	8748	1			T1	26		T3	9		T18	2
valid_sources[0x6c]	8386	1			T3	15		T15	2		T16	1
valid_sources[0x6d]	8883	1			T1	11		T3	11		T18	5
valid_sources[0x6e]	8808	1			T1	1		T3	6		T15	1
valid_sources[0x6f]	8413	1			T1	1		T3	12		T18	7
valid_sources[0x70]	8456	1			T3	7		T16	1		T18	1
valid_sources[0x71]	8277	1			T3	10		T16	2		T18	4
valid_sources[0x72]	8520	1			T1	2		T2	1		T3	16
valid_sources[0x73]	7629	1			T3	7		T16	1		T18	6
valid_sources[0x74]	8895	1			T1	26		T2	1		T3	16
valid_sources[0x75]	9487	1			T3	11		T15	5		T18	6
valid_sources[0x76]	8619	1			T1	6		T3	9		T18	20
valid_sources[0x77]	9611	1			T3	11		T15	1		T18	9
valid_sources[0x78]	7951	1			T3	11		T16	1		T18	5
valid_sources[0x79]	7920	1			T1	4		T3	8		T18	1
valid_sources[0x7a]	9439	1			T1	3		T3	12		T18	8
valid_sources[0x7b]	9441	1			T3	13		T15	5		T16	2
valid_sources[0x7c]	8458	1			T1	4		T3	10		T16	1
valid_sources[0x7d]	9151	1			T2	2		T3	12		T18	6
valid_sources[0x7e]	9276	1			T3	9		T18	6		T19	3
valid_sources[0x7f]	7818	1			T3	7		T15	5		T18	1
valid_sources[0x80]	9403	1			T3	14		T15	1		T18	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31505

1

T1

30

T3

38

T15

2

values[0x0]

all_enables

biggest_size

239451

1

T1

183

T2

1

T3

318

values[0x1]

all_enables

biggest_size

31309

1

T1

19

T3

43

T15

2