Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	355386133	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355386133	0	0
T1	50881600	905668	0	0
T2	495432	7106	0	0
T3	345632	14335	0	0
T15	268856	6207	0	0
T16	849296	36786	0	0
T17	66360	2638	0	0
T18	11278736	1735309	0	0
T19	8390760	1395249	0	0
T20	7540512	137901	0	0
T21	7479360	165126	0	0
T22	0	5980	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50881600	50880928	0	0
T2	495432	493976	0	0
T3	345632	340592	0	0
T15	268856	260680	0	0
T16	849296	836416	0	0
T17	66360	65184	0	0
T18	11278736	11278568	0	0
T19	8390760	8390648	0	0
T20	7540512	7538888	0	0
T21	7479360	7479360	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50881600	50880928	0	0
T2	495432	493976	0	0
T3	345632	340592	0	0
T15	268856	260680	0	0
T16	849296	836416	0	0
T17	66360	65184	0	0
T18	11278736	11278568	0	0
T19	8390760	8390648	0	0
T20	7540512	7538888	0	0
T21	7479360	7479360	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	50881600	50880928	0	0
T2	495432	493976	0	0
T3	345632	340592	0	0
T15	268856	260680	0	0
T16	849296	836416	0	0
T17	66360	65184	0	0
T18	11278736	11278568	0	0
T19	8390760	8390648	0	0
T20	7540512	7538888	0	0
T21	7479360	7479360	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	125307419	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	125307419	0	0
T1	908600	885068	0	0
T2	8847	3202	0	0
T3	6172	5575	0	0
T15	4801	2681	0	0
T16	15166	13055	0	0
T17	1185	1030	0	0
T18	201406	199075	0	0
T19	149835	147680	0	0
T20	134652	61154	0	0
T21	133560	130203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	93836387	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	93836387	0	0
T1	908600	6417	0	0
T2	8847	1099	0	0
T3	6172	2920	0	0
T15	4801	1219	0	0
T16	15166	8701	0	0
T17	1185	536	0	0
T18	201406	763746	0	0
T19	149835	619857	0	0
T20	134652	15568	0	0
T21	133560	11731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1631324	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1631324	0	0
T1	908600	259	0	0
T2	8847	28	0	0
T3	6172	131	0	0
T15	4801	16	0	0
T16	15166	484	0	0
T17	1185	18	0	0
T18	201406	329	0	0
T19	149835	312	0	0
T20	134652	3076	0	0
T21	133560	463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3886801	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3886801	0	0
T1	908600	70	0	0
T2	8847	34	0	0
T3	6172	131	0	0
T15	4801	1	0	0
T16	15166	484	0	0
T17	1185	18	0	0
T18	201406	25693	0	0
T19	149835	22400	0	0
T20	134652	1654	0	0
T21	133560	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1648837	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1648837	0	0
T1	908600	398	0	0
T2	8847	48	0	0
T3	6172	112	0	0
T15	4801	25	0	0
T16	15166	169	0	0
T17	1185	30	0	0
T18	201406	284	0	0
T19	149835	270	0	0
T20	134652	1947	0	0
T21	133560	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3717176	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3717176	0	0
T1	908600	1111	0	0
T2	8847	20	0	0
T3	6172	112	0	0
T15	4801	8	0	0
T16	15166	169	0	0
T17	1185	30	0	0
T18	201406	27249	0	0
T19	149835	15748	0	0
T20	134652	928	0	0
T21	133560	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1586963	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1586963	0	0
T1	908600	389	0	0
T2	8847	73	0	0
T3	6172	103	0	0
T15	4801	187	0	0
T16	15166	159	0	0
T17	1185	23	0	0
T18	201406	249	0	0
T19	149835	294	0	0
T20	134652	1607	0	0
T21	133560	385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3413947	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3413947	0	0
T1	908600	87	0	0
T2	8847	51	0	0
T3	6172	103	0	0
T15	4801	202	0	0
T16	15166	159	0	0
T17	1185	23	0	0
T18	201406	19332	0	0
T19	149835	25816	0	0
T20	134652	725	0	0
T21	133560	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1665301	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1665301	0	0
T1	908600	266	0	0
T2	8847	123	0	0
T3	6172	120	0	0
T15	4801	46	0	0
T16	15166	195	0	0
T17	1185	21	0	0
T18	201406	404	0	0
T19	149835	284	0	0
T20	134652	2012	0	0
T21	133560	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3571927	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3571927	0	0
T1	908600	443	0	0
T2	8847	35	0	0
T3	6172	120	0	0
T15	4801	20	0	0
T16	15166	195	0	0
T17	1185	21	0	0
T18	201406	31923	0	0
T19	149835	25038	0	0
T20	134652	509	0	0
T21	133560	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1611445	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1611445	0	0
T1	908600	247	0	0
T2	8847	88	0	0
T3	6172	98	0	0
T15	4801	30	0	0
T16	15166	598	0	0
T17	1185	22	0	0
T18	201406	354	0	0
T19	149835	211	0	0
T20	134652	919	0	0
T21	133560	391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3494108	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3494108	0	0
T1	908600	60	0	0
T2	8847	30	0	0
T3	6172	98	0	0
T15	4801	30	0	0
T16	15166	598	0	0
T17	1185	22	0	0
T18	201406	33395	0	0
T19	149835	17733	0	0
T20	134652	125	0	0
T21	133560	830	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1616519	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1616519	0	0
T1	908600	318	0	0
T2	8847	76	0	0
T3	6172	109	0	0
T15	4801	16	0	0
T16	15166	183	0	0
T17	1185	32	0	0
T18	201406	369	0	0
T19	149835	281	0	0
T20	134652	1521	0	0
T21	133560	377	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3065659	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3065659	0	0
T1	908600	71	0	0
T2	8847	35	0	0
T3	6172	109	0	0
T15	4801	25	0	0
T16	15166	183	0	0
T17	1185	32	0	0
T18	201406	30176	0	0
T19	149835	20652	0	0
T20	134652	105	0	0
T21	133560	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1584886	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1584886	0	0
T1	908600	299	0	0
T2	8847	65	0	0
T3	6172	107	0	0
T15	4801	18	0	0
T16	15166	371	0	0
T17	1185	13	0	0
T18	201406	328	0	0
T19	149835	328	0	0
T20	134652	3684	0	0
T21	133560	416	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3138308	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3138308	0	0
T1	908600	77	0	0
T2	8847	28	0	0
T3	6172	107	0	0
T15	4801	36	0	0
T16	15166	371	0	0
T17	1185	13	0	0
T18	201406	30125	0	0
T19	149835	24715	0	0
T20	134652	1114	0	0
T21	133560	1414	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1539605	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1539605	0	0
T1	908600	275	0	0
T2	8847	42	0	0
T3	6172	111	0	0
T15	4801	36	0	0
T16	15166	161	0	0
T17	1185	13	0	0
T18	201406	375	0	0
T19	149835	301	0	0
T20	134652	792	0	0
T21	133560	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3152785	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3152785	0	0
T1	908600	70	0	0
T2	8847	15	0	0
T3	6172	111	0	0
T15	4801	34	0	0
T16	15166	161	0	0
T17	1185	13	0	0
T18	201406	30483	0	0
T19	149835	22488	0	0
T20	134652	272	0	0
T21	133560	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1604227	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1604227	0	0
T1	908600	230	0	0
T2	8847	134	0	0
T3	6172	120	0	0
T15	4801	42	0	0
T16	15166	170	0	0
T17	1185	21	0	0
T18	201406	367	0	0
T19	149835	349	0	0
T20	134652	1061	0	0
T21	133560	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3920365	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3920365	0	0
T1	908600	103	0	0
T2	8847	65	0	0
T3	6172	120	0	0
T15	4801	34	0	0
T16	15166	170	0	0
T17	1185	21	0	0
T18	201406	31126	0	0
T19	149835	26092	0	0
T20	134652	40	0	0
T21	133560	195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1609080	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1609080	0	0
T1	908600	266	0	0
T2	8847	32	0	0
T3	6172	87	0	0
T15	4801	62	0	0
T16	15166	187	0	0
T17	1185	20	0	0
T18	201406	358	0	0
T19	149835	315	0	0
T20	134652	2132	0	0
T21	133560	378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3096203	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3096203	0	0
T1	908600	317	0	0
T2	8847	24	0	0
T3	6172	87	0	0
T15	4801	26	0	0
T16	15166	187	0	0
T17	1185	20	0	0
T18	201406	28344	0	0
T19	149835	22866	0	0
T20	134652	566	0	0
T21	133560	224	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1616309	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1616309	0	0
T1	908600	224	0	0
T2	8847	58	0	0
T3	6172	124	0	0
T15	4801	40	0	0
T16	15166	192	0	0
T17	1185	14	0	0
T18	201406	285	0	0
T19	149835	344	0	0
T20	134652	2455	0	0
T21	133560	513	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3652327	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3652327	0	0
T1	908600	55	0	0
T2	8847	27	0	0
T3	6172	124	0	0
T15	4801	72	0	0
T16	15166	192	0	0
T17	1185	14	0	0
T18	201406	31381	0	0
T19	149835	27729	0	0
T20	134652	792	0	0
T21	133560	2005	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1653520	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1653520	0	0
T1	908600	211	0	0
T2	8847	78	0	0
T3	6172	116	0	0
T15	4801	28	0	0
T16	15166	184	0	0
T17	1185	23	0	0
T18	201406	306	0	0
T19	149835	262	0	0
T20	134652	1086	0	0
T21	133560	327	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	4304495	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	4304495	0	0
T1	908600	57	0	0
T2	8847	20	0	0
T3	6172	116	0	0
T15	4801	26	0	0
T16	15166	184	0	0
T17	1185	23	0	0
T18	201406	26156	0	0
T19	149835	22003	0	0
T20	134652	180	0	0
T21	133560	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1616274	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1616274	0	0
T1	908600	291	0	0
T2	8847	48	0	0
T3	6172	97	0	0
T15	4801	144	0	0
T16	15166	172	0	0
T17	1185	22	0	0
T18	201406	346	0	0
T19	149835	262	0	0
T20	134652	0	0	0
T21	133560	440	0	0
T22	0	2926	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	2988847	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	2988847	0	0
T1	908600	72	0	0
T2	8847	33	0	0
T3	6172	97	0	0
T15	4801	99	0	0
T16	15166	172	0	0
T17	1185	22	0	0
T18	201406	30043	0	0
T19	149835	20817	0	0
T20	134652	0	0	0
T21	133560	337	0	0
T22	0	3054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1587343	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1587343	0	0
T1	908600	285	0	0
T2	8847	95	0	0
T3	6172	89	0	0
T15	4801	44	0	0
T16	15166	175	0	0
T17	1185	24	0	0
T18	201406	321	0	0
T19	149835	268	0	0
T20	134652	797	0	0
T21	133560	400	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3188896	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3188896	0	0
T1	908600	73	0	0
T2	8847	16	0	0
T3	6172	89	0	0
T15	4801	43	0	0
T16	15166	175	0	0
T17	1185	24	0	0
T18	201406	22350	0	0
T19	149835	20889	0	0
T20	134652	918	0	0
T21	133560	1295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1600065	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1600065	0	0
T1	908600	241	0	0
T2	8847	113	0	0
T3	6172	85	0	0
T15	4801	21	0	0
T16	15166	449	0	0
T17	1185	19	0	0
T18	201406	323	0	0
T19	149835	306	0	0
T20	134652	1370	0	0
T21	133560	445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3460809	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3460809	0	0
T1	908600	64	0	0
T2	8847	50	0	0
T3	6172	85	0	0
T15	4801	31	0	0
T16	15166	449	0	0
T17	1185	19	0	0
T18	201406	31260	0	0
T19	149835	20908	0	0
T20	134652	268	0	0
T21	133560	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1631653	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1631653	0	0
T1	908600	341	0	0
T2	8847	92	0	0
T3	6172	88	0	0
T15	4801	23	0	0
T16	15166	169	0	0
T17	1185	18	0	0
T18	201406	273	0	0
T19	149835	272	0	0
T20	134652	1332	0	0
T21	133560	427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3416674	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3416674	0	0
T1	908600	1030	0	0
T2	8847	47	0	0
T3	6172	88	0	0
T15	4801	43	0	0
T16	15166	169	0	0
T17	1185	18	0	0
T18	201406	27170	0	0
T19	149835	21931	0	0
T20	134652	517	0	0
T21	133560	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1537240	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1537240	0	0
T1	908600	280	0	0
T2	8847	64	0	0
T3	6172	103	0	0
T15	4801	22	0	0
T16	15166	180	0	0
T17	1185	14	0	0
T18	201406	354	0	0
T19	149835	290	0	0
T20	134652	1238	0	0
T21	133560	477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3913741	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3913741	0	0
T1	908600	541	0	0
T2	8847	26	0	0
T3	6172	103	0	0
T15	4801	16	0	0
T16	15166	180	0	0
T17	1185	14	0	0
T18	201406	25998	0	0
T19	149835	23214	0	0
T20	134652	568	0	0
T21	133560	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1659186	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1659186	0	0
T1	908600	345	0	0
T2	8847	55	0	0
T3	6172	106	0	0
T15	4801	31	0	0
T16	15166	185	0	0
T17	1185	14	0	0
T18	201406	338	0	0
T19	149835	323	0	0
T20	134652	1973	0	0
T21	133560	427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3798302	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3798302	0	0
T1	908600	84	0	0
T2	8847	21	0	0
T3	6172	106	0	0
T15	4801	13	0	0
T16	15166	185	0	0
T17	1185	14	0	0
T18	201406	33409	0	0
T19	149835	27404	0	0
T20	134652	180	0	0
T21	133560	509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1613838	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1613838	0	0
T1	908600	251	0	0
T2	8847	90	0	0
T3	6172	124	0	0
T15	4801	24	0	0
T16	15166	379	0	0
T17	1185	15	0	0
T18	201406	300	0	0
T19	149835	236	0	0
T20	134652	1689	0	0
T21	133560	454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3718958	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3718958	0	0
T1	908600	69	0	0
T2	8847	26	0	0
T3	6172	124	0	0
T15	4801	41	0	0
T16	15166	379	0	0
T17	1185	15	0	0
T18	201406	26516	0	0
T19	149835	18664	0	0
T20	134652	651	0	0
T21	133560	929	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1622052	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1622052	0	0
T1	908600	358	0	0
T2	8847	42	0	0
T3	6172	112	0	0
T15	4801	35	0	0
T16	15166	458	0	0
T17	1185	16	0	0
T18	201406	353	0	0
T19	149835	294	0	0
T20	134652	1895	0	0
T21	133560	398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	4119008	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	4119008	0	0
T1	908600	366	0	0
T2	8847	19	0	0
T3	6172	112	0	0
T15	4801	7	0	0
T16	15166	458	0	0
T17	1185	16	0	0
T18	201406	34229	0	0
T19	149835	22406	0	0
T20	134652	950	0	0
T21	133560	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1574378	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1574378	0	0
T1	908600	302	0	0
T2	8847	60	0	0
T3	6172	107	0	0
T15	4801	7	0	0
T16	15166	418	0	0
T17	1185	26	0	0
T18	201406	262	0	0
T19	149835	385	0	0
T20	134652	2095	0	0
T21	133560	536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3210658	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3210658	0	0
T1	908600	68	0	0
T2	8847	37	0	0
T3	6172	107	0	0
T15	4801	7	0	0
T16	15166	418	0	0
T17	1185	26	0	0
T18	201406	28641	0	0
T19	149835	29601	0	0
T20	134652	662	0	0
T21	133560	536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1586617	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1586617	0	0
T1	908600	268	0	0
T2	8847	143	0	0
T3	6172	122	0	0
T15	4801	40	0	0
T16	15166	471	0	0
T17	1185	20	0	0
T18	201406	295	0	0
T19	149835	235	0	0
T20	134652	1450	0	0
T21	133560	462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	2725479	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	2725479	0	0
T1	908600	72	0	0
T2	8847	18	0	0
T3	6172	122	0	0
T15	4801	43	0	0
T16	15166	471	0	0
T17	1185	20	0	0
T18	201406	21596	0	0
T19	149835	21369	0	0
T20	134652	406	0	0
T21	133560	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1637161	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1637161	0	0
T1	908600	244	0	0
T2	8847	51	0	0
T3	6172	109	0	0
T15	4801	14	0	0
T16	15166	412	0	0
T17	1185	19	0	0
T18	201406	348	0	0
T19	149835	300	0	0
T20	134652	3026	0	0
T21	133560	454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	2869860	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	2869860	0	0
T1	908600	214	0	0
T2	8847	30	0	0
T3	6172	109	0	0
T15	4801	32	0	0
T16	15166	412	0	0
T17	1185	19	0	0
T18	201406	29784	0	0
T19	149835	27112	0	0
T20	134652	1418	0	0
T21	133560	305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1578577	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1578577	0	0
T1	908600	313	0	0
T2	8847	72	0	0
T3	6172	110	0	0
T15	4801	20	0	0
T16	15166	184	0	0
T17	1185	17	0	0
T18	201406	272	0	0
T19	149835	272	0	0
T20	134652	777	0	0
T21	133560	330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3219813	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3219813	0	0
T1	908600	240	0	0
T2	8847	50	0	0
T3	6172	110	0	0
T15	4801	32	0	0
T16	15166	184	0	0
T17	1185	17	0	0
T18	201406	26676	0	0
T19	149835	24507	0	0
T20	134652	26	0	0
T21	133560	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1609725	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1609725	0	0
T1	908600	267	0	0
T2	8847	57	0	0
T3	6172	119	0	0
T15	4801	159	0	0
T16	15166	174	0	0
T17	1185	16	0	0
T18	201406	343	0	0
T19	149835	271	0	0
T20	134652	957	0	0
T21	133560	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3239593	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3239593	0	0
T1	908600	65	0	0
T2	8847	34	0	0
T3	6172	119	0	0
T15	4801	124	0	0
T16	15166	174	0	0
T17	1185	16	0	0
T18	201406	27967	0	0
T19	149835	22368	0	0
T20	134652	95	0	0
T21	133560	1256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1593468	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1593468	0	0
T1	908600	369	0	0
T2	8847	75	0	0
T3	6172	109	0	0
T15	4801	35	0	0
T16	15166	459	0	0
T17	1185	21	0	0
T18	201406	241	0	0
T19	149835	298	0	0
T20	134652	1426	0	0
T21	133560	309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3045893	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3045893	0	0
T1	908600	878	0	0
T2	8847	30	0	0
T3	6172	109	0	0
T15	4801	26	0	0
T16	15166	459	0	0
T17	1185	21	0	0
T18	201406	18297	0	0
T19	149835	21386	0	0
T20	134652	629	0	0
T21	133560	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	1630500	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	1630500	0	0
T1	908600	231	0	0
T2	8847	64	0	0
T3	6172	102	0	0
T15	4801	40	0	0
T16	15166	177	0	0
T17	1185	25	0	0
T18	201406	365	0	0
T19	149835	292	0	0
T20	134652	3294	0	0
T21	133560	538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	335839383	3465602	0	0
DepthKnown_A	335839383	335718700	0	0
RvalidKnown_A	335839383	335718700	0	0
WreadyKnown_A	335839383	335718700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	3465602	0	0
T1	908600	58	0	0
T2	8847	18	0	0
T3	6172	102	0	0
T15	4801	31	0	0
T16	15166	177	0	0
T17	1185	25	0	0
T18	201406	34427	0	0
T19	149835	24001	0	0
T20	134652	1270	0	0
T21	133560	389	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335839383	335718700	0	0
T1	908600	908588	0	0
T2	8847	8821	0	0
T3	6172	6082	0	0
T15	4801	4655	0	0
T16	15166	14936	0	0
T17	1185	1164	0	0
T18	201406	201403	0	0
T19	149835	149833	0	0
T20	134652	134623	0	0
T21	133560	133560	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0