Unified Coverage Report :: Module :: tlul_fifo_sync

Module : tlul_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d	100.00		100.00			100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d	100.00		100.00			100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.28	100.00	93.10			100.00	100.00	u_s1n_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Cond Coverage for Module : tlul_fifo_sync

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_fifo_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.fifo_h

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.fifo_h

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T3,T5,T16

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T16

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T16
0	Covered	T1,T3,T5

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3