Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	336621683	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	336621683
T1	41418	720
T2	201432	4406
T3	38136	933
T4	37072	789
T5	45416	631
T6	44072	789
T13	212296	9457
T14	202216	6304
T17	88928	1076
T18	60872	1136
T19	174664	3218
T20	0	1519

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	42952	39144
T2	201432	195944
T3	38136	36176
T4	37072	35280
T5	45416	40544
T6	44072	40656
T13	212296	211736
T14	202216	197904
T18	60872	56224
T19	174664	173656

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	42952	39144
T2	201432	195944
T3	38136	36176
T4	37072	35280
T5	45416	40544
T6	44072	40656
T13	212296	211736
T14	202216	197904
T18	60872	56224
T19	174664	173656

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	42952	39144
T2	201432	195944
T3	38136	36176
T4	37072	35280
T5	45416	40544
T6	44072	40656
T13	212296	211736
T14	202216	197904
T18	60872	56224
T19	174664	173656

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T6	56	56
T13	56	56
T14	56	56
T18	56	56
T19	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	127203346	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	127203346
T1	767	282
T2	3597	1860
T3	681	360
T4	662	309
T5	811	247
T6	787	309
T13	3791	3681
T14	3611	3096
T18	1087	284
T19	3119	1410

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	85155246	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	85155246
T1	767	146
T2	3597	821
T3	681	191
T4	662	160
T5	811	128
T6	787	160
T13	3791	1926
T14	3611	1584
T18	1087	284
T19	3119	436

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1476978	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1476978
T1	767	7
T2	3597	45
T3	681	5
T4	662	2
T5	811	5
T6	787	10
T13	3791	75
T14	3611	23
T18	1087	12
T19	3119	5

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2818370	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2818370
T1	767	7
T2	3597	55
T3	681	5
T4	662	2
T5	811	5
T6	787	10
T13	3791	75
T14	3611	23
T18	1087	12
T19	3119	3

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1497517	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1497517
T1	767	5
T2	3597	2
T3	681	9
T4	662	3
T5	811	4
T6	787	5
T13	3791	72
T14	3611	29
T18	1087	9
T19	3119	14

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3166547	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3166547
T1	767	5
T2	3597	16
T3	681	9
T4	662	3
T5	811	4
T6	787	5
T13	3791	72
T14	3611	29
T18	1087	9
T19	3119	23

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1507638	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1507638
T1	767	7
T2	3597	39
T3	681	5
T4	662	4
T5	811	10
T6	787	10
T13	3791	73
T14	3611	43
T18	1087	12
T19	3119	22

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3040430	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3040430
T1	767	7
T2	3597	31
T3	681	5
T4	662	4
T5	811	10
T6	787	10
T13	3791	73
T14	3611	43
T18	1087	12
T19	3119	21

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1474050	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1474050
T1	767	5
T2	3597	39
T3	681	8
T4	662	5
T5	811	6
T6	787	10
T13	3791	78
T14	3611	20
T18	1087	6
T19	3119	21

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3089774	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3089774
T1	767	5
T2	3597	55
T3	681	8
T4	662	5
T5	811	6
T6	787	10
T13	3791	78
T14	3611	20
T18	1087	6
T19	3119	2

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1491881	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1491881
T1	767	8
T2	3597	26
T3	681	7
T4	662	8
T5	811	4
T6	787	7
T13	3791	63
T14	3611	32
T18	1087	11
T19	3119	68

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2981734	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2981734
T1	767	8
T2	3597	12
T3	681	7
T4	662	8
T5	811	4
T6	787	7
T13	3791	63
T14	3611	32
T18	1087	11
T19	3119	11

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1476737	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1476737
T2	3597	24
T3	681	14
T4	662	7
T5	811	4
T6	787	5
T13	3791	64
T14	3611	30
T17	44464	303
T18	1087	8
T19	3119	39

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T6 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3106023	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3106023
T2	3597	21
T3	681	14
T4	662	7
T5	811	4
T6	787	5
T13	3791	64
T14	3611	30
T17	44464	295
T18	1087	8
T19	3119	16

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1442598	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1442598
T1	767	10
T2	3597	11
T3	681	2
T4	662	5
T5	811	5
T6	787	4
T13	3791	67
T14	3611	32
T18	1087	10
T19	3119	4

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3114071	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3114071
T1	767	10
T2	3597	34
T3	681	2
T4	662	5
T5	811	5
T6	787	4
T13	3791	67
T14	3611	32
T18	1087	10
T19	3119	1

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1501197	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1501197
T1	767	3
T2	3597	33
T3	681	5
T4	662	6
T5	811	9
T6	787	7
T13	3791	75
T14	3611	30
T18	1087	15
T19	3119	17

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3294503	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3294503
T1	767	3
T2	3597	22
T3	681	5
T4	662	6
T5	811	9
T6	787	7
T13	3791	75
T14	3611	30
T18	1087	15
T19	3119	15

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1503820	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1503820
T1	767	3
T2	3597	26
T3	681	4
T4	662	2
T5	811	4
T6	787	7
T13	3791	67
T14	3611	33
T18	1087	16
T19	3119	50

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3212505	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3212505
T1	767	3
T2	3597	39
T3	681	4
T4	662	2
T5	811	4
T6	787	7
T13	3791	67
T14	3611	33
T18	1087	16
T19	3119	13

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1512422	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1512422
T1	767	4
T2	3597	0
T3	681	4
T4	662	8
T5	811	7
T6	787	0
T13	3791	67
T14	3611	32
T17	0	282
T18	1087	7
T19	3119	12
T20	0	778

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2793448	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2793448
T1	767	4
T2	3597	0
T3	681	4
T4	662	8
T5	811	7
T6	787	0
T13	3791	67
T14	3611	32
T17	0	196
T18	1087	7
T19	3119	3
T20	0	741

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1512795	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1512795
T1	767	1
T2	3597	70
T3	681	9
T4	662	4
T5	811	1
T6	787	6
T13	3791	67
T14	3611	20
T18	1087	13
T19	3119	39

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3456326	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3456326
T1	767	1
T2	3597	47
T3	681	9
T4	662	4
T5	811	1
T6	787	6
T13	3791	67
T14	3611	20
T18	1087	13
T19	3119	15

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1491088	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1491088
T1	767	4
T2	3597	90
T3	681	7
T4	662	7
T5	811	5
T6	787	4
T13	3791	89
T14	3611	27
T18	1087	9
T19	3119	26

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3080378	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3080378
T1	767	4
T2	3597	60
T3	681	7
T4	662	7
T5	811	5
T6	787	4
T13	3791	89
T14	3611	27
T18	1087	9
T19	3119	18

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1464837	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1464837
T1	767	4
T2	3597	41
T3	681	6
T4	662	7
T5	811	7
T6	787	5
T13	3791	66
T14	3611	35
T18	1087	14
T19	3119	49

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3888665	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3888665
T1	767	4
T2	3597	23
T3	681	6
T4	662	7
T5	811	7
T6	787	5
T13	3791	66
T14	3611	35
T18	1087	14
T19	3119	16

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1477484	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1477484
T1	767	4
T2	3597	15
T3	681	7
T4	662	5
T5	811	5
T6	787	6
T13	3791	67
T14	3611	23
T18	1087	6
T19	3119	61

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3150530	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3150530
T1	767	4
T2	3597	26
T3	681	7
T4	662	5
T5	811	5
T6	787	6
T13	3791	67
T14	3611	23
T18	1087	6
T19	3119	46

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1465040	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1465040
T1	767	9
T2	3597	41
T3	681	8
T4	662	8
T5	811	3
T6	787	11
T13	3791	70
T14	3611	32
T18	1087	9
T19	3119	22

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2628849	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2628849
T1	767	9
T2	3597	29
T3	681	8
T4	662	8
T5	811	3
T6	787	11
T13	3791	70
T14	3611	32
T18	1087	9
T19	3119	2

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1437959	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1437959
T1	767	5
T2	3597	12
T3	681	9
T4	662	5
T5	811	5
T6	787	2
T13	3791	62
T14	3611	27
T18	1087	11
T19	3119	9

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3341187	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3341187
T1	767	5
T2	3597	16
T3	681	9
T4	662	5
T5	811	5
T6	787	2
T13	3791	62
T14	3611	27
T18	1087	11
T19	3119	2

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1477209	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1477209
T1	767	3
T2	3597	13
T3	681	3
T4	662	10
T5	811	4
T6	787	9
T13	3791	78
T14	3611	29
T18	1087	10
T19	3119	38

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3200590	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3200590
T1	767	3
T2	3597	16
T3	681	3
T4	662	10
T5	811	4
T6	787	9
T13	3791	78
T14	3611	29
T18	1087	10
T19	3119	35

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1470895	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1470895
T1	767	6
T2	3597	30
T3	681	7
T4	662	5
T5	811	6
T6	787	5
T13	3791	63
T14	3611	38
T18	1087	10
T19	3119	34

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2662625	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2662625
T1	767	6
T2	3597	36
T3	681	7
T4	662	5
T5	811	6
T6	787	5
T13	3791	63
T14	3611	38
T18	1087	10
T19	3119	11

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1410189	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1410189
T1	767	3
T2	3597	86
T3	681	9
T4	662	8
T5	811	4
T6	787	6
T13	3791	89
T14	3611	30
T18	1087	11
T19	3119	63

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2913455	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2913455
T1	767	3
T2	3597	37
T3	681	9
T4	662	8
T5	811	4
T6	787	6
T13	3791	89
T14	3611	30
T18	1087	11
T19	3119	31

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1476011	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1476011
T1	767	7
T2	3597	23
T3	681	6
T4	662	2
T5	811	3
T6	787	5
T13	3791	77
T14	3611	41
T18	1087	6
T19	3119	71

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2808573	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2808573
T1	767	7
T2	3597	15
T3	681	6
T4	662	2
T5	811	3
T6	787	5
T13	3791	77
T14	3611	41
T18	1087	6
T19	3119	56

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1433330	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1433330
T1	767	8
T2	3597	39
T3	681	12
T4	662	11
T5	811	2
T6	787	8
T13	3791	72
T14	3611	34
T18	1087	10
T19	3119	90

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	2784781	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	2784781
T1	767	8
T2	3597	21
T3	681	12
T4	662	11
T5	811	2
T6	787	8
T13	3791	72
T14	3611	34
T18	1087	10
T19	3119	19

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1497422	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1497422
T1	767	12
T2	3597	48
T3	681	9
T4	662	7
T5	811	5
T6	787	3
T13	3791	70
T14	3611	26
T18	1087	10
T19	3119	4

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3200255	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3200255
T1	767	12
T2	3597	48
T3	681	9
T4	662	7
T5	811	5
T6	787	3
T13	3791	70
T14	3611	26
T18	1087	10
T19	3119	6

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1500781	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1500781
T1	767	4
T2	3597	63
T3	681	12
T4	662	7
T5	811	6
T6	787	3
T13	3791	79
T14	3611	27
T18	1087	11
T19	3119	101

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3620454	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3620454
T1	767	4
T2	3597	72
T3	681	12
T4	662	7
T5	811	6
T6	787	3
T13	3791	79
T14	3611	27
T18	1087	11
T19	3119	24

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1461727	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1461727
T1	767	6
T2	3597	30
T3	681	6
T4	662	6
T5	811	3
T6	787	2
T13	3791	58
T14	3611	28
T18	1087	8
T19	3119	2

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3109347	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3109347
T1	767	6
T2	3597	17
T3	681	6
T4	662	6
T5	811	3
T6	787	2
T13	3791	58
T14	3611	28
T18	1087	8
T19	3119	2

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1501617	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1501617
T1	767	2
T2	3597	32
T3	681	10
T4	662	6
T5	811	6
T6	787	7
T13	3791	70
T14	3611	28
T18	1087	14
T19	3119	31

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3401185	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3401185
T1	767	2
T2	3597	39
T3	681	10
T4	662	6
T5	811	6
T6	787	7
T13	3791	70
T14	3611	28
T18	1087	14
T19	3119	15

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1497087	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1497087
T1	767	5
T2	3597	3
T3	681	5
T4	662	9
T5	811	1
T6	787	7
T13	3791	72
T14	3611	38
T18	1087	14
T19	3119	12

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3055588	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3055588
T1	767	5
T2	3597	17
T3	681	5
T4	662	9
T5	811	1
T6	787	7
T13	3791	72
T14	3611	38
T18	1087	14
T19	3119	17

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	1474355	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	1474355
T1	767	11
T2	3597	23
T3	681	3
T4	662	3
T5	811	4
T6	787	6
T13	3791	75
T14	3611	25
T18	1087	12
T19	3119	32

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300575583	3408234	0	0
DepthKnown_A	300575583	300446146	0	0
RvalidKnown_A	300575583	300446146	0	0
WreadyKnown_A	300575583	300446146	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	300575583	3408234
T1	767	11
T2	3597	17
T3	681	3
T4	662	3
T5	811	4
T6	787	6
T13	3791	75
T14	3611	25
T18	1087	12
T19	3119	13

DepthKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

RvalidKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

WreadyKnown_A

Name	Attempts	Real Successes
Total	300575583	300446146
T1	767	699
T2	3597	3499
T3	681	646
T4	662	630
T5	811	724
T6	787	726
T13	3791	3781
T14	3611	3534
T18	1087	1004
T19	3119	3101

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T14	1	1
T18	1	1
T19	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children