Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	343582380	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343582380	0	0
T1	41272	873	0	0
T2	9771328	234607	0	0
T3	1225504	17371	0	0
T4	4425512	129252	0	0
T5	90328	3073	0	0
T15	45808	742	0	0
T19	27216	490	0	0
T20	797608	21305	0	0
T21	31828944	568820	0	0
T22	7671944	137279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	41272	38080	0	0
T2	9771328	9770488	0	0
T3	1225504	1224104	0	0
T4	4425512	4423608	0	0
T5	90328	86520	0	0
T15	45808	41832	0	0
T19	27216	24584	0	0
T20	797608	797272	0	0
T21	31828944	31828216	0	0
T22	7671944	7669928	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	41272	38080	0	0
T2	9771328	9770488	0	0
T3	1225504	1224104	0	0
T4	4425512	4423608	0	0
T5	90328	86520	0	0
T15	45808	41832	0	0
T19	27216	24584	0	0
T20	797608	797272	0	0
T21	31828944	31828216	0	0
T22	7671944	7669928	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	41272	38080	0	0
T2	9771328	9770488	0	0
T3	1225504	1224104	0	0
T4	4425512	4423608	0	0
T5	90328	86520	0	0
T15	45808	41832	0	0
T19	27216	24584	0	0
T20	797608	797272	0	0
T21	31828944	31828216	0	0
T22	7671944	7669928	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T15	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	122812715	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	122812715	0	0
T1	737	339	0	0
T2	174488	97309	0	0
T3	21884	4387	0	0
T4	79027	77690	0	0
T5	1613	1195	0	0
T15	818	286	0	0
T19	486	192	0	0
T20	14243	9221	0	0
T21	568374	554600	0	0
T22	136999	63248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	90950392	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	90950392	0	0
T1	737	178	0	0
T2	174488	46047	0	0
T3	21884	4313	0	0
T4	79027	25921	0	0
T5	1613	626	0	0
T15	818	152	0	0
T19	486	100	0	0
T20	14243	4088	0	0
T21	568374	4605	0	0
T22	136999	14910	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1480017	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1480017	0	0
T1	737	8	0	0
T2	174488	647	0	0
T3	21884	250	0	0
T4	79027	14	0	0
T5	1613	17	0	0
T15	818	5	0	0
T19	486	2	0	0
T20	14243	118	0	0
T21	568374	177	0	0
T22	136999	1804	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3673538	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3673538	0	0
T1	737	8	0	0
T2	174488	435	0	0
T3	21884	243	0	0
T4	79027	1697	0	0
T5	1613	17	0	0
T15	818	5	0	0
T19	486	2	0	0
T20	14243	121	0	0
T21	568374	32	0	0
T22	136999	864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1475852	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1475852	0	0
T1	737	8	0	0
T2	174488	1603	0	0
T3	21884	170	0	0
T4	79027	17	0	0
T5	1613	12	0	0
T15	818	5	0	0
T19	486	3	0	0
T20	14243	145	0	0
T21	568374	158	0	0
T22	136999	2602	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3099866	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3099866	0	0
T1	737	8	0	0
T2	174488	939	0	0
T3	21884	203	0	0
T4	79027	1105	0	0
T5	1613	12	0	0
T15	818	5	0	0
T19	486	3	0	0
T20	14243	151	0	0
T21	568374	36	0	0
T22	136999	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1480457	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1480457	0	0
T1	737	5	0	0
T2	174488	1619	0	0
T3	21884	150	0	0
T4	79027	18	0	0
T5	1613	20	0	0
T15	818	2	0	0
T19	486	2	0	0
T20	14243	171	0	0
T21	568374	178	0	0
T22	136999	1464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3776067	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3776067	0	0
T1	737	5	0	0
T2	174488	1275	0	0
T3	21884	272	0	0
T4	79027	1634	0	0
T5	1613	20	0	0
T15	818	2	0	0
T19	486	2	0	0
T20	14243	198	0	0
T21	568374	36	0	0
T22	136999	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1521379	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1521379	0	0
T1	737	7	0	0
T2	174488	833	0	0
T3	21884	160	0	0
T4	79027	2	0	0
T5	1613	25	0	0
T15	818	4	0	0
T19	486	3	0	0
T20	14243	200	0	0
T21	568374	231	0	0
T22	136999	1636	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3444161	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3444161	0	0
T1	737	7	0	0
T2	174488	1299	0	0
T3	21884	168	0	0
T4	79027	36	0	0
T5	1613	25	0	0
T15	818	4	0	0
T19	486	3	0	0
T20	14243	210	0	0
T21	568374	49	0	0
T22	136999	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1432416	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1432416	0	0
T1	737	7	0	0
T2	174488	1515	0	0
T3	21884	139	0	0
T4	79027	7	0	0
T5	1613	27	0	0
T15	818	9	0	0
T19	486	2	0	0
T20	14243	153	0	0
T21	568374	114	0	0
T22	136999	1474	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3282789	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3282789	0	0
T1	737	7	0	0
T2	174488	1227	0	0
T3	21884	129	0	0
T4	79027	340	0	0
T5	1613	27	0	0
T15	818	9	0	0
T19	486	2	0	0
T20	14243	146	0	0
T21	568374	35	0	0
T22	136999	439	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1478310	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1478310	0	0
T1	737	5	0	0
T2	174488	748	0	0
T3	21884	171	0	0
T4	79027	5	0	0
T5	1613	25	0	0
T15	818	4	0	0
T19	486	2	0	0
T20	14243	160	0	0
T21	568374	249	0	0
T22	136999	1300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	2404877	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	2404877	0	0
T1	737	5	0	0
T2	174488	726	0	0
T3	21884	133	0	0
T4	79027	99	0	0
T5	1613	25	0	0
T15	818	4	0	0
T19	486	2	0	0
T20	14243	154	0	0
T21	568374	52	0	0
T22	136999	666	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1482513	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1482513	0	0
T1	737	4	0	0
T2	174488	2332	0	0
T3	21884	165	0	0
T4	79027	12	0	0
T5	1613	19	0	0
T15	818	11	0	0
T19	486	6	0	0
T20	14243	137	0	0
T21	568374	244	0	0
T22	136999	920	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3984880	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3984880	0	0
T1	737	4	0	0
T2	174488	2643	0	0
T3	21884	212	0	0
T4	79027	637	0	0
T5	1613	19	0	0
T15	818	11	0	0
T19	486	6	0	0
T20	14243	140	0	0
T21	568374	60	0	0
T22	136999	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1464764	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1464764	0	0
T1	737	10	0	0
T2	174488	2451	0	0
T3	21884	110	0	0
T4	79027	40	0	0
T5	1613	24	0	0
T15	818	5	0	0
T19	486	2	0	0
T20	14243	148	0	0
T21	568374	150	0	0
T22	136999	1135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	2756825	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	2756825	0	0
T1	737	10	0	0
T2	174488	1836	0	0
T3	21884	172	0	0
T4	79027	3470	0	0
T5	1613	24	0	0
T15	818	5	0	0
T19	486	2	0	0
T20	14243	161	0	0
T21	568374	35	0	0
T22	136999	946	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1457197	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1457197	0	0
T1	737	6	0	0
T2	174488	1335	0	0
T3	21884	302	0	0
T4	79027	4	0	0
T5	1613	27	0	0
T15	818	2	0	0
T19	486	1	0	0
T20	14243	134	0	0
T21	568374	145	0	0
T22	136999	3575	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3797609	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3797609	0	0
T1	737	6	0	0
T2	174488	750	0	0
T3	21884	302	0	0
T4	79027	58	0	0
T5	1613	27	0	0
T15	818	2	0	0
T19	486	1	0	0
T20	14243	130	0	0
T21	568374	34	0	0
T22	136999	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1476785	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1476785	0	0
T1	737	8	0	0
T2	174488	1354	0	0
T3	21884	135	0	0
T4	79027	8	0	0
T5	1613	19	0	0
T15	818	4	0	0
T19	486	4	0	0
T20	14243	197	0	0
T21	568374	145	0	0
T22	136999	827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	2890671	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	2890671	0	0
T1	737	8	0	0
T2	174488	1830	0	0
T3	21884	114	0	0
T4	79027	1576	0	0
T5	1613	19	0	0
T15	818	4	0	0
T19	486	4	0	0
T20	14243	221	0	0
T21	568374	41	0	0
T22	136999	333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1457227	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1457227	0	0
T1	737	5	0	0
T2	174488	616	0	0
T3	21884	233	0	0
T4	79027	9	0	0
T5	1613	18	0	0
T15	818	2	0	0
T19	486	7	0	0
T20	14243	154	0	0
T21	568374	209	0	0
T22	136999	2334	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3392770	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3392770	0	0
T1	737	5	0	0
T2	174488	757	0	0
T3	21884	176	0	0
T4	79027	544	0	0
T5	1613	18	0	0
T15	818	2	0	0
T19	486	7	0	0
T20	14243	164	0	0
T21	568374	138	0	0
T22	136999	802	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1444109	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1444109	0	0
T1	737	1	0	0
T2	174488	3659	0	0
T3	21884	164	0	0
T4	79027	5	0	0
T5	1613	21	0	0
T15	818	8	0	0
T19	486	9	0	0
T20	14243	100	0	0
T21	568374	137	0	0
T22	136999	1621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3734581	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3734581	0	0
T1	737	1	0	0
T2	174488	4581	0	0
T3	21884	198	0	0
T4	79027	889	0	0
T5	1613	21	0	0
T15	818	8	0	0
T19	486	9	0	0
T20	14243	90	0	0
T21	568374	33	0	0
T22	136999	370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1462454	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1462454	0	0
T1	737	12	0	0
T2	174488	2107	0	0
T3	21884	127	0	0
T4	79027	12	0	0
T5	1613	31	0	0
T15	818	6	0	0
T19	486	4	0	0
T20	14243	101	0	0
T21	568374	201	0	0
T22	136999	1836	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3873395	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3873395	0	0
T1	737	12	0	0
T2	174488	2065	0	0
T3	21884	160	0	0
T4	79027	389	0	0
T5	1613	31	0	0
T15	818	6	0	0
T19	486	4	0	0
T20	14243	101	0	0
T21	568374	48	0	0
T22	136999	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1485781	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1485781	0	0
T1	737	4	0	0
T2	174488	1955	0	0
T3	21884	160	0	0
T4	79027	15	0	0
T5	1613	18	0	0
T15	818	1	0	0
T19	486	5	0	0
T20	14243	80	0	0
T21	568374	187	0	0
T22	136999	3278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3493982	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3493982	0	0
T1	737	4	0	0
T2	174488	1427	0	0
T3	21884	121	0	0
T4	79027	562	0	0
T5	1613	18	0	0
T15	818	1	0	0
T19	486	5	0	0
T20	14243	106	0	0
T21	568374	41	0	0
T22	136999	1717	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1450637	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1450637	0	0
T1	737	7	0	0
T2	174488	3092	0	0
T3	21884	145	0	0
T4	79027	4	0	0
T5	1613	17	0	0
T15	818	7	0	0
T19	486	3	0	0
T20	14243	98	0	0
T21	568374	125	0	0
T22	136999	259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3288785	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3288785	0	0
T1	737	7	0	0
T2	174488	2370	0	0
T3	21884	136	0	0
T4	79027	559	0	0
T5	1613	17	0	0
T15	818	7	0	0
T19	486	3	0	0
T20	14243	116	0	0
T21	568374	356	0	0
T22	136999	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1436190	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1436190	0	0
T1	737	7	0	0
T2	174488	3604	0	0
T3	21884	148	0	0
T4	79027	21	0	0
T5	1613	26	0	0
T15	818	12	0	0
T19	486	1	0	0
T20	14243	178	0	0
T21	568374	186	0	0
T22	136999	1680	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	2960006	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	2960006	0	0
T1	737	7	0	0
T2	174488	2898	0	0
T3	21884	156	0	0
T4	79027	539	0	0
T5	1613	26	0	0
T15	818	12	0	0
T19	486	1	0	0
T20	14243	162	0	0
T21	568374	39	0	0
T22	136999	883	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1464116	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1464116	0	0
T1	737	5	0	0
T2	174488	872	0	0
T3	21884	204	0	0
T4	79027	1	0	0
T5	1613	18	0	0
T15	818	7	0	0
T19	486	2	0	0
T20	14243	136	0	0
T21	568374	235	0	0
T22	136999	2086	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3250930	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3250930	0	0
T1	737	5	0	0
T2	174488	873	0	0
T3	21884	120	0	0
T4	79027	132	0	0
T5	1613	18	0	0
T15	818	7	0	0
T19	486	2	0	0
T20	14243	135	0	0
T21	568374	851	0	0
T22	136999	834	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1509455	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1509455	0	0
T1	737	7	0	0
T2	174488	1924	0	0
T3	21884	141	0	0
T4	79027	18	0	0
T5	1613	31	0	0
T15	818	6	0	0
T19	486	5	0	0
T20	14243	130	0	0
T21	568374	235	0	0
T22	136999	1353	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3782846	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3782846	0	0
T1	737	7	0	0
T2	174488	1748	0	0
T3	21884	182	0	0
T4	79027	524	0	0
T5	1613	31	0	0
T15	818	6	0	0
T19	486	5	0	0
T20	14243	122	0	0
T21	568374	447	0	0
T22	136999	158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1473047	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1473047	0	0
T1	737	11	0	0
T2	174488	1524	0	0
T3	21884	91	0	0
T4	79027	7	0	0
T5	1613	34	0	0
T15	818	1	0	0
T19	486	6	0	0
T20	14243	128	0	0
T21	568374	220	0	0
T22	136999	2088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3313398	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3313398	0	0
T1	737	11	0	0
T2	174488	1046	0	0
T3	21884	119	0	0
T4	79027	216	0	0
T5	1613	34	0	0
T15	818	1	0	0
T19	486	6	0	0
T20	14243	190	0	0
T21	568374	46	0	0
T22	136999	1198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1490681	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1490681	0	0
T1	737	9	0	0
T2	174488	2798	0	0
T3	21884	164	0	0
T4	79027	6	0	0
T5	1613	24	0	0
T15	818	4	0	0
T19	486	1	0	0
T20	14243	152	0	0
T21	568374	191	0	0
T22	136999	1926	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3500474	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3500474	0	0
T1	737	9	0	0
T2	174488	4198	0	0
T3	21884	106	0	0
T4	79027	1395	0	0
T5	1613	24	0	0
T15	818	4	0	0
T19	486	1	0	0
T20	14243	179	0	0
T21	568374	43	0	0
T22	136999	448	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1478918	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1478918	0	0
T1	737	10	0	0
T2	174488	2183	0	0
T3	21884	239	0	0
T4	79027	11	0	0
T5	1613	29	0	0
T15	818	7	0	0
T19	486	8	0	0
T20	14243	175	0	0
T21	568374	156	0	0
T22	136999	1169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3253251	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3253251	0	0
T1	737	10	0	0
T2	174488	3258	0	0
T3	21884	229	0	0
T4	79027	750	0	0
T5	1613	29	0	0
T15	818	7	0	0
T19	486	8	0	0
T20	14243	153	0	0
T21	568374	39	0	0
T22	136999	686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1469373	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1469373	0	0
T1	737	5	0	0
T2	174488	597	0	0
T3	21884	148	0	0
T4	79027	16	0	0
T5	1613	22	0	0
T15	818	5	0	0
T19	486	3	0	0
T20	14243	172	0	0
T21	568374	185	0	0
T22	136999	2562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3123584	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3123584	0	0
T1	737	5	0	0
T2	174488	421	0	0
T3	21884	102	0	0
T4	79027	545	0	0
T5	1613	22	0	0
T15	818	5	0	0
T19	486	3	0	0
T20	14243	221	0	0
T21	568374	296	0	0
T22	136999	992	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1461811	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1461811	0	0
T1	737	8	0	0
T2	174488	798	0	0
T3	21884	123	0	0
T4	79027	20	0	0
T5	1613	27	0	0
T15	818	6	0	0
T19	486	4	0	0
T20	14243	179	0	0
T21	568374	210	0	0
T22	136999	2072	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	2607873	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	2607873	0	0
T1	737	8	0	0
T2	174488	946	0	0
T3	21884	102	0	0
T4	79027	1734	0	0
T5	1613	27	0	0
T15	818	6	0	0
T19	486	4	0	0
T20	14243	182	0	0
T21	568374	1202	0	0
T22	136999	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1427509	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1427509	0	0
T1	737	5	0	0
T2	174488	1016	0	0
T3	21884	103	0	0
T4	79027	30	0	0
T5	1613	24	0	0
T15	818	7	0	0
T19	486	5	0	0
T20	14243	181	0	0
T21	568374	215	0	0
T22	136999	190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	2797395	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	2797395	0	0
T1	737	5	0	0
T2	174488	1589	0	0
T3	21884	80	0	0
T4	79027	2313	0	0
T5	1613	24	0	0
T15	818	7	0	0
T19	486	5	0	0
T20	14243	137	0	0
T21	568374	50	0	0
T22	136999	447	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1496779	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1496779	0	0
T1	737	8	0	0
T2	174488	1066	0	0
T3	21884	190	0	0
T4	79027	10	0	0
T5	1613	20	0	0
T15	818	7	0	0
T19	486	1	0	0
T20	14243	141	0	0
T21	568374	147	0	0
T22	136999	1051	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3822802	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3822802	0	0
T1	737	8	0	0
T2	174488	2780	0	0
T3	21884	138	0	0
T4	79027	684	0	0
T5	1613	20	0	0
T15	818	7	0	0
T19	486	1	0	0
T20	14243	96	0	0
T21	568374	37	0	0
T22	136999	399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1490879	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1490879	0	0
T1	737	2	0	0
T2	174488	2296	0	0
T3	21884	147	0	0
T4	79027	21	0	0
T5	1613	28	0	0
T15	818	8	0	0
T19	486	2	0	0
T20	14243	170	0	0
T21	568374	172	0	0
T22	136999	931	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3110663	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3110663	0	0
T1	737	2	0	0
T2	174488	1357	0	0
T3	21884	184	0	0
T4	79027	861	0	0
T5	1613	28	0	0
T15	818	8	0	0
T19	486	2	0	0
T20	14243	211	0	0
T21	568374	487	0	0
T22	136999	687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	1487971	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	1487971	0	0
T1	737	4	0	0
T2	174488	660	0	0
T3	21884	106	0	0
T4	79027	37	0	0
T5	1613	23	0	0
T15	818	7	0	0
T19	486	6	0	0
T20	14243	70	0	0
T21	568374	208	0	0
T22	136999	1038	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314491122	3664628	0	0
DepthKnown_A	314491122	314358625	0	0
RvalidKnown_A	314491122	314358625	0	0
WreadyKnown_A	314491122	314358625	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	3664628	0	0
T1	737	4	0	0
T2	174488	773	0	0
T3	21884	29	0	0
T4	79027	1983	0	0
T5	1613	23	0	0
T15	818	7	0	0
T19	486	6	0	0
T20	14243	91	0	0
T21	568374	42	0	0
T22	136999	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314491122	314358625	0	0
T1	737	680	0	0
T2	174488	174473	0	0
T3	21884	21859	0	0
T4	79027	78993	0	0
T5	1613	1545	0	0
T15	818	747	0	0
T19	486	439	0	0
T20	14243	14237	0	0
T21	568374	568361	0	0
T22	136999	136963	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0