Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	210384871	0	0
DataKnown_AKnownEnable	2147483647	2147483647	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	210384871
T1	16016	496
T2	47152	615
T3	18592	702
T4	256760	7596
T5	462448	6944
T12	1548	332
T13	0	52
T16	313768	14151
T17	11549328	296768
T18	10593296	181078
T19	8619800	219690
T20	3000592	44510

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	17248	16464
T2	47152	41496
T3	18592	18200
T4	256760	254576
T5	462448	461272
T16	313768	313320
T17	11549328	11546584
T18	10593296	10591728
T19	8619800	8617280
T20	3000592	2996952

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	17248	16464
T2	47152	41496
T3	18592	18200
T4	256760	254576
T5	462448	461272
T16	313768	313320
T17	11549328	11546584
T18	10593296	10591728
T19	8619800	8617280
T20	3000592	2996952

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	17248	16464
T2	47152	41496
T3	18592	18200
T4	256760	254576
T5	462448	461272
T16	313768	313320
T17	11549328	11546584
T18	10593296	10591728
T19	8619800	8617280
T20	3000592	2996952

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	17248	16464
T2	47152	41496
T3	18592	18200
T4	256760	254576
T5	462448	461272
T16	313768	313320
T17	11549328	11546584
T18	10593296	10591728
T19	8619800	8617280
T20	3000592	2996952

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T16	56	56
T17	56	56
T18	56	56
T19	56	56
T20	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	80002108	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	80002108
T1	308	193
T2	842	240
T3	332	273
T4	4585	1921
T5	8258	3199
T16	5603	5515
T17	206238	122276
T18	189166	79888
T19	153925	96288
T20	53582	10913

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	52236521	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	52236521
T1	308	101
T2	842	125
T3	332	143
T4	4585	1877
T5	8258	1086
T16	5603	2882
T17	206238	60199
T18	189166	21794
T19	153925	43962
T20	53582	11349

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1027078	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1027078
T1	308	3
T2	842	3
T3	332	5
T4	4585	0
T5	8258	34
T12	0	10
T16	5603	112
T17	206238	3322
T18	189166	3553
T19	153925	2496
T20	53582	339

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1966623	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1966623
T1	308	3
T2	842	3
T3	332	5
T4	4585	0
T5	8258	11
T12	0	10
T16	5603	112
T17	206238	2044
T18	189166	394
T19	153925	1037
T20	53582	392

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	993271	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	993271
T1	308	2
T2	842	8
T3	332	6
T4	4585	0
T5	8258	93
T12	0	9
T16	5603	97
T17	206238	2328
T18	189166	2674
T19	153925	1027
T20	53582	359

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2403272	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2403272
T1	308	2
T2	842	8
T3	332	6
T4	4585	0
T5	8258	22
T12	0	9
T16	5603	97
T17	206238	2302
T18	189166	1427
T19	153925	1547
T20	53582	400

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	965210	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	965210
T1	308	7
T2	842	6
T3	332	6
T4	4585	0
T5	8258	136
T12	0	5
T16	5603	111
T17	206238	1238
T18	189166	849
T19	153925	2055
T20	53582	328

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2134723	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2134723
T1	308	7
T2	842	6
T3	332	6
T4	4585	0
T5	8258	39
T12	0	5
T16	5603	111
T17	206238	1077
T18	189166	92
T19	153925	1999
T20	53582	321

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1043680	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1043680
T1	308	3
T2	842	6
T3	332	2
T4	4585	0
T5	8258	69
T12	0	5
T16	5603	108
T17	206238	1677
T18	189166	2318
T19	153925	1726
T20	53582	348

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1788026	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1788026
T1	308	3
T2	842	6
T3	332	2
T4	4585	0
T5	8258	46
T12	0	5
T16	5603	108
T17	206238	2564
T18	189166	1305
T19	153925	2620
T20	53582	338

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	976140	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	976140
T2	842	5
T3	332	4
T4	4585	0
T5	8258	67
T12	387	6
T13	0	11
T16	5603	94
T17	206238	1765
T18	189166	2355
T19	153925	1148
T20	53582	416

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T5 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1483147	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1483147
T2	842	5
T3	332	4
T4	4585	0
T5	8258	11
T12	387	6
T13	0	11
T16	5603	94
T17	206238	2946
T18	189166	235
T19	153925	884
T20	53582	426

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1028717	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1028717
T1	308	3
T2	842	10
T3	332	10
T4	4585	0
T5	8258	73
T12	0	8
T16	5603	113
T17	206238	1883
T18	189166	4302
T19	153925	528
T20	53582	359

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1990576	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1990576
T1	308	3
T2	842	10
T3	332	10
T4	4585	0
T5	8258	62
T12	0	8
T16	5603	113
T17	206238	3127
T18	189166	1927
T19	153925	718
T20	53582	396

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1014455	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1014455
T1	308	2
T2	842	0
T3	332	6
T4	4585	0
T5	8258	73
T12	0	8
T13	0	10
T16	5603	106
T17	206238	2361
T18	189166	4176
T19	153925	2842
T20	53582	437

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T3 T5 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T3 T5 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2090462	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2090462
T1	308	2
T2	842	0
T3	332	6
T4	4585	0
T5	8258	41
T12	0	8
T13	0	10
T16	5603	106
T17	206238	2396
T18	189166	1837
T19	153925	2699
T20	53582	529

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	988878	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	988878
T1	308	5
T2	842	2
T3	332	10
T4	4585	0
T5	8258	37
T12	0	7
T16	5603	102
T17	206238	1738
T18	189166	383
T19	153925	1367
T20	53582	472

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1859709	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1859709
T1	308	5
T2	842	2
T3	332	10
T4	4585	0
T5	8258	19
T12	0	7
T16	5603	102
T17	206238	1907
T18	189166	483
T19	153925	1280
T20	53582	438

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	966392	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	966392
T1	308	6
T2	842	4
T3	332	4
T4	4585	1921
T5	8258	76
T16	5603	107
T17	206238	2095
T18	189166	434
T19	153925	698
T20	53582	347

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1613981	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1613981
T1	308	6
T2	842	4
T3	332	4
T4	4585	1877
T5	8258	44
T16	5603	107
T17	206238	2797
T18	189166	621
T19	153925	2545
T20	53582	329

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	979770	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	979770
T1	308	5
T2	842	2
T3	332	5
T4	4585	0
T5	8258	63
T12	0	11
T16	5603	133
T17	206238	2711
T18	189166	2833
T19	153925	2212
T20	53582	463

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1775950	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1775950
T1	308	5
T2	842	2
T3	332	5
T4	4585	0
T5	8258	20
T12	0	11
T16	5603	133
T17	206238	2499
T18	189166	560
T19	153925	3505
T20	53582	495

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1004402	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1004402
T1	308	4
T2	842	2
T3	332	5
T4	4585	0
T5	8258	80
T12	0	5
T16	5603	103
T17	206238	2226
T18	189166	2126
T19	153925	505
T20	53582	443

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1612414	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1612414
T1	308	4
T2	842	2
T3	332	5
T4	4585	0
T5	8258	39
T12	0	5
T16	5603	103
T17	206238	2034
T18	189166	491
T19	153925	951
T20	53582	408

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	990059	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	990059
T1	308	7
T2	842	4
T3	332	5
T4	4585	0
T5	8258	30
T12	0	8
T16	5603	126
T17	206238	401
T18	189166	1595
T19	153925	2022
T20	53582	429

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1655652	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1655652
T1	308	7
T2	842	4
T3	332	5
T4	4585	0
T5	8258	27
T12	0	8
T16	5603	126
T17	206238	698
T18	189166	528
T19	153925	2115
T20	53582	381

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	978567	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	978567
T1	308	8
T2	842	3
T3	332	5
T4	4585	0
T5	8258	70
T12	0	5
T16	5603	113
T17	206238	1560
T18	189166	1643
T19	153925	1826
T20	53582	329

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2074911	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2074911
T1	308	8
T2	842	3
T3	332	5
T4	4585	0
T5	8258	24
T12	0	5
T16	5603	113
T17	206238	2572
T18	189166	253
T19	153925	2400
T20	53582	369

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1025203	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1025203
T1	308	1
T2	842	3
T3	332	2
T4	4585	0
T5	8258	83
T12	0	11
T16	5603	95
T17	206238	969
T18	189166	3073
T19	153925	814
T20	53582	400

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2034301	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2034301
T1	308	1
T2	842	3
T3	332	2
T4	4585	0
T5	8258	55
T12	0	11
T16	5603	95
T17	206238	754
T18	189166	1319
T19	153925	1965
T20	53582	471

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	977806	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	977806
T1	308	3
T2	842	3
T3	332	4
T4	4585	0
T5	8258	39
T12	0	4
T16	5603	111
T17	206238	3938
T18	189166	2121
T19	153925	2210
T20	53582	384

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1469918	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1469918
T1	308	3
T2	842	3
T3	332	4
T4	4585	0
T5	8258	24
T12	0	4
T16	5603	111
T17	206238	2863
T18	189166	1848
T19	153925	2026
T20	53582	411

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1034557	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1034557
T1	308	4
T2	842	6
T3	332	6
T4	4585	0
T5	8258	47
T12	0	6
T16	5603	105
T17	206238	2805
T18	189166	1522
T19	153925	691
T20	53582	351

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1615903	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1615903
T1	308	4
T2	842	6
T3	332	6
T4	4585	0
T5	8258	16
T12	0	6
T16	5603	105
T17	206238	2013
T18	189166	374
T19	153925	396
T20	53582	327

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	960030	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	960030
T1	308	3
T2	842	6
T3	332	4
T4	4585	0
T5	8258	121
T12	0	8
T16	5603	99
T17	206238	3479
T18	189166	1643
T19	153925	748
T20	53582	433

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1847277	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1847277
T1	308	3
T2	842	6
T3	332	4
T4	4585	0
T5	8258	14
T12	0	8
T16	5603	99
T17	206238	4150
T18	189166	593
T19	153925	1654
T20	53582	451

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1003476	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1003476
T1	308	2
T2	842	5
T3	332	6
T4	4585	0
T5	8258	40
T12	0	5
T16	5603	95
T17	206238	2621
T18	189166	2945
T19	153925	532
T20	53582	410

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1772693	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1772693
T1	308	2
T2	842	5
T3	332	6
T4	4585	0
T5	8258	15
T12	0	5
T16	5603	95
T17	206238	2855
T18	189166	1165
T19	153925	795
T20	53582	502

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1004788	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1004788
T1	308	3
T2	842	4
T3	332	6
T4	4585	0
T5	8258	36
T12	0	6
T16	5603	107
T17	206238	1889
T18	189166	1903
T19	153925	877
T20	53582	445

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2120000	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2120000
T1	308	3
T2	842	4
T3	332	6
T4	4585	0
T5	8258	17
T12	0	6
T16	5603	107
T17	206238	1343
T18	189166	899
T19	153925	2197
T20	53582	401

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	965328	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	965328
T1	308	5
T2	842	10
T3	332	7
T4	4585	0
T5	8258	63
T12	0	2
T16	5603	104
T17	206238	1135
T18	189166	1629
T19	153925	1521
T20	53582	427

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1521093	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1521093
T1	308	5
T2	842	10
T3	332	7
T4	4585	0
T5	8258	59
T12	0	2
T16	5603	104
T17	206238	1017
T18	189166	596
T19	153925	1775
T20	53582	469

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	982172	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	982172
T1	308	5
T2	842	5
T3	332	6
T4	4585	0
T5	8258	67
T12	0	4
T16	5603	100
T17	206238	513
T18	189166	2092
T19	153925	139
T20	53582	474

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1848153	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1848153
T1	308	5
T2	842	5
T3	332	6
T4	4585	0
T5	8258	33
T12	0	4
T16	5603	100
T17	206238	907
T18	189166	919
T19	153925	340
T20	53582	569

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1008742	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1008742
T2	842	5
T3	332	4
T4	4585	0
T5	8258	79
T12	387	1
T13	0	5
T16	5603	95
T17	206238	461
T18	189166	2425
T19	153925	3530
T20	53582	411

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T5 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1989151	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1989151
T2	842	5
T3	332	4
T4	4585	0
T5	8258	32
T12	387	1
T13	0	5
T16	5603	95
T17	206238	1127
T18	189166	860
T19	153925	1835
T20	53582	414

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1014250	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1014250
T1	308	1
T2	842	6
T3	332	4
T4	4585	0
T5	8258	71
T12	0	3
T16	5603	117
T17	206238	1844
T18	189166	2210
T19	153925	1126
T20	53582	365

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2095641	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2095641
T1	308	1
T2	842	6
T3	332	4
T4	4585	0
T5	8258	62
T12	0	3
T16	5603	117
T17	206238	2745
T18	189166	468
T19	153925	1089
T20	53582	305

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1005313	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1005313
T1	308	6
T2	842	1
T3	332	6
T4	4585	0
T5	8258	41
T12	0	8
T16	5603	101
T17	206238	2174
T18	189166	2944
T19	153925	1339
T20	53582	442

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2341700	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2341700
T1	308	6
T2	842	1
T3	332	6
T4	4585	0
T5	8258	24
T12	0	8
T16	5603	101
T17	206238	1903
T18	189166	862
T19	153925	2418
T20	53582	424

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1007079	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1007079
T1	308	2
T2	842	5
T3	332	6
T4	4585	0
T5	8258	73
T12	0	9
T16	5603	135
T17	206238	1129
T18	189166	322
T19	153925	151
T20	53582	488

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2144871	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2144871
T1	308	2
T2	842	5
T3	332	6
T4	4585	0
T5	8258	66
T12	0	9
T16	5603	135
T17	206238	2381
T18	189166	326
T19	153925	740
T20	53582	382

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	978118	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	978118
T1	308	6
T2	842	2
T3	332	5
T4	4585	0
T5	8258	60
T12	0	5
T16	5603	89
T17	206238	2648
T18	189166	1225
T19	153925	992
T20	53582	327

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	2161891	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	2161891
T1	308	6
T2	842	2
T3	332	5
T4	4585	0
T5	8258	9
T12	0	5
T16	5603	89
T17	206238	3365
T18	189166	826
T19	153925	1665
T20	53582	432

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	988025	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	988025
T1	308	5
T2	842	9
T3	332	4
T4	4585	0
T5	8258	89
T12	0	7
T16	5603	99
T17	206238	3614
T18	189166	2307
T19	153925	356
T20	53582	480

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183670821	1822698	0	0
DataKnown_AKnownEnable	183670821	183545320	0	0
DepthKnown_A	183670821	183545320	0	0
RvalidKnown_A	183670821	183545320	0	0
WreadyKnown_A	183670821	183545320	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	183670821	1822698
T1	308	5
T2	842	9
T3	332	4
T4	4585	0
T5	8258	18
T12	0	7
T16	5603	99
T17	206238	3383
T18	189166	586
T19	153925	767
T20	53582	562

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

DepthKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

RvalidKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

WreadyKnown_A

Name	Attempts	Real Successes
Total	183670821	183545320
T1	308	294
T2	842	741
T3	332	325
T4	4585	4546
T5	8258	8237
T16	5603	5595
T17	206238	206189
T18	189166	189138
T19	153925	153880
T20	53582	53517

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T19	1	1
T20	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children