Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer.u_state_regs	100.00	100.00					100.00
tb.dut.gen_classes[0].u_esc_timer.u_state_regs	100.00	100.00					100.00
tb.dut.gen_classes[1].u_esc_timer.u_state_regs	100.00	100.00					100.00
tb.dut.gen_classes[2].u_esc_timer.u_state_regs	100.00	100.00					100.00
tb.dut.gen_classes[3].u_esc_timer.u_state_regs	100.00	100.00					100.00

---

Module Instance : tb.dut.u_ping_timer.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.30		100.00	100.00	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.08	94.06	93.33		85.71	92.31	100.00	gen_classes[0].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.36	88.12	88.89		71.43	84.62	93.75	gen_classes[1].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.29	91.09	93.33		78.57	88.46	100.00	gen_classes[2].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	88.12	93.33		71.43	84.62	100.00	gen_classes[3].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Module : prim_sparse_fsm_flop

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	3225	3225	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3225	3225	0	0
T17	5	5	0	0
T18	5	5	0	0
T19	5	5	0	0
T23	5	5	0	0
T24	5	5	0	0
T29	5	5	0	0
T30	5	5	0	0
T32	5	5	0	0
T35	5	5	0	0
T57	5	5	0	0

Line Coverage for Instance : tb.dut.u_ping_timer.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_ping_timer.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	645	645	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	645	645	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	645	645	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	645	645	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	645	645	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0