Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.15	94.06	89.36		60.00	92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	85.36	88.12	88.89		71.43	84.62	93.75
tb.dut.gen_classes[3].u_esc_timer	87.50	88.12	93.33		71.43	84.62	100.00
tb.dut.gen_classes[2].u_esc_timer	90.29	91.09	93.33		78.57	88.46	100.00
tb.dut.gen_classes[0].u_esc_timer	93.08	94.06	93.33		85.71	92.31	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.36	88.12	88.89		71.43	84.62	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.21	89.09	88.89	100.00	71.43	85.71	94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	88.12	93.33		71.43	84.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.93	89.09	93.33	100.00	71.43	85.71	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.29	91.09	93.33		78.57	88.46	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.17	91.82	93.33	100.00	78.57	89.29	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.08	94.06	93.33		85.71	92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.41	94.55	93.33	100.00	85.71	92.86	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	95	94.06
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	83	93.26
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	0	1
189	0	1
190	0	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	0	1
224	0	1
225	0	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T19

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T19

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T18,T23

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T19,T23
1	0	1	Covered	T17,T18,T23
1	1	0	Covered	T17,T19,T23
1	1	1	Covered	T17,T19,T24

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T24
0	1	Covered	T17,T25,T26
1	0	Covered	T17,T27,T28

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T19,T24
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T27,T28

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T24
1	0	Not Covered
1	1	Covered	T17,T25,T26

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T23
1	Covered	T17,T23,T29

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T23,T29
1	Covered	T17,T18,T23

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T23
1	Covered	T17,T30,T31

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T23
1	Covered	T17,T27,T31

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T32

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T30,T33

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T23

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T23

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	12	60.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T34
IdleSt	175	Covered	T34
Phase0St	146	Covered	T34
Phase1St	192	Covered	T34
Phase2St	209	Covered	T34
Phase3St	227	Covered	T34
TerminalSt	243	Covered	T34
TimeoutSt	153	Covered	T34

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T34
IdleSt->Phase0St	146	Covered	T34
IdleSt->TimeoutSt	153	Covered	T34
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Not Covered
Phase0St->Phase1St	192	Covered	T34
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T34
Phase1St->Phase2St	209	Covered	T34
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Not Covered
Phase2St->Phase3St	227	Covered	T34
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T34
Phase3St->TerminalSt	243	Covered	T34
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T34
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T34
TimeoutSt->Phase0St	166	Covered	T34

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
CASE	138	22	20	90.91
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T23
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T27,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T18,T23
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T18,T23
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T29,T35
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T18,T23
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T18,T23
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T18,T23
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T18,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T25,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T18,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T23,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T23,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T18,T23
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1410	0	0
CheckAccumTrig0_A	2147483647	3970	0	0
CheckAccumTrig1_A	2147483647	350	0	0
CheckClr_A	2147483647	1550	0	0
CheckEn_A	2147483647	1046532950	0	0
CheckPhase0_A	2147483647	4720	0	0
CheckPhase1_A	2147483647	4520	0	0
CheckPhase2_A	2147483647	4520	0	0
CheckPhase3_A	2147483647	4420	0	0
CheckTimeout0_A	2147483647	12700	0	0
CheckTimeoutSt1_A	2147483647	1626050	0	0
CheckTimeoutSt2_A	2147483647	11950	0	0
CheckTimeoutStTrig_A	2147483647	400	0	0
ErrorStAllEscAsserted_A	2147483647	7380	0	0
ErrorStIsTerminal_A	2147483647	6180	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1410	0	0
T20	165948	282	0	0
T21	0	282	0	0
T22	0	282	0	0
T36	0	282	0	0
T37	0	282	0	0
T38	1307092	0	0	0
T39	1307092	0	0	0
T40	325356	0	0	0
T41	313540	0	0	0
T42	325356	0	0	0
T43	690456	0	0	0
T44	313540	0	0	0
T45	1307092	0	0	0
T46	1078772	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3970	0	0
T17	1789012	11	0	0
T18	3869304	1	0	0
T19	324608	0	0	0
T23	313540	4	0	0
T24	324608	0	0	0
T25	0	3	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	313540	4	0	0
T30	1307092	3	0	0
T31	0	3	0	0
T32	3869304	1	0	0
T35	313540	4	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	4	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	325356	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350	0	0
T17	1341759	3	0	0
T18	2901978	0	0	0
T19	243456	0	0	0
T23	235155	0	0	0
T24	243456	0	0	0
T25	0	3	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	235155	0	0	0
T30	980319	0	0	0
T32	2901978	0	0	0
T35	235155	0	0	0
T57	244017	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	3	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1550	0	0
T17	447253	3	0	0
T23	156770	3	0	0
T24	162304	0	0	0
T25	447253	0	0	0
T29	156770	3	0	0
T30	653546	0	0	0
T32	1934652	0	0	0
T33	2783	0	0	0
T35	156770	3	0	0
T47	967326	0	0	0
T48	78385	3	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	2	0	0
T54	391717	0	0	0
T55	391717	0	0	0
T56	70654	2	0	0
T57	162678	0	0	0
T58	72311	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T72	87292	1	0	0
T73	78385	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	78385	0	0	0
T81	87292	0	0	0
T82	967326	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1046532950	0	0
T17	1789012	899642	0	0
T18	3869304	2686362	0	0
T19	324608	161122	0	0
T23	313540	240579	0	0
T24	324608	161122	0	0
T29	313540	240579	0	0
T30	1307092	64614	0	0
T32	3869304	2686362	0	0
T35	313540	240579	0	0
T57	325356	9265	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4720	0	0
T17	1789012	18	0	0
T18	3869304	1	0	0
T19	324608	0	0	0
T23	313540	4	0	0
T24	324608	0	0	0
T25	0	6	0	0
T27	0	4	0	0
T28	0	3	0	0
T29	313540	4	0	0
T30	1307092	3	0	0
T31	0	3	0	0
T32	3869304	1	0	0
T35	313540	4	0	0
T47	0	1	0	0
T48	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	325356	0	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4520	0	0
T17	1789012	18	0	0
T18	3869304	1	0	0
T19	324608	0	0	0
T23	313540	2	0	0
T24	324608	0	0	0
T25	0	6	0	0
T27	0	4	0	0
T28	0	3	0	0
T29	313540	2	0	0
T30	1307092	3	0	0
T31	0	3	0	0
T32	3869304	1	0	0
T35	313540	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	325356	0	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4520	0	0
T17	1789012	18	0	0
T18	3869304	1	0	0
T19	324608	0	0	0
T23	313540	2	0	0
T24	324608	0	0	0
T25	0	6	0	0
T27	0	4	0	0
T28	0	3	0	0
T29	313540	2	0	0
T30	1307092	3	0	0
T31	0	3	0	0
T32	3869304	1	0	0
T35	313540	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	325356	0	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4420	0	0
T17	1789012	17	0	0
T18	3869304	1	0	0
T19	324608	0	0	0
T23	313540	2	0	0
T24	324608	0	0	0
T25	0	5	0	0
T27	0	4	0	0
T28	0	3	0	0
T29	313540	2	0	0
T30	1307092	3	0	0
T31	0	3	0	0
T32	3869304	1	0	0
T35	313540	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	325356	0	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12700	0	0
T17	1789012	105	0	0
T18	3869304	0	0	0
T19	324608	7	0	0
T23	313540	0	0	0
T24	324608	7	0	0
T25	0	105	0	0
T26	0	10	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	313540	0	0	0
T30	1307092	0	0	0
T32	3869304	0	0	0
T35	313540	0	0	0
T50	0	1	0	0
T57	325356	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	87	0	0
T61	0	1	0	0
T63	0	80	0	0
T64	0	80	0	0
T65	0	1	0	0
T67	0	80	0	0
T68	0	80	0	0
T69	0	80	0	0
T72	0	1	0	0
T81	0	1	0	0
T83	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1626050	0	0
T17	1789012	14197	0	0
T18	3869304	0	0	0
T19	324608	1070	0	0
T23	313540	0	0	0
T24	324608	1070	0	0
T25	0	14197	0	0
T26	0	962	0	0
T27	0	8	0	0
T28	0	8	0	0
T29	313540	0	0	0
T30	1307092	0	0	0
T32	3869304	0	0	0
T35	313540	0	0	0
T50	0	114	0	0
T57	325356	0	0	0
T58	0	3	0	0
T59	0	3	0	0
T60	0	10170	0	0
T61	0	3	0	0
T63	0	9335	0	0
T64	0	9335	0	0
T65	0	30	0	0
T67	0	9335	0	0
T68	0	9335	0	0
T69	0	9335	0	0
T72	0	114	0	0
T81	0	114	0	0
T83	0	1070	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11950	0	0
T17	1789012	132	0	0
T18	3869304	0	0	0
T19	324608	18	0	0
T23	313540	0	0	0
T24	324608	18	0	0
T25	0	132	0	0
T26	0	87	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	313540	0	0	0
T30	1307092	0	0	0
T32	3869304	0	0	0
T35	313540	0	0	0
T50	0	1	0	0
T57	325356	0	0	0
T60	0	117	0	0
T63	0	117	0	0
T64	0	83	0	0
T65	0	10	0	0
T67	0	83	0	0
T68	0	83	0	0
T69	0	83	0	0
T72	0	1	0	0
T81	0	1	0	0
T83	0	18	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	400	0	0
T17	1789012	7	0	0
T18	3869304	0	0	0
T19	324608	0	0	0
T23	313540	0	0	0
T24	324608	0	0	0
T25	0	7	0	0
T26	0	1	0	0
T29	313540	0	0	0
T30	1307092	0	0	0
T32	3869304	0	0	0
T35	313540	0	0	0
T57	325356	0	0	0
T60	0	7	0	0
T63	0	7	0	0
T64	0	7	0	0
T65	0	1	0	0
T67	0	7	0	0
T68	0	7	0	0
T69	0	7	0	0
T70	0	5	0	0
T71	0	5	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7380	0	0
T20	165948	1476	0	0
T21	0	1476	0	0
T22	0	1476	0	0
T36	0	1476	0	0
T37	0	1476	0	0
T38	1307092	0	0	0
T39	1307092	0	0	0
T40	325356	0	0	0
T41	313540	0	0	0
T42	325356	0	0	0
T43	690456	0	0	0
T44	313540	0	0	0
T45	1307092	0	0	0
T46	1078772	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6180	0	0
T20	165948	1236	0	0
T21	0	1236	0	0
T22	0	1236	0	0
T36	0	1236	0	0
T37	0	1236	0	0
T38	1307092	0	0	0
T39	1307092	0	0	0
T40	325356	0	0	0
T41	313540	0	0	0
T42	325356	0	0	0
T43	690456	0	0	0
T44	313540	0	0	0
T45	1307092	0	0	0
T46	1078772	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T17	1789012	1788964	0	0
T18	3869304	3869064	0	0
T19	324608	324368	0	0
T23	313540	313300	0	0
T24	324608	324368	0	0
T29	313540	313300	0	0
T30	1307092	1307068	0	0
T32	3869304	3869064	0	0
T35	313540	313300	0	0
T57	325356	324772	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	89	88.12
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	77	86.52
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	0	1
189	0	1
190	0	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	0	1
206	0	1
207	0	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	0	1
224	0	1
225	0	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	0	1
240	0	1
241	0	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	40	88.89
Logical	45	40	88.89
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T57
1	1	Covered	T17,T18,T19

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T32
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T57

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T18,T57

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T19,T24
1	0	1	Covered	T17,T18,T32
1	1	0	Covered	T17,T19,T24
1	1	1	Covered	T17,T25,T26

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T25,T26
0	1	Covered	T17,T25,T60
1	0	Not Covered

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T25,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T26
1	0	Not Covered
1	1	Covered	T17,T25,T60

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T32
1	Covered	T26,T65,T85

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T30,T31,T53
1	Covered	T17,T18,T32

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T32
1	Covered	T30,T31,T53

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T32
1	Covered	T58,T26,T59

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T32

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T27,T31

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T32

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T18,T32

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	10	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T34
IdleSt	175	Covered	T34
Phase0St	146	Covered	T34
Phase1St	192	Covered	T34
Phase2St	209	Covered	T34
Phase3St	227	Covered	T34
TerminalSt	243	Covered	T34
TimeoutSt	153	Covered	T34

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T34
IdleSt->Phase0St	146	Covered	T34
IdleSt->TimeoutSt	153	Covered	T34
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Not Covered
Phase0St->Phase1St	192	Covered	T34
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Not Covered
Phase1St->Phase2St	209	Covered	T34
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Not Covered
Phase2St->Phase3St	227	Covered	T34
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Not Covered
Phase3St->TerminalSt	243	Covered	T34
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T34
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T34
TimeoutSt->Phase0St	166	Covered	T34

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	22	84.62
CASE	138	22	18	81.82
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T57
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T18,T32
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T18,T32
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T18,T32
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T18,T32
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T18,T32
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T18,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T18,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T30,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T58,T59,T61
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T18,T32
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	874973625	380	0	0
CheckAccumTrig0_A	874973625	600	0	0
CheckAccumTrig1_A	874973625	0	0	0
CheckClr_A	874973625	50	0	0
CheckEn_A	874767930	188358145	0	0
CheckPhase0_A	874973625	650	0	0
CheckPhase1_A	874973625	650	0	0
CheckPhase2_A	874973625	650	0	0
CheckPhase3_A	874973625	650	0	0
CheckTimeout0_A	874973625	4050	0	0
CheckTimeoutSt1_A	874973625	468250	0	0
CheckTimeoutSt2_A	874973625	4000	0	0
CheckTimeoutStTrig_A	874973625	50	0	0
ErrorStAllEscAsserted_A	874973625	1800	0	0
ErrorStIsTerminal_A	874973625	1500	0	0
u_state_regs_A	874973625	874766355	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	380	0	0
T20	41487	76	0	0
T21	0	76	0	0
T22	0	76	0	0
T36	0	76	0	0
T37	0	76	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	600	0	0
T17	447253	2	0	0
T18	967326	1	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	1	0	0
T35	78385	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T57	81339	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	50	0	0
T25	447253	0	0	0
T54	391717	0	0	0
T55	391717	0	0	0
T56	70654	0	0	0
T58	72311	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T72	87292	0	0	0
T73	78385	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	78385	0	0	0
T81	87292	0	0	0
T82	967326	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874767930	188358145	0	0
T17	447253	233456	0	0
T18	967326	2020	0	0
T19	81152	72373	0	0
T23	78385	78324	0	0
T24	81152	72373	0	0
T29	78385	78324	0	0
T30	326773	8214	0	0
T32	967326	2020	0	0
T35	78385	78324	0	0
T57	81339	2305	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	650	0	0
T17	447253	3	0	0
T18	967326	1	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	1	0	0
T35	78385	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T57	81339	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	650	0	0
T17	447253	3	0	0
T18	967326	1	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	1	0	0
T35	78385	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T57	81339	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	650	0	0
T17	447253	3	0	0
T18	967326	1	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	1	0	0
T35	78385	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T57	81339	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	650	0	0
T17	447253	3	0	0
T18	967326	1	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	1	0	0
T35	78385	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T57	81339	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	4050	0	0
T17	447253	80	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	80	0	0
T26	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	80	0	0
T63	0	80	0	0
T64	0	80	0	0
T65	0	1	0	0
T67	0	80	0	0
T68	0	80	0	0
T69	0	80	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	468250	0	0
T17	447253	9335	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	9335	0	0
T26	0	30	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	9335	0	0
T63	0	9335	0	0
T64	0	9335	0	0
T65	0	30	0	0
T67	0	9335	0	0
T68	0	9335	0	0
T69	0	9335	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	4000	0	0
T17	447253	79	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	79	0	0
T26	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	79	0	0
T63	0	79	0	0
T64	0	79	0	0
T65	0	1	0	0
T67	0	79	0	0
T68	0	79	0	0
T69	0	79	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	50	0	0
T17	447253	1	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1800	0	0
T20	41487	360	0	0
T21	0	360	0	0
T22	0	360	0	0
T36	0	360	0	0
T37	0	360	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1500	0	0
T20	41487	300	0	0
T21	0	300	0	0
T22	0	300	0	0
T36	0	300	0	0
T37	0	300	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	89	88.12
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	77	86.52
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	0	1
189	0	1
190	0	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	0	1
206	0	1
207	0	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	0	1
224	0	1
225	0	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	0	1
240	0	1
241	0	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T19,T24
1	1	Covered	T17,T18,T19

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T24
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T19,T24

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T19,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T30,T33

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T19,T24
1	0	1	Covered	T17,T30,T33
1	1	0	Covered	T17,T25,T26
1	1	1	Covered	T17,T19,T24

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T24
0	1	Covered	T17,T25,T60
1	0	Covered	T17,T25,T60

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T19,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T25,T60

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T24
1	0	Not Covered
1	1	Covered	T17,T25,T60

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T30,T27
1	Covered	T17,T33,T25

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T30,T33
1	Covered	T17,T27,T28

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T33,T27
1	Covered	T30,T26,T86

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T30,T33
1	Covered	T17,T31,T52

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T33,T52

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T30,T33

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T33,T31

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T33,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	10	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T34
IdleSt	175	Covered	T34
Phase0St	146	Covered	T34
Phase1St	192	Covered	T34
Phase2St	209	Covered	T34
Phase3St	227	Covered	T34
TerminalSt	243	Covered	T34
TimeoutSt	153	Covered	T34

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T34
IdleSt->Phase0St	146	Covered	T34
IdleSt->TimeoutSt	153	Covered	T34
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Not Covered
Phase0St->Phase1St	192	Covered	T34
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Not Covered
Phase1St->Phase2St	209	Covered	T34
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Not Covered
Phase2St->Phase3St	227	Covered	T34
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Not Covered
Phase3St->TerminalSt	243	Covered	T34
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T34
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T34
TimeoutSt->Phase0St	166	Covered	T34

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	22	84.62
CASE	138	22	18	81.82
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T30,T33
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T30,T33
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T30,T27
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T30,T33
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T30,T27
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T30,T33
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T30,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T30,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T30,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T52,T58,T56
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T30,T33
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	874973625	290	0	0
CheckAccumTrig0_A	874973625	1070	0	0
CheckAccumTrig1_A	874973625	50	0	0
CheckClr_A	874973625	450	0	0
CheckEn_A	874767930	313069475	0	0
CheckPhase0_A	874973625	1220	0	0
CheckPhase1_A	874973625	1220	0	0
CheckPhase2_A	874973625	1220	0	0
CheckPhase3_A	874973625	1220	0	0
CheckTimeout0_A	874973625	4700	0	0
CheckTimeoutSt1_A	874973625	694400	0	0
CheckTimeoutSt2_A	874973625	4550	0	0
CheckTimeoutStTrig_A	874973625	100	0	0
ErrorStAllEscAsserted_A	874973625	1750	0	0
ErrorStIsTerminal_A	874973625	1450	0	0
u_state_regs_A	874973625	874766355	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	290	0	0
T20	41487	58	0	0
T21	0	58	0	0
T22	0	58	0	0
T36	0	58	0	0
T37	0	58	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1070	0	0
T17	447253	2	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T33	0	1	0	0
T35	78385	0	0	0
T52	0	4	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	50	0	0
T17	447253	1	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	450	0	0
T25	447253	0	0	0
T26	0	4	0	0
T52	70654	3	0	0
T53	269693	0	0	0
T54	391717	0	0	0
T55	391717	0	0	0
T56	70654	3	0	0
T58	72311	2	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T65	0	4	0	0
T72	87292	0	0	0
T73	78385	0	0	0
T74	0	2	0	0
T80	78385	0	0	0
T87	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874767930	313069475	0	0
T17	447253	180548	0	0
T18	967326	967265	0	0
T19	81152	2054	0	0
T23	78385	78324	0	0
T24	81152	2054	0	0
T29	78385	78324	0	0
T30	326773	29307	0	0
T32	967326	967265	0	0
T35	78385	78324	0	0
T57	81339	2339	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1220	0	0
T17	447253	5	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T33	0	1	0	0
T35	78385	0	0	0
T52	0	4	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1220	0	0
T17	447253	5	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T33	0	1	0	0
T35	78385	0	0	0
T52	0	4	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1220	0	0
T17	447253	5	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T33	0	1	0	0
T35	78385	0	0	0
T52	0	4	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1220	0	0
T17	447253	5	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T33	0	1	0	0
T35	78385	0	0	0
T52	0	4	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	4700	0	0
T17	447253	37	0	0
T18	967326	0	0	0
T19	81152	11	0	0
T23	78385	0	0	0
T24	81152	11	0	0
T25	0	37	0	0
T26	0	45	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	37	0	0
T63	0	37	0	0
T83	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	694400	0	0
T17	447253	7038	0	0
T18	967326	0	0	0
T19	81152	1524	0	0
T23	78385	0	0	0
T24	81152	1524	0	0
T25	0	7038	0	0
T26	0	5193	0	0
T27	0	133	0	0
T28	0	133	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	7038	0	0
T63	0	7038	0	0
T83	0	1524	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	4550	0	0
T17	447253	34	0	0
T18	967326	0	0	0
T19	81152	11	0	0
T23	78385	0	0	0
T24	81152	11	0	0
T25	0	34	0	0
T26	0	45	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	34	0	0
T63	0	34	0	0
T83	0	11	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	100	0	0
T17	447253	2	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	2	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	2	0	0
T63	0	2	0	0
T64	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1750	0	0
T20	41487	350	0	0
T21	0	350	0	0
T22	0	350	0	0
T36	0	350	0	0
T37	0	350	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1450	0	0
T20	41487	290	0	0
T21	0	290	0	0
T22	0	290	0	0
T36	0	290	0	0
T37	0	290	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	92	91.09
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	80	89.89
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	0	1
189	0	1
190	0	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	0	1
206	0	1
207	0	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	0	1
224	0	1
225	0	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T30,T27
1	1	Covered	T17,T18,T19

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T27
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T30,T27

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T57
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T30,T27

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T27,T50
1	0	1	Covered	T17,T30,T31
1	1	0	Covered	T17,T19,T24
1	1	1	Covered	T17,T27,T28

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T27,T28
0	1	Covered	T17,T25,T60
1	0	Covered	T17,T27,T28

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T27,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T27,T28

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T27,T28
1	0	Not Covered
1	1	Covered	T17,T25,T60

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T30,T27
1	Covered	T17,T25,T26

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T30,T27
1	Covered	T17,T27,T28

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T27,T31
1	Covered	T17,T30,T58

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T30,T27
1	Covered	T17,T27,T31

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T27,T31

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T30,T27

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T27,T28

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T30,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T34
IdleSt	175	Covered	T34
Phase0St	146	Covered	T34
Phase1St	192	Covered	T34
Phase2St	209	Covered	T34
Phase3St	227	Covered	T34
TerminalSt	243	Covered	T34
TimeoutSt	153	Covered	T34

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T34
IdleSt->Phase0St	146	Covered	T34
IdleSt->TimeoutSt	153	Covered	T34
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Not Covered
Phase0St->Phase1St	192	Covered	T34
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Not Covered
Phase1St->Phase2St	209	Covered	T34
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Not Covered
Phase2St->Phase3St	227	Covered	T34
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T34
Phase3St->TerminalSt	243	Covered	T34
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T34
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T34
TimeoutSt->Phase0St	166	Covered	T34

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	138	22	19	86.36
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T30,T27
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T27,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T27,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T27,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T30,T27
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T30,T31
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T30,T27
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T30,T27
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T30,T27
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T30,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T25,T60
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T30,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T30,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T27,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T30,T27
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	874973625	380	0	0
CheckAccumTrig0_A	874973625	650	0	0
CheckAccumTrig1_A	874973625	150	0	0
CheckClr_A	874973625	250	0	0
CheckEn_A	874767930	479132485	0	0
CheckPhase0_A	874973625	900	0	0
CheckPhase1_A	874973625	900	0	0
CheckPhase2_A	874973625	900	0	0
CheckPhase3_A	874973625	850	0	0
CheckTimeout0_A	874973625	900	0	0
CheckTimeoutSt1_A	874973625	88650	0	0
CheckTimeoutSt2_A	874973625	650	0	0
CheckTimeoutStTrig_A	874973625	100	0	0
ErrorStAllEscAsserted_A	874973625	1860	0	0
ErrorStIsTerminal_A	874973625	1560	0	0
u_state_regs_A	874973625	874766355	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	380	0	0
T20	41487	76	0	0
T21	0	76	0	0
T22	0	76	0	0
T36	0	76	0	0
T37	0	76	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	650	0	0
T17	447253	3	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	3	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	81339	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	150	0	0
T17	447253	1	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	250	0	0
T17	447253	3	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	3	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	3	0	0
T63	0	3	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874767930	479132485	0	0
T17	447253	316042	0	0
T18	967326	814676	0	0
T19	81152	81091	0	0
T23	78385	78324	0	0
T24	81152	81091	0	0
T29	78385	78324	0	0
T30	326773	19165	0	0
T32	967326	814676	0	0
T35	78385	78324	0	0
T57	81339	2321	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	900	0	0
T17	447253	6	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	6	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	900	0	0
T17	447253	6	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	6	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	900	0	0
T17	447253	6	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	6	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	850	0	0
T17	447253	5	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	81339	0	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	900	0	0
T17	447253	7	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	7	0	0
T26	0	9	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	7	0	0
T61	0	1	0	0
T62	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	88650	0	0
T17	447253	835	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	835	0	0
T26	0	932	0	0
T27	0	3	0	0
T28	0	3	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T58	0	3	0	0
T59	0	3	0	0
T60	0	835	0	0
T61	0	3	0	0
T62	0	3	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	650	0	0
T17	447253	4	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	4	0	0
T26	0	9	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	4	0	0
T63	0	4	0	0
T64	0	4	0	0
T65	0	9	0	0
T67	0	4	0	0
T68	0	4	0	0
T69	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	100	0	0
T17	447253	2	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	2	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	2	0	0
T63	0	2	0	0
T64	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1860	0	0
T20	41487	372	0	0
T21	0	372	0	0
T22	0	372	0	0
T36	0	372	0	0
T37	0	372	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1560	0	0
T20	41487	312	0	0
T21	0	312	0	0
T22	0	312	0	0
T36	0	312	0	0
T37	0	312	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	95	94.06
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	83	93.26
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	0	1
189	0	1
190	0	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	0	1
224	0	1
225	0	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T19,T23
1	1	Covered	T17,T18,T19

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T23
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T19,T23

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T23,T29

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T19,T23
1	0	1	Covered	T17,T23,T29
1	1	0	Covered	T17,T23,T29
1	1	1	Covered	T17,T19,T24

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T24
0	1	Covered	T17,T25,T26
1	0	Covered	T17,T27,T28

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T19,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T27,T28

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T24
1	0	Not Covered
1	1	Covered	T17,T25,T26

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T23,T29
1	Covered	T17,T23,T29

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T23,T29
1	Covered	T17,T23,T29

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T23,T29
1	Covered	T17,T31,T50

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T23,T29
1	Covered	T17,T27,T28

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T50,T52

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T30,T27

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T23,T29

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T20,T21,T22
1	0	Covered	T17,T23,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T34
IdleSt	175	Covered	T34
Phase0St	146	Covered	T34
Phase1St	192	Covered	T34
Phase2St	209	Covered	T34
Phase3St	227	Covered	T34
TerminalSt	243	Covered	T34
TimeoutSt	153	Covered	T34

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T34
IdleSt->Phase0St	146	Covered	T34
IdleSt->TimeoutSt	153	Covered	T34
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Not Covered
Phase0St->Phase1St	192	Covered	T34
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T34
Phase1St->Phase2St	209	Covered	T34
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Not Covered
Phase2St->Phase3St	227	Covered	T34
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T34
Phase3St->TerminalSt	243	Covered	T34
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T34
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T34
TimeoutSt->Phase0St	166	Covered	T34

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
CASE	138	22	20	90.91
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T23,T29
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T27,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T23,T29
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T23,T29
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T29,T35
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T23,T29
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T23,T29
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T23,T29
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T23,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T65,T85
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T23,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T23,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T29,T35
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T23,T29
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	874973625	360	0	0
CheckAccumTrig0_A	874973625	1650	0	0
CheckAccumTrig1_A	874973625	150	0	0
CheckClr_A	874973625	800	0	0
CheckEn_A	874767930	65972845	0	0
CheckPhase0_A	874973625	1950	0	0
CheckPhase1_A	874973625	1750	0	0
CheckPhase2_A	874973625	1750	0	0
CheckPhase3_A	874973625	1700	0	0
CheckTimeout0_A	874973625	3050	0	0
CheckTimeoutSt1_A	874973625	374750	0	0
CheckTimeoutSt2_A	874973625	2750	0	0
CheckTimeoutStTrig_A	874973625	150	0	0
ErrorStAllEscAsserted_A	874973625	1970	0	0
ErrorStIsTerminal_A	874973625	1670	0	0
u_state_regs_A	874973625	874766355	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	360	0	0
T20	41487	72	0	0
T21	0	72	0	0
T22	0	72	0	0
T36	0	72	0	0
T37	0	72	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1650	0	0
T17	447253	6	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	4	0	0
T24	81152	0	0	0
T29	78385	4	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	4	0	0
T48	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T52	0	3	0	0
T57	81339	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	150	0	0
T17	447253	1	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	800	0	0
T23	78385	3	0	0
T24	81152	0	0	0
T29	78385	3	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T33	2783	0	0	0
T35	78385	3	0	0
T47	967326	0	0	0
T48	78385	3	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	2	0	0
T56	0	2	0	0
T57	81339	0	0	0
T72	0	1	0	0
T73	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874767930	65972845	0	0
T17	447253	169596	0	0
T18	967326	902401	0	0
T19	81152	5604	0	0
T23	78385	5607	0	0
T24	81152	5604	0	0
T29	78385	5607	0	0
T30	326773	7928	0	0
T32	967326	902401	0	0
T35	78385	5607	0	0
T57	81339	2300	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1950	0	0
T17	447253	9	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	4	0	0
T24	81152	0	0	0
T27	0	1	0	0
T29	78385	4	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	4	0	0
T48	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T57	81339	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1750	0	0
T17	447253	9	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	2	0	0
T24	81152	0	0	0
T27	0	1	0	0
T29	78385	2	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T57	81339	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1750	0	0
T17	447253	9	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	2	0	0
T24	81152	0	0	0
T27	0	1	0	0
T29	78385	2	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T57	81339	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1700	0	0
T17	447253	9	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	2	0	0
T24	81152	0	0	0
T27	0	1	0	0
T29	78385	2	0	0
T30	326773	1	0	0
T31	0	1	0	0
T32	967326	0	0	0
T35	78385	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T57	81339	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	3050	0	0
T17	447253	18	0	0
T18	967326	0	0	0
T19	81152	7	0	0
T23	78385	0	0	0
T24	81152	7	0	0
T25	0	18	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T50	0	1	0	0
T57	81339	0	0	0
T72	0	1	0	0
T81	0	1	0	0
T83	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	374750	0	0
T17	447253	4027	0	0
T18	967326	0	0	0
T19	81152	1070	0	0
T23	78385	0	0	0
T24	81152	1070	0	0
T25	0	4027	0	0
T27	0	5	0	0
T28	0	5	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T50	0	114	0	0
T57	81339	0	0	0
T72	0	114	0	0
T81	0	114	0	0
T83	0	1070	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	2750	0	0
T17	447253	15	0	0
T18	967326	0	0	0
T19	81152	7	0	0
T23	78385	0	0	0
T24	81152	7	0	0
T25	0	15	0	0
T26	0	32	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T50	0	1	0	0
T57	81339	0	0	0
T72	0	1	0	0
T81	0	1	0	0
T83	0	7	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	150	0	0
T17	447253	2	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T29	78385	0	0	0
T30	326773	0	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T57	81339	0	0	0
T60	0	2	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1970	0	0
T20	41487	394	0	0
T21	0	394	0	0
T22	0	394	0	0
T36	0	394	0	0
T37	0	394	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	1670	0	0
T20	41487	334	0	0
T21	0	334	0	0
T22	0	334	0	0
T36	0	334	0	0
T37	0	334	0	0
T38	326773	0	0	0
T39	326773	0	0	0
T40	81339	0	0	0
T41	78385	0	0	0
T42	81339	0	0	0
T43	172614	0	0	0
T44	78385	0	0	0
T45	326773	0	0	0
T46	269693	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0