Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66993796	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32707414

1

T16

31039

T27

27341

T28

16530

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14837713	1			T16	57852		T27	54943		T28	16641
values[0x0]	41130216	1			T16	20427		T27	434		T28	12045
values[0x1]	43733281	1			T16	20194		T27	407		T28	12083

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56935788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42765422

1

T16

45763

T27

35917

T28

19879

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	336749	1			T16	302		T28	165		T32	118
valid_sources[0x01]	338722	1			T16	612		T28	209		T30	20
valid_sources[0x02]	326850	1			T16	311		T28	156		T30	23
valid_sources[0x03]	322220	1			T16	1251		T27	348		T28	168
valid_sources[0x04]	313384	1			T27	174		T28	163		T30	23
valid_sources[0x05]	330048	1			T27	174		T28	125		T30	11
valid_sources[0x06]	324462	1			T28	168		T30	47		T31	128
valid_sources[0x07]	315711	1			T27	174		T28	155		T30	3
valid_sources[0x08]	319837	1			T27	174		T28	113		T30	6
valid_sources[0x09]	817959	1			T16	753		T27	174		T28	142
valid_sources[0x0a]	633616	1			T28	143		T29	1		T31	384
valid_sources[0x0b]	352079	1			T16	607		T28	181		T30	2
valid_sources[0x0c]	587807	1			T16	153		T27	174		T28	163
valid_sources[0x0d]	318205	1			T16	153		T27	174		T28	183
valid_sources[0x0e]	334342	1			T16	463		T28	164		T30	44
valid_sources[0x0f]	321175	1			T16	941		T27	174		T28	187
valid_sources[0x10]	327420	1			T16	153		T28	159		T31	192
valid_sources[0x11]	319575	1			T28	177		T30	16		T31	128
valid_sources[0x12]	333972	1			T16	155		T28	164		T31	128
valid_sources[0x13]	317436	1			T16	1225		T28	177		T30	10
valid_sources[0x14]	319210	1			T16	456		T28	145		T30	26
valid_sources[0x15]	329750	1			T16	1245		T28	162		T30	23
valid_sources[0x16]	325623	1			T16	310		T27	174		T28	162
valid_sources[0x17]	313513	1			T16	443		T27	174		T28	175
valid_sources[0x18]	335000	1			T28	179		T30	18		T31	384
valid_sources[0x19]	338583	1			T28	157		T30	3		T32	88
valid_sources[0x1a]	330825	1			T16	156		T28	120		T30	11
valid_sources[0x1b]	334942	1			T16	762		T28	172		T30	21
valid_sources[0x1c]	324834	1			T16	153		T28	165		T30	48
valid_sources[0x1d]	336251	1			T16	609		T28	180		T30	19
valid_sources[0x1e]	318895	1			T16	1701		T28	204		T30	26
valid_sources[0x1f]	320920	1			T27	174		T28	147		T32	118
valid_sources[0x20]	313290	1			T28	90		T30	20		T31	320
valid_sources[0x21]	318759	1			T27	174		T28	156		T30	34
valid_sources[0x22]	315259	1			T16	775		T28	124		T30	1
valid_sources[0x23]	312840	1			T27	174		T28	196		T30	1
valid_sources[0x24]	319686	1			T16	2020		T28	149		T32	93
valid_sources[0x25]	321511	1			T27	348		T28	196		T30	30
valid_sources[0x26]	322190	1			T16	460		T27	174		T28	137
valid_sources[0x27]	1008975	1			T16	609		T28	128		T31	384
valid_sources[0x28]	324281	1			T28	161		T30	12		T32	101
valid_sources[0x29]	323196	1			T28	185		T31	320		T32	106
valid_sources[0x2a]	350252	1			T16	299		T27	28988		T28	190
valid_sources[0x2b]	317566	1			T16	443		T28	137		T30	49
valid_sources[0x2c]	312124	1			T16	156		T27	174		T28	182
valid_sources[0x2d]	346227	1			T16	153		T28	160		T32	99
valid_sources[0x2e]	316499	1			T27	174		T28	179		T30	36
valid_sources[0x2f]	324919	1			T16	156		T27	348		T28	175
valid_sources[0x30]	637185	1			T16	450		T28	129		T30	15
valid_sources[0x31]	619943	1			T16	155		T28	187		T30	32
valid_sources[0x32]	331544	1			T16	297		T28	199		T30	3
valid_sources[0x33]	814835	1			T16	610		T28	178		T30	20
valid_sources[0x34]	316905	1			T16	155		T28	177		T31	192
valid_sources[0x35]	345041	1			T27	174		T28	146		T31	192
valid_sources[0x36]	325439	1			T16	461		T27	174		T28	144
valid_sources[0x37]	327649	1			T16	306		T28	181		T31	192
valid_sources[0x38]	314056	1			T16	1078		T27	174		T28	187
valid_sources[0x39]	322609	1			T16	299		T28	174		T30	6
valid_sources[0x3a]	313970	1			T16	759		T28	154		T30	18
valid_sources[0x3b]	320754	1			T27	174		T28	155		T30	12
valid_sources[0x3c]	315130	1			T28	168		T30	18		T32	95
valid_sources[0x3d]	334398	1			T16	309		T27	348		T28	151
valid_sources[0x3e]	325394	1			T16	1067		T27	348		T28	169
valid_sources[0x3f]	321058	1			T27	696		T28	141		T31	320
valid_sources[0x40]	320505	1			T16	302		T28	181		T30	15
valid_sources[0x41]	323014	1			T16	299		T27	174		T28	192
valid_sources[0x42]	316601	1			T16	302		T28	228		T30	4
valid_sources[0x43]	321178	1			T16	316		T28	190		T30	8
valid_sources[0x44]	321569	1			T28	131		T30	11		T31	256
valid_sources[0x45]	322061	1			T16	1400		T28	162		T30	17
valid_sources[0x46]	317326	1			T28	149		T30	4		T31	768
valid_sources[0x47]	310998	1			T16	765		T28	180		T30	18
valid_sources[0x48]	326024	1			T16	476		T28	170		T32	102
valid_sources[0x49]	317524	1			T16	1205		T27	174		T28	170
valid_sources[0x4a]	317405	1			T16	931		T28	157		T32	126
valid_sources[0x4b]	637264	1			T16	763		T28	146		T30	30
valid_sources[0x4c]	659120	1			T28	142		T31	320		T32	76
valid_sources[0x4d]	308079	1			T28	196		T29	2		T30	15
valid_sources[0x4e]	331192	1			T16	452		T27	174		T28	163
valid_sources[0x4f]	535231	1			T16	154		T27	348		T28	154
valid_sources[0x50]	319176	1			T28	158		T30	25		T31	192
valid_sources[0x51]	329006	1			T16	302		T27	348		T28	96
valid_sources[0x52]	316566	1			T16	1091		T28	133		T31	384
valid_sources[0x53]	327206	1			T16	467		T28	159		T32	89
valid_sources[0x54]	333850	1			T16	153		T28	143		T30	3
valid_sources[0x55]	323002	1			T16	309		T28	231		T30	3
valid_sources[0x56]	325456	1			T28	186		T29	1		T30	9
valid_sources[0x57]	1140704	1			T16	765		T27	174		T28	176
valid_sources[0x58]	318857	1			T16	153		T27	348		T28	148
valid_sources[0x59]	316860	1			T16	450		T28	155		T30	15
valid_sources[0x5a]	330124	1			T16	599		T28	133		T30	5
valid_sources[0x5b]	318459	1			T16	456		T27	174		T28	127
valid_sources[0x5c]	318756	1			T16	306		T28	161		T30	18
valid_sources[0x5d]	326569	1			T16	609		T28	150		T31	320
valid_sources[0x5e]	323344	1			T16	310		T27	174		T28	175
valid_sources[0x5f]	315862	1			T16	1259		T28	134		T30	11
valid_sources[0x60]	323760	1			T16	596		T28	161		T30	18
valid_sources[0x61]	317996	1			T16	455		T27	174		T28	133
valid_sources[0x62]	320994	1			T16	452		T28	156		T30	15
valid_sources[0x63]	319333	1			T27	174		T28	147		T31	192
valid_sources[0x64]	321019	1			T28	151		T30	20		T31	128
valid_sources[0x65]	318324	1			T16	153		T27	174		T28	150
valid_sources[0x66]	812523	1			T16	933		T27	174		T28	160
valid_sources[0x67]	326333	1			T28	168		T30	14		T32	79
valid_sources[0x68]	318279	1			T16	299		T27	348		T28	156
valid_sources[0x69]	536244	1			T27	174		T28	217		T30	27
valid_sources[0x6a]	322911	1			T16	156		T28	174		T31	128
valid_sources[0x6b]	321527	1			T16	153		T28	144		T31	192
valid_sources[0x6c]	338531	1			T16	466		T27	174		T28	154
valid_sources[0x6d]	315992	1			T16	769		T28	206		T30	20
valid_sources[0x6e]	389342	1			T16	621		T28	137		T30	3
valid_sources[0x6f]	321704	1			T28	113		T30	5		T32	120
valid_sources[0x70]	327897	1			T27	174		T28	197		T30	40
valid_sources[0x71]	317738	1			T16	1066		T28	131		T30	71
valid_sources[0x72]	321475	1			T16	1084		T28	147		T30	4
valid_sources[0x73]	321867	1			T16	1215		T28	152		T30	16
valid_sources[0x74]	314879	1			T27	174		T28	189		T30	5
valid_sources[0x75]	328105	1			T16	758		T27	348		T28	109
valid_sources[0x76]	324911	1			T16	299		T28	183		T30	46
valid_sources[0x77]	322460	1			T28	162		T30	65		T31	576
valid_sources[0x78]	325800	1			T16	153		T27	174		T28	157
valid_sources[0x79]	809420	1			T16	766		T27	174		T28	176
valid_sources[0x7a]	326615	1			T16	471		T27	174		T28	136
valid_sources[0x7b]	316659	1			T28	183		T30	19		T31	128
valid_sources[0x7c]	318252	1			T28	146		T30	3		T31	192
valid_sources[0x7d]	315024	1			T27	348		T28	182		T32	112
valid_sources[0x7e]	1007693	1			T16	1065		T27	174		T28	129
valid_sources[0x7f]	317552	1			T16	611		T27	174		T28	170
valid_sources[0x80]	710154	1			T16	912		T27	174		T28	186

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7484542

1

T16

19950

T27

27076

T28

8363

values[0x0]

all_enables

biggest_size

15866219

1

T16

7260

T27

159

T28

5056

values[0x1]

all_enables

biggest_size

9356653

1

T16

3829

T27

106

T28

3111