Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T227
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T8

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13538	0	0
DisabledNoTrigBkwd_A	2147483647	807874	0	0
DisabledNoTrigFwd_A	2147483647	1651000687	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13538	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	1036	0	0
T9	503009	0	0	0
T13	17460	0	0	0
T14	34192	0	0	0
T17	616487	0	0	0
T23	3937	514	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	55579	0	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T55	236122	0	0	0
T227	0	683	0	0
T228	0	299	0	0
T229	1034	273	0	0
T230	0	1142	0	0
T231	3872	1095	0	0
T232	0	865	0	0
T233	0	647	0	0
T234	0	541	0	0
T235	0	382	0	0
T236	0	307	0	0
T237	0	526	0	0
T238	0	314	0	0
T239	0	396	0	0
T240	0	206	0	0
T241	0	830	0	0
T242	0	734	0	0
T243	0	1714	0	0
T244	0	1034	0	0
T245	5653	0	0	0
T246	445127	0	0	0
T247	117063	0	0	0
T248	111927	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	807874	0	0
T1	31058	10	0	0
T2	160214	1	0	0
T3	9902	0	0	0
T4	2713956	0	0	0
T5	1851012	1036	0	0
T6	1060916	4729	0	0
T7	17636	24	0	0
T8	259788	79	0	0
T9	1006018	9557	0	0
T17	1232974	1	0	0
T18	0	2031	0	0
T19	0	4931	0	0
T23	15748	4	0	0
T24	374012	71	0	0
T25	82268	0	0	0
T26	0	33	0	0
T42	0	2	0	0
T55	0	169	0	0
T56	0	175	0	0
T57	0	729	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1651000687	0	0
T1	62116	44355	0	0
T2	320428	311425	0	0
T3	19804	12311	0	0
T4	2713956	2527798	0	0
T5	1851012	929060	0	0
T7	17636	12382	0	0
T8	259788	85498	0	0
T23	15748	12893	0	0
T24	374012	192173	0	0
T25	82268	52709	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T228,T235
1	1	Covered	T1,T2,T8

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T7,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	751538390	4817	0	0
DisabledNoTrigBkwd_A	751538390	202573	0	0
DisabledNoTrigFwd_A	751538390	398602470	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	4817	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	1036	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	55579	0	0	0
T55	236122	0	0	0
T228	0	299	0	0
T235	0	382	0	0
T237	0	526	0	0
T238	0	314	0	0
T239	0	396	0	0
T241	0	830	0	0
T244	0	1034	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	202573	0	0
T1	15529	3	0	0
T2	80107	1	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	0	2427	0	0
T7	4409	24	0	0
T8	64947	0	0	0
T9	0	2632	0	0
T18	0	5	0	0
T23	3937	0	0	0
T24	93503	40	0	0
T25	20567	0	0	0
T26	0	18	0	0
T42	0	2	0	0
T56	0	101	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	398602470	0	0
T1	15529	12321	0	0
T2	80107	71326	0	0
T3	4951	1959	0	0
T4	678489	678405	0	0
T5	462753	462745	0	0
T7	4409	3071	0	0
T8	64947	57222	0	0
T23	3937	3196	0	0
T24	93503	14591	0	0
T25	20567	5396	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T229,T232,T242
1	1	Covered	T1,T3,T8

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T24,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	751538390	1872	0	0
DisabledNoTrigBkwd_A	751538390	185360	0	0
DisabledNoTrigFwd_A	751538390	431333086	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1872	0	0
T13	17460	0	0	0
T14	34192	0	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T229	1034	273	0	0
T232	0	865	0	0
T242	0	734	0	0
T245	5653	0	0	0
T246	445127	0	0	0
T247	117063	0	0	0
T248	111927	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	185360	0	0
T4	678489	0	0	0
T5	462753	380	0	0
T6	530458	2302	0	0
T7	4409	0	0	0
T8	64947	17	0	0
T9	503009	2036	0	0
T17	616487	0	0	0
T18	0	2	0	0
T19	0	1253	0	0
T23	3937	0	0	0
T24	93503	3	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	32	0	0
T56	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	431333086	0	0
T1	15529	13839	0	0
T2	80107	80033	0	0
T3	4951	3504	0	0
T4	678489	678405	0	0
T5	462753	3041	0	0
T7	4409	3081	0	0
T8	64947	2993	0	0
T23	3937	3221	0	0
T24	93503	81094	0	0
T25	20567	19250	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T231,T233,T243
1	1	Covered	T1,T3,T8

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T24,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	751538390	3456	0	0
DisabledNoTrigBkwd_A	751538390	211533	0	0
DisabledNoTrigFwd_A	751538390	402413002	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	3456	0	0
T65	192654	0	0	0
T231	3872	1095	0	0
T233	0	647	0	0
T243	0	1714	0	0
T249	47455	0	0	0
T250	72464	0	0	0
T251	371303	0	0	0
T252	174018	0	0	0
T253	108628	0	0	0
T254	18204	0	0	0
T255	81128	0	0	0
T256	48321	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	211533	0	0
T4	678489	0	0	0
T5	462753	2	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	41	0	0
T9	503009	1799	0	0
T17	616487	0	0	0
T18	0	1593	0	0
T19	0	6	0	0
T23	3937	0	0	0
T24	93503	28	0	0
T25	20567	0	0	0
T26	0	9	0	0
T55	0	67	0	0
T56	0	68	0	0
T57	0	729	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	402413002	0	0
T1	15529	13839	0	0
T2	80107	80033	0	0
T3	4951	1967	0	0
T4	678489	492583	0	0
T5	462753	460192	0	0
T7	4409	3100	0	0
T8	64947	16469	0	0
T23	3937	3229	0	0
T24	93503	3083	0	0
T25	20567	15317	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T7
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T8,T23

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T227,T230
1	1	Covered	T1,T8,T23

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T23

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	751538390	3393	0	0
DisabledNoTrigBkwd_A	751538390	208408	0	0
DisabledNoTrigFwd_A	751538390	418652129	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	3393	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T23	3937	514	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	55579	0	0	0
T55	236122	0	0	0
T102	36324	0	0	0
T227	0	683	0	0
T230	0	1142	0	0
T234	0	541	0	0
T236	0	307	0	0
T240	0	206	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	208408	0	0
T1	15529	7	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	654	0	0
T7	4409	0	0	0
T8	64947	21	0	0
T9	0	3090	0	0
T17	0	1	0	0
T18	0	431	0	0
T19	0	3672	0	0
T23	3937	4	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	5	0	0
T55	0	70	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	418652129	0	0
T1	15529	4356	0	0
T2	80107	80033	0	0
T3	4951	4881	0	0
T4	678489	678405	0	0
T5	462753	3082	0	0
T7	4409	3130	0	0
T8	64947	8814	0	0
T23	3937	3247	0	0
T24	93503	93405	0	0
T25	20567	12746	0	0