Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T36,T37
1	1	1	Covered	T1,T2,T8

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T23,T24
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T22,T38,T39

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T38,T39

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Not Covered
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T2,T8,T7

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T3,T8

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T5,T6

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T9

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T8,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T16
IdleSt	175	Covered	T16
Phase0St	146	Covered	T16
Phase1St	192	Covered	T16
Phase2St	209	Covered	T16
Phase3St	227	Covered	T16
TerminalSt	243	Covered	T16
TimeoutSt	153	Covered	T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T16
IdleSt->Phase0St	146	Covered	T16
IdleSt->TimeoutSt	153	Covered	T16
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T16
Phase0St->Phase1St	192	Covered	T16
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T16
Phase1St->Phase2St	209	Covered	T16
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T16
Phase2St->Phase3St	227	Covered	T16
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T16
Phase3St->TerminalSt	243	Covered	T16
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T16
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T16
TimeoutSt->Phase0St	166	Covered	T16

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T40,T41
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T42,T19
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T42,T43,T44
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T38,T39,T45
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1006	0	0
CheckAccumTrig0_A	2147483647	2598	0	0
CheckAccumTrig1_A	2147483647	119	0	0
CheckClr_A	2147483647	1259	0	0
CheckEn_A	2147483647	1223913811	0	0
CheckPhase0_A	2147483647	2982	0	0
CheckPhase1_A	2147483647	2917	0	0
CheckPhase2_A	2147483647	2865	0	0
CheckPhase3_A	2147483647	2798	0	0
CheckTimeout0_A	2147483647	4135	0	0
CheckTimeoutSt1_A	2147483647	485088	0	0
CheckTimeoutSt2_A	2147483647	3707	0	0
CheckTimeoutStTrig_A	2147483647	309	0	0
ErrorStAllEscAsserted_A	2147483647	5134	0	0
ErrorStIsTerminal_A	2147483647	4294	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1006	0	0
T13	69840	130	0	0
T14	136768	293	0	0
T15	336784	145	0	0
T46	0	132	0	0
T47	0	306	0	0
T48	462780	0	0	0
T49	69216	0	0	0
T50	1435420	0	0	0
T51	228056	0	0	0
T52	509532	0	0	0
T53	1520704	0	0	0
T54	444924	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2598	0	0
T1	31058	4	0	0
T2	160214	1	0	0
T3	9902	0	0	0
T4	2713956	0	0	0
T5	1851012	7	0	0
T6	1060916	2	0	0
T7	17636	1	0	0
T8	259788	5	0	0
T9	1006018	5	0	0
T10	0	1	0	0
T17	1232974	1	0	0
T18	0	4	0	0
T19	0	7	0	0
T23	15748	1	0	0
T24	374012	4	0	0
T25	82268	0	0	0
T26	0	4	0	0
T42	0	2	0	0
T55	0	3	0	0
T56	0	3	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119	0	0
T22	334586	1	0	0
T38	662328	1	0	0
T39	675178	1	0	0
T43	250497	0	0	0
T45	85606	0	0	0
T50	0	1	0	0
T58	249041	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	20039	0	0	0
T76	238983	0	0	0
T77	574861	0	0	0
T78	117037	0	0	0
T79	993631	0	0	0
T80	71664	0	0	0
T81	123732	0	0	0
T82	138694	0	0	0
T83	28251	0	0	0
T84	72274	0	0	0
T85	8521	0	0	0
T86	285936	0	0	0
T87	968492	0	0	0
T88	112978	0	0	0
T89	21065	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1259	0	0
T1	46587	3	0	0
T2	240321	0	0	0
T3	14853	0	0	0
T4	2035467	0	0	0
T5	1388259	0	0	0
T7	13227	0	0	0
T8	194841	1	0	0
T10	292422	0	0	0
T11	289219	0	0	0
T18	892985	1	0	0
T19	549903	4	0	0
T20	0	1	0	0
T21	321462	2	0	0
T22	334586	0	0	0
T23	11811	0	0	0
T24	280509	1	0	0
T25	61701	0	0	0
T38	0	6	0	0
T39	0	21	0	0
T42	32004	2	0	0
T43	0	12	0	0
T45	0	6	0	0
T57	916146	6	0	0
T75	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	5	0	0
T93	6420	0	0	0
T94	15232	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223913811	0	0
T1	62116	41327	0	0
T2	320428	242066	0	0
T3	19804	12309	0	0
T4	2713956	2527794	0	0
T5	1851012	477524	0	0
T7	17636	12382	0	0
T8	259788	82820	0	0
T23	15748	12893	0	0
T24	374012	126575	0	0
T25	82268	40576	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2982	0	0
T1	31058	4	0	0
T2	160214	1	0	0
T3	14853	1	0	0
T4	2713956	0	0	0
T5	1851012	7	0	0
T6	1060916	2	0	0
T7	17636	1	0	0
T8	259788	6	0	0
T9	1006018	5	0	0
T17	616487	1	0	0
T18	0	4	0	0
T19	0	6	0	0
T23	15748	1	0	0
T24	374012	4	0	0
T25	82268	1	0	0
T26	0	5	0	0
T55	0	3	0	0
T56	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2917	0	0
T1	31058	4	0	0
T2	160214	1	0	0
T3	14853	1	0	0
T4	2713956	0	0	0
T5	1851012	5	0	0
T6	1060916	2	0	0
T7	17636	1	0	0
T8	259788	6	0	0
T9	1006018	5	0	0
T17	616487	1	0	0
T18	0	3	0	0
T19	0	4	0	0
T21	0	1	0	0
T23	15748	1	0	0
T24	374012	4	0	0
T25	82268	1	0	0
T26	0	5	0	0
T55	0	3	0	0
T56	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2865	0	0
T1	31058	4	0	0
T2	160214	1	0	0
T3	14853	1	0	0
T4	2713956	0	0	0
T5	1851012	4	0	0
T6	1060916	2	0	0
T7	17636	1	0	0
T8	259788	6	0	0
T9	1006018	5	0	0
T17	616487	1	0	0
T18	0	3	0	0
T19	0	4	0	0
T21	0	1	0	0
T23	15748	1	0	0
T24	374012	4	0	0
T25	82268	1	0	0
T26	0	5	0	0
T55	0	3	0	0
T56	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2798	0	0
T1	31058	4	0	0
T2	160214	1	0	0
T3	14853	1	0	0
T4	2713956	0	0	0
T5	1851012	4	0	0
T6	1060916	2	0	0
T7	17636	1	0	0
T8	259788	6	0	0
T9	1006018	5	0	0
T17	616487	1	0	0
T18	0	3	0	0
T19	0	4	0	0
T21	0	1	0	0
T23	15748	1	0	0
T24	374012	4	0	0
T25	82268	1	0	0
T26	0	5	0	0
T55	0	3	0	0
T56	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4135	0	0
T1	31058	3	0	0
T2	160214	0	0	0
T3	9902	2	0	0
T4	2713956	0	0	0
T5	1851012	0	0	0
T6	1060916	0	0	0
T7	17636	0	0	0
T8	259788	2	0	0
T9	1006018	0	0	0
T17	1232974	0	0	0
T19	0	2	0	0
T22	0	1	0	0
T23	15748	0	0	0
T24	374012	0	0	0
T25	82268	7	0	0
T26	0	2	0	0
T38	0	18	0	0
T39	0	23	0	0
T45	0	3	0	0
T57	0	24	0	0
T78	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T95	0	7	0	0
T96	0	12	0	0
T97	0	4	0	0
T98	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	485088	0	0
T1	31058	1370	0	0
T2	160214	0	0	0
T3	9902	517	0	0
T4	2713956	0	0	0
T5	1851012	0	0	0
T6	1060916	0	0	0
T7	17636	0	0	0
T8	259788	761	0	0
T9	1006018	0	0	0
T17	1232974	0	0	0
T19	0	80	0	0
T22	0	7	0	0
T23	15748	0	0	0
T24	374012	0	0	0
T25	82268	1273	0	0
T26	0	211	0	0
T38	0	2689	0	0
T39	0	5271	0	0
T45	0	97	0	0
T57	0	2252	0	0
T78	0	3	0	0
T83	0	47	0	0
T84	0	157	0	0
T91	0	1074	0	0
T93	0	209	0	0
T95	0	811	0	0
T96	0	2162	0	0
T97	0	766	0	0
T98	0	7	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3707	0	0
T1	31058	2	0	0
T2	160214	0	0	0
T3	9902	1	0	0
T4	2035467	0	0	0
T5	1388259	0	0	0
T6	1060916	0	0	0
T7	13227	0	0	0
T8	194841	1	0	0
T9	1006018	0	0	0
T17	1232974	0	0	0
T18	892985	0	0	0
T19	0	2	0	0
T23	11811	0	0	0
T24	280509	0	0	0
T25	82268	6	0	0
T26	55579	1	0	0
T38	0	15	0	0
T39	0	12	0	0
T42	32004	0	0	0
T45	0	2	0	0
T55	236122	0	0	0
T56	234033	0	0	0
T57	0	23	0	0
T59	0	1	0	0
T84	0	1	0	0
T88	0	1	0	0
T92	0	24	0	0
T93	0	1	0	0
T95	0	6	0	0
T96	0	11	0	0
T97	0	5	0	0
T99	0	1	0	0
T100	0	7	0	0
T101	0	1	0	0
T102	36324	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	309	0	0
T1	15529	1	0	0
T3	0	1	0	0
T4	1356978	0	0	0
T5	925506	0	0	0
T6	530458	0	0	0
T7	8818	0	0	0
T8	129894	1	0	0
T9	503009	0	0	0
T10	292422	0	0	0
T11	289219	0	0	0
T12	960878	0	0	0
T17	616487	0	0	0
T22	334586	0	0	0
T23	7874	0	0	0
T24	187006	0	0	0
T25	41134	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T39	0	9	0	0
T40	0	1	0	0
T57	916146	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T83	0	1	0	0
T88	0	1	0	0
T90	56352	0	0	0
T91	0	1	0	0
T93	6420	0	0	0
T94	15232	0	0	0
T95	21126	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T100	0	2	0	0
T103	0	2	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	77444	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5134	0	0
T13	69840	732	0	0
T14	136768	1475	0	0
T15	336784	736	0	0
T46	0	726	0	0
T47	0	1465	0	0
T48	462780	0	0	0
T49	69216	0	0	0
T50	1435420	0	0	0
T51	228056	0	0	0
T52	509532	0	0	0
T53	1520704	0	0	0
T54	444924	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4294	0	0
T13	69840	612	0	0
T14	136768	1235	0	0
T15	336784	616	0	0
T46	0	606	0	0
T47	0	1225	0	0
T48	462780	0	0	0
T49	69216	0	0	0
T50	1435420	0	0	0
T51	228056	0	0	0
T52	509532	0	0	0
T53	1520704	0	0	0
T54	444924	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	62116	61720	0	0
T2	320428	320132	0	0
T3	19804	19524	0	0
T4	2713956	2713620	0	0
T5	1851012	1850980	0	0
T7	17636	17332	0	0
T8	259788	259480	0	0
T23	15748	15548	0	0
T24	374012	373620	0	0
T25	82268	81984	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T24,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T5,T6,T55
1	1	0	Covered	T1,T3,T25
1	1	1	Covered	T1,T3,T26

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T26
0	1	Covered	T57,T38,T39
1	0	Covered	T39,T59,T63

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T39,T59,T63

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T26
1	0	Not Covered
1	1	Covered	T57,T38,T39

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T5,T6
1	Covered	T24,T19,T75

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T24,T5
1	Covered	T55,T57,T38

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T24,T9,T55
1	Covered	T8,T5,T6

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T24,T5
1	Covered	T9,T56,T21

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T8,T6,T56

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T24,T5,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T8,T24,T55

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T5,T55,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T16
IdleSt	175	Covered	T16
Phase0St	146	Covered	T16
Phase1St	192	Covered	T16
Phase2St	209	Covered	T16
Phase3St	227	Covered	T16
TerminalSt	243	Covered	T16
TimeoutSt	153	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T16
IdleSt->Phase0St	146	Covered	T16
IdleSt->TimeoutSt	153	Covered	T16
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T16
Phase0St->Phase1St	192	Covered	T16
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T16
Phase1St->Phase2St	209	Covered	T16
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T16
Phase2St->Phase3St	227	Covered	T16
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T16
Phase3St->TerminalSt	243	Covered	T16
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T16
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T16
TimeoutSt->Phase0St	166	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T57,T38,T39
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T108,T109,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T8,T24,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T8,T24,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T19,T41
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T8,T24,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T8,T24,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T43,T51,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T8,T24,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T8,T24,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T92,T64,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T8,T24,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T8,T24,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T21,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T24,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	751538390	263	0	0
CheckAccumTrig0_A	751538390	586	0	0
CheckAccumTrig1_A	751538390	16	0	0
CheckClr_A	751538390	299	0	0
CheckEn_A	751314551	324853956	0	0
CheckPhase0_A	751538390	679	0	0
CheckPhase1_A	751538390	654	0	0
CheckPhase2_A	751538390	643	0	0
CheckPhase3_A	751538390	627	0	0
CheckTimeout0_A	751538390	1129	0	0
CheckTimeoutSt1_A	751538390	131800	0	0
CheckTimeoutSt2_A	751538390	1024	0	0
CheckTimeoutStTrig_A	751538390	89	0	0
ErrorStAllEscAsserted_A	751538390	1302	0	0
ErrorStIsTerminal_A	751538390	1092	0	0
u_state_regs_A	751538390	751381070	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	263	0	0
T13	17460	55	0	0
T14	34192	47	0	0
T15	84196	43	0	0
T46	0	26	0	0
T47	0	92	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	586	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	1	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T17	616487	0	0	0
T18	0	1	0	0
T19	0	5	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	16	0	0
T39	675178	1	0	0
T43	250497	0	0	0
T45	85606	0	0	0
T50	0	1	0	0
T59	0	1	0	0
T63	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T81	123732	0	0	0
T82	138694	0	0	0
T83	28251	0	0	0
T84	72274	0	0	0
T85	8521	0	0	0
T86	285936	0	0	0
T87	968492	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	299	0	0
T10	292422	0	0	0
T11	289219	0	0	0
T18	892985	1	0	0
T19	549903	4	0	0
T21	321462	1	0	0
T22	334586	0	0	0
T38	0	1	0	0
T39	0	9	0	0
T42	32004	0	0	0
T43	0	12	0	0
T57	916146	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T91	0	1	0	0
T92	0	4	0	0
T93	6420	0	0	0
T94	15232	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751314551	324853956	0	0
T1	15529	13838	0	0
T2	80107	80032	0	0
T3	4951	3503	0	0
T4	678489	678404	0	0
T5	462753	3041	0	0
T7	4409	3081	0	0
T8	64947	2993	0	0
T23	3937	3221	0	0
T24	93503	15497	0	0
T25	20567	19249	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	679	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	1	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T17	616487	0	0	0
T18	0	1	0	0
T19	0	5	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	654	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	1	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T17	616487	0	0	0
T19	0	3	0	0
T21	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	643	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	1	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T17	616487	0	0	0
T19	0	3	0	0
T21	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	627	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	1	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T17	616487	0	0	0
T19	0	3	0	0
T21	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1129	0	0
T1	15529	1	0	0
T2	80107	0	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	1	0	0
T38	0	6	0	0
T39	0	3	0	0
T57	0	9	0	0
T91	0	1	0	0
T93	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	131800	0	0
T1	15529	701	0	0
T2	80107	0	0	0
T3	4951	492	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	123	0	0
T38	0	916	0	0
T39	0	1143	0	0
T57	0	721	0	0
T91	0	112	0	0
T93	0	209	0	0
T97	0	246	0	0
T98	0	7	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1024	0	0
T1	15529	1	0	0
T2	80107	0	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T57	0	8	0	0
T92	0	3	0	0
T93	0	1	0	0
T97	0	1	0	0
T100	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	89	0	0
T10	292422	0	0	0
T11	289219	0	0	0
T12	960878	0	0	0
T22	334586	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T57	916146	1	0	0
T88	0	1	0	0
T90	56352	0	0	0
T91	0	1	0	0
T93	6420	0	0	0
T94	15232	0	0	0
T95	21126	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T100	0	1	0	0
T103	0	2	0	0
T104	0	1	0	0
T107	77444	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1302	0	0
T13	17460	199	0	0
T14	34192	371	0	0
T15	84196	190	0	0
T46	0	170	0	0
T47	0	372	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1092	0	0
T13	17460	169	0	0
T14	34192	311	0	0
T15	84196	160	0	0
T46	0	140	0	0
T47	0	312	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	751381070	0	0
T1	15529	15430	0	0
T2	80107	80033	0	0
T3	4951	4881	0	0
T4	678489	678405	0	0
T5	462753	462745	0	0
T7	4409	4333	0	0
T8	64947	64870	0	0
T23	3937	3887	0	0
T24	93503	93405	0	0
T25	20567	20496	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T24,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T24,T5,T9
1	1	0	Covered	T1,T3,T25
1	1	1	Covered	T1,T3,T25

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T25
0	1	Covered	T1,T3,T26
1	0	Covered	T22,T45,T62

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T45,T62

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Not Covered
1	1	Covered	T1,T3,T26

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T24
1	Covered	T8,T57,T10

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T24,T26
1	Covered	T3,T5,T9

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T8,T24
1	Covered	T26,T55,T19

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T8,T5
1	Covered	T24,T56,T96

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T8,T24

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T8,T24

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T8,T9

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T8,T24,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T16
IdleSt	175	Covered	T16
Phase0St	146	Covered	T16
Phase1St	192	Covered	T16
Phase2St	209	Covered	T16
Phase3St	227	Covered	T16
TerminalSt	243	Covered	T16
TimeoutSt	153	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T16
IdleSt->Phase0St	146	Covered	T16
IdleSt->TimeoutSt	153	Covered	T16
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T16
Phase0St->Phase1St	192	Covered	T16
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T16
Phase1St->Phase2St	209	Covered	T16
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T16
Phase2St->Phase3St	227	Covered	T16
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T16
Phase3St->TerminalSt	243	Covered	T16
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T16
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T16
TimeoutSt->Phase0St	166	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T24,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T95
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T40,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T8,T24
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T113,T114,T115
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T8,T24
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T8,T24
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T44,T61,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T8,T24
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T8,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T45,T117,T44
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T8,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T8,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T78,T80,T39
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T8,T24
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	751538390	264	0	0
CheckAccumTrig0_A	751538390	567	0	0
CheckAccumTrig1_A	751538390	38	0	0
CheckClr_A	751538390	287	0	0
CheckEn_A	751314551	318760710	0	0
CheckPhase0_A	751538390	678	0	0
CheckPhase1_A	751538390	667	0	0
CheckPhase2_A	751538390	652	0	0
CheckPhase3_A	751538390	630	0	0
CheckTimeout0_A	751538390	888	0	0
CheckTimeoutSt1_A	751538390	100537	0	0
CheckTimeoutSt2_A	751538390	773	0	0
CheckTimeoutStTrig_A	751538390	77	0	0
ErrorStAllEscAsserted_A	751538390	1323	0	0
ErrorStIsTerminal_A	751538390	1113	0	0
u_state_regs_A	751538390	751381070	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	264	0	0
T13	17460	22	0	0
T14	34192	83	0	0
T15	84196	52	0	0
T46	0	31	0	0
T47	0	76	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	567	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T10	0	1	0	0
T17	616487	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	38	0	0
T10	292422	0	0	0
T11	289219	0	0	0
T12	960878	0	0	0
T22	334586	1	0	0
T45	0	1	0	0
T66	0	1	0	0
T90	56352	0	0	0
T93	6420	0	0	0
T94	15232	0	0	0
T95	21126	0	0	0
T96	99306	0	0	0
T107	77444	0	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	287	0	0
T1	15529	1	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T39	0	9	0	0
T40	0	6	0	0
T45	0	6	0	0
T78	0	1	0	0
T80	0	1	0	0
T84	0	1	0	0
T92	0	1	0	0
T101	0	1	0	0
T125	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751314551	318760710	0	0
T1	15529	13838	0	0
T2	80107	80032	0	0
T3	4951	1967	0	0
T4	678489	492582	0	0
T5	462753	8656	0	0
T7	4409	3100	0	0
T8	64947	16469	0	0
T23	3937	3229	0	0
T24	93503	3083	0	0
T25	20567	15316	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	678	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	667	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	652	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	630	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	1	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T26	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	888	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T22	0	1	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T26	0	1	0	0
T38	0	3	0	0
T39	0	10	0	0
T45	0	1	0	0
T95	0	3	0	0
T96	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	100537	0	0
T1	15529	669	0	0
T2	80107	0	0	0
T3	4951	25	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T22	0	7	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	212	0	0
T26	0	88	0	0
T38	0	544	0	0
T39	0	1282	0	0
T95	0	345	0	0
T96	0	30	0	0
T97	0	133	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	773	0	0
T1	15529	1	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T38	0	2	0	0
T39	0	5	0	0
T59	0	1	0	0
T88	0	1	0	0
T92	0	14	0	0
T95	0	2	0	0
T97	0	1	0	0
T100	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	77	0	0
T1	15529	1	0	0
T2	80107	0	0	0
T3	4951	1	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	1	0	0
T38	0	1	0	0
T39	0	5	0	0
T44	0	1	0	0
T60	0	1	0	0
T92	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1323	0	0
T13	17460	176	0	0
T14	34192	370	0	0
T15	84196	188	0	0
T46	0	207	0	0
T47	0	382	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1113	0	0
T13	17460	146	0	0
T14	34192	310	0	0
T15	84196	158	0	0
T46	0	177	0	0
T47	0	322	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	751381070	0	0
T1	15529	15430	0	0
T2	80107	80033	0	0
T3	4951	4881	0	0
T4	678489	678405	0	0
T5	462753	462745	0	0
T7	4409	4333	0	0
T8	64947	64870	0	0
T23	3937	3887	0	0
T24	93503	93405	0	0
T25	20567	20496	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T8,T23
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T23

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T8,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T23

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T8,T25
1	0	1	Covered	T23,T9,T55
1	1	0	Covered	T3,T26,T57
1	1	1	Covered	T8,T25,T57

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T57
0	1	Covered	T25,T39,T91
1	0	Covered	T78,T92,T63

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T8,T25,T57
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T78,T92,T63

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T25,T57
1	0	Not Covered
1	1	Covered	T25,T39,T91

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T5
1	Covered	T23,T25,T26

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T23
1	Covered	T1,T26,T38

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T23,T25
1	Covered	T1,T8,T5

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T23
1	Covered	T17,T19,T22

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T23,T5,T9

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T23,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T23,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T8,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T16
IdleSt	175	Covered	T16
Phase0St	146	Covered	T16
Phase1St	192	Covered	T16
Phase2St	209	Covered	T16
Phase3St	227	Covered	T16
TerminalSt	243	Covered	T16
TimeoutSt	153	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T16
IdleSt->Phase0St	146	Covered	T16
IdleSt->TimeoutSt	153	Covered	T16
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T16
Phase0St->Phase1St	192	Covered	T16
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T16
Phase1St->Phase2St	209	Covered	T16
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T16
Phase2St->Phase3St	227	Covered	T16
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T16
Phase3St->TerminalSt	243	Covered	T16
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T16
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T16
TimeoutSt->Phase0St	166	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T23
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T57
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T78,T39
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T57
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T8,T57,T38
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T39,T45,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T8,T23
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T8,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T39,T45
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T8,T23
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T8,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T61,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T8,T23
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T8,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T78,T39,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T8,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T8,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T8,T23
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	751538390	239	0	0
CheckAccumTrig0_A	751538390	599	0	0
CheckAccumTrig1_A	751538390	22	0	0
CheckClr_A	751538390	267	0	0
CheckEn_A	751314551	315242107	0	0
CheckPhase0_A	751538390	676	0	0
CheckPhase1_A	751538390	660	0	0
CheckPhase2_A	751538390	650	0	0
CheckPhase3_A	751538390	641	0	0
CheckTimeout0_A	751538390	750	0	0
CheckTimeoutSt1_A	751538390	99410	0	0
CheckTimeoutSt2_A	751538390	663	0	0
CheckTimeoutStTrig_A	751538390	65	0	0
ErrorStAllEscAsserted_A	751538390	1242	0	0
ErrorStIsTerminal_A	751538390	1032	0	0
u_state_regs_A	751538390	751381070	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	239	0	0
T13	17460	33	0	0
T14	34192	80	0	0
T15	84196	29	0	0
T46	0	32	0	0
T47	0	65	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	599	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	5	0	0
T7	4409	0	0	0
T8	64947	3	0	0
T9	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T23	3937	1	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	2	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	22	0	0
T50	0	1	0	0
T63	401891	1	0	0
T64	65923	0	0	0
T78	117037	1	0	0
T79	993631	0	0	0
T80	71664	0	0	0
T111	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	92890	0	0	0
T134	63547	0	0	0
T135	769720	0	0	0
T136	125462	0	0	0
T137	63594	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	267	0	0
T1	15529	1	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	4	0	0
T7	4409	0	0	0
T8	64947	2	0	0
T9	0	1	0	0
T12	0	1	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T26	0	1	0	0
T39	0	12	0	0
T45	0	11	0	0
T78	0	1	0	0
T83	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751314551	315242107	0	0
T1	15529	4356	0	0
T2	80107	80032	0	0
T3	4951	4880	0	0
T4	678489	678404	0	0
T5	462753	3082	0	0
T7	4409	3130	0	0
T8	64947	8814	0	0
T23	3937	3247	0	0
T24	93503	93404	0	0
T25	20567	615	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	676	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	5	0	0
T7	4409	0	0	0
T8	64947	3	0	0
T9	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T23	3937	1	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T26	0	2	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	660	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	3	0	0
T7	4409	0	0	0
T8	64947	3	0	0
T9	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T23	3937	1	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T26	0	2	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	650	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	2	0	0
T7	4409	0	0	0
T8	64947	3	0	0
T9	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T23	3937	1	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T26	0	2	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	641	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	2	0	0
T7	4409	0	0	0
T8	64947	3	0	0
T9	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T23	3937	1	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T26	0	2	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	750	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	1	0	0
T38	0	4	0	0
T39	0	1	0	0
T45	0	1	0	0
T57	0	2	0	0
T78	0	1	0	0
T84	0	1	0	0
T91	0	2	0	0
T97	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	99410	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	8	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	68	0	0
T38	0	668	0	0
T39	0	134	0	0
T45	0	66	0	0
T57	0	187	0	0
T78	0	3	0	0
T84	0	157	0	0
T91	0	962	0	0
T97	0	387	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	663	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T38	0	4	0	0
T45	0	1	0	0
T57	0	2	0	0
T84	0	1	0	0
T92	0	7	0	0
T97	0	2	0	0
T100	0	5	0	0
T101	0	1	0	0
T138	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	65	0	0
T6	530458	0	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T18	892985	0	0	0
T25	20567	1	0	0
T26	55579	0	0	0
T39	0	1	0	0
T42	32004	0	0	0
T44	0	2	0	0
T55	236122	0	0	0
T56	234033	0	0	0
T62	0	1	0	0
T91	0	2	0	0
T100	0	1	0	0
T102	36324	0	0	0
T133	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1242	0	0
T13	17460	163	0	0
T14	34192	368	0	0
T15	84196	180	0	0
T46	0	177	0	0
T47	0	354	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1032	0	0
T13	17460	133	0	0
T14	34192	308	0	0
T15	84196	150	0	0
T46	0	147	0	0
T47	0	294	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	751381070	0	0
T1	15529	15430	0	0
T2	80107	80033	0	0
T3	4951	4881	0	0
T4	678489	678405	0	0
T5	462753	462745	0	0
T7	4409	4333	0	0
T8	64947	64870	0	0
T23	3937	3887	0	0
T24	93503	93405	0	0
T25	20567	20496	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T8

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T36,T37
1	1	1	Covered	T1,T2,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T6,T9
1	1	0	Covered	T1,T8,T26
1	1	1	Covered	T8,T25,T19

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T19
0	1	Covered	T8,T39,T83
1	0	Covered	T38,T58,T60

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T8,T25,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T38,T58,T60

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T25,T19
1	0	Not Covered
1	1	Covered	T8,T39,T83

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T24
1	Covered	T2,T7,T6

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T8,T24,T9

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T42,T21,T57

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T8,T7
1	Covered	T1,T24,T26

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T24

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T8,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T26

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T16
IdleSt	175	Covered	T16
Phase0St	146	Covered	T16
Phase1St	192	Covered	T16
Phase2St	209	Covered	T16
Phase3St	227	Covered	T16
TerminalSt	243	Covered	T16
TimeoutSt	153	Covered	T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T16
IdleSt->Phase0St	146	Covered	T16
IdleSt->TimeoutSt	153	Covered	T16
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T16
Phase0St->Phase1St	192	Covered	T16
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T16
Phase1St->Phase2St	209	Covered	T16
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T16
Phase2St->Phase3St	227	Covered	T16
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T16
Phase3St->TerminalSt	243	Covered	T16
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T16
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T16
TimeoutSt->Phase0St	166	Covered	T16

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T38,T39
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T25,T19,T57
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T41,T141,T137
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T42,T142,T143
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T42,T144,T145
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T38,T39,T146
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	751538390	240	0	0
CheckAccumTrig0_A	751538390	846	0	0
CheckAccumTrig1_A	751538390	43	0	0
CheckClr_A	751538390	406	0	0
CheckEn_A	751314551	265057038	0	0
CheckPhase0_A	751538390	949	0	0
CheckPhase1_A	751538390	936	0	0
CheckPhase2_A	751538390	920	0	0
CheckPhase3_A	751538390	900	0	0
CheckTimeout0_A	751538390	1368	0	0
CheckTimeoutSt1_A	751538390	153341	0	0
CheckTimeoutSt2_A	751538390	1247	0	0
CheckTimeoutStTrig_A	751538390	78	0	0
ErrorStAllEscAsserted_A	751538390	1267	0	0
ErrorStIsTerminal_A	751538390	1057	0	0
u_state_regs_A	751538390	751381070	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	240	0	0
T13	17460	20	0	0
T14	34192	83	0	0
T15	84196	21	0	0
T46	0	43	0	0
T47	0	73	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	846	0	0
T1	15529	2	0	0
T2	80107	1	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	0	1	0	0
T7	4409	1	0	0
T8	64947	0	0	0
T9	0	1	0	0
T18	0	1	0	0
T23	3937	0	0	0
T24	93503	2	0	0
T25	20567	0	0	0
T26	0	1	0	0
T42	0	2	0	0
T56	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	43	0	0
T38	662328	1	0	0
T58	249041	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T75	20039	0	0	0
T76	238983	0	0	0
T77	574861	0	0	0
T78	117037	0	0	0
T79	993631	0	0	0
T80	71664	0	0	0
T88	112978	0	0	0
T89	21065	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	406	0	0
T1	15529	2	0	0
T2	80107	0	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	3937	0	0	0
T24	93503	1	0	0
T25	20567	0	0	0
T38	0	5	0	0
T39	0	3	0	0
T42	0	2	0	0
T57	0	6	0	0
T90	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751314551	265057038	0	0
T1	15529	9295	0	0
T2	80107	1970	0	0
T3	4951	1959	0	0
T4	678489	678404	0	0
T5	462753	462745	0	0
T7	4409	3071	0	0
T8	64947	54544	0	0
T23	3937	3196	0	0
T24	93503	14591	0	0
T25	20567	5396	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	949	0	0
T1	15529	2	0	0
T2	80107	1	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	0	1	0	0
T7	4409	1	0	0
T8	64947	1	0	0
T9	0	1	0	0
T18	0	1	0	0
T23	3937	0	0	0
T24	93503	2	0	0
T25	20567	0	0	0
T26	0	1	0	0
T56	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	936	0	0
T1	15529	2	0	0
T2	80107	1	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	0	1	0	0
T7	4409	1	0	0
T8	64947	1	0	0
T9	0	1	0	0
T18	0	1	0	0
T23	3937	0	0	0
T24	93503	2	0	0
T25	20567	0	0	0
T26	0	1	0	0
T56	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	920	0	0
T1	15529	2	0	0
T2	80107	1	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	0	1	0	0
T7	4409	1	0	0
T8	64947	1	0	0
T9	0	1	0	0
T18	0	1	0	0
T23	3937	0	0	0
T24	93503	2	0	0
T25	20567	0	0	0
T26	0	1	0	0
T56	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	900	0	0
T1	15529	2	0	0
T2	80107	1	0	0
T3	4951	0	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	0	1	0	0
T7	4409	1	0	0
T8	64947	1	0	0
T9	0	1	0	0
T18	0	1	0	0
T23	3937	0	0	0
T24	93503	2	0	0
T25	20567	0	0	0
T26	0	1	0	0
T56	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1368	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T19	0	2	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	5	0	0
T38	0	5	0	0
T39	0	9	0	0
T45	0	1	0	0
T57	0	13	0	0
T83	0	1	0	0
T95	0	4	0	0
T96	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	153341	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	753	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T19	0	80	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	993	0	0
T38	0	561	0	0
T39	0	2712	0	0
T45	0	31	0	0
T57	0	1344	0	0
T83	0	47	0	0
T95	0	466	0	0
T96	0	2132	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1247	0	0
T6	530458	0	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T18	892985	0	0	0
T19	0	2	0	0
T25	20567	5	0	0
T26	55579	0	0	0
T38	0	4	0	0
T39	0	6	0	0
T42	32004	0	0	0
T45	0	1	0	0
T55	236122	0	0	0
T56	234033	0	0	0
T57	0	13	0	0
T95	0	4	0	0
T96	0	11	0	0
T97	0	1	0	0
T99	0	1	0	0
T102	36324	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	78	0	0
T4	678489	0	0	0
T5	462753	0	0	0
T6	530458	0	0	0
T7	4409	0	0	0
T8	64947	1	0	0
T9	503009	0	0	0
T17	616487	0	0	0
T23	3937	0	0	0
T24	93503	0	0	0
T25	20567	0	0	0
T39	0	3	0	0
T40	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T83	0	1	0	0
T100	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1267	0	0
T13	17460	194	0	0
T14	34192	366	0	0
T15	84196	178	0	0
T46	0	172	0	0
T47	0	357	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	1057	0	0
T13	17460	164	0	0
T14	34192	306	0	0
T15	84196	148	0	0
T46	0	142	0	0
T47	0	297	0	0
T48	115695	0	0	0
T49	17304	0	0	0
T50	358855	0	0	0
T51	57014	0	0	0
T52	127383	0	0	0
T53	380176	0	0	0
T54	111231	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751538390	751381070	0	0
T1	15529	15430	0	0
T2	80107	80033	0	0
T3	4951	4881	0	0
T4	678489	678405	0	0
T5	462753	462745	0	0
T7	4409	4333	0	0
T8	64947	64870	0	0
T23	3937	3887	0	0
T24	93503	93405	0	0
T25	20567	20496	0	0