ALERT_HANDLER Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 54.120s 1.858ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 8.280s 106.870us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 9.360s 126.847us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 3.014m 11.885ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 2.507m 4.580ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 7.000s 238.221us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 9.360s 126.847us 20 20 100.00
alert_handler_csr_aliasing 2.507m 4.580ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 4.566m 10.465ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.182m 1.612ms 50 50 100.00
V2 entropy alert_handler_entropy 53.872m 230.017ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.143m 2.172ms 50 50 100.00
V2 clk_skew alert_handler_smoke 54.120s 1.858ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.027m 13.331ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.176m 1.293ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 10.826m 156.786ms 50 50 100.00
V2 lpg alert_handler_lpg 55.396m 128.433ms 50 50 100.00
alert_handler_lpg_stub_clk 53.152m 256.579ms 50 50 100.00
V2 stress_all alert_handler_stress_all 54.969m 568.845ms 49 50 98.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 1.283m 3.559ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.230s 55.087us 20 20 100.00
V2 intr_test alert_handler_intr_test 3.810s 71.816us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 23.980s 378.868us 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 23.980s 378.868us 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 8.280s 106.870us 5 5 100.00
alert_handler_csr_rw 9.360s 126.847us 20 20 100.00
alert_handler_csr_aliasing 2.507m 4.580ms 5 5 100.00
alert_handler_same_csr_outstanding 40.960s 3.278ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 8.280s 106.870us 5 5 100.00
alert_handler_csr_rw 9.360s 126.847us 20 20 100.00
alert_handler_csr_aliasing 2.507m 4.580ms 5 5 100.00
alert_handler_same_csr_outstanding 40.960s 3.278ms 20 20 100.00
V2 TOTAL 629 630 99.84
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 5.989m 22.435ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 5.989m 22.435ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 5.989m 22.435ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 5.989m 22.435ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 17.248m 16.507ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
alert_handler_tl_intg_err 1.334m 4.553ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.334m 4.553ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 5.989m 22.435ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 54.120s 1.858ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 54.120s 1.858ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 54.120s 1.858ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 54.120s 1.858ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.143m 2.172ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 55.396m 128.433ms 50 50 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.143m 2.172ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 53.872m 230.017ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 53.872m 230.017ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 37.560s 841.994us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.287h 190.460ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 849 850 99.88

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 14 93.33
V2S 4 4 4 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.65 99.99 98.65 99.97 100.00 100.00 99.38 99.56

Failure Buckets

Past Results